JPH0812930B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MES field effect transistor (hereinafter referred to as FET).

[0002]

2. Description of the Related Art A compound semiconductor such as GaAs having a high electron velocity is used for a microwave power FET.

FIG. 8 is a plan view showing an example of a conventional power FET.

Approximately 250 is formed on the surface of the semi-insulating GaAs substrate.
An n-type active layer 2A having an area of μm × 0.8 mm is provided and 4
Eight finger-shaped gate electrodes G (gate length 1 μm) are provided, and a source electrode S and a drain electrode D are arranged on both sides of each gate electrode. GP is a gate electrode pad connected to the gate electrode, SP is a source electrode pad connected to the source electrode, and DP is a drain electrode pad connected to the drain electrode.

If the maximum drain current Imax of the FET or the drain current I _DSS when the gate voltage is set to zero in the wafer state is measured and chips are to be selected, the measuring device easily emits, and the measurement is difficult. This is a FET
It is considered that this is due to the fact that the gm is large and the influence of the parasitic inductance and the parasitic capacitance of the measuring prober.

Therefore, a checking FET having a gate width of 200 μm to 1 mm is formed in the vicinity of the FET of the main body, and Imax or I _DSS of the checking FET is measured to select the chip 100. 2At, Gt
, GPt, DPt, and SPt are the active layer, gate electrode, gate electrode pad, drain electrode pad, and source electrode pad of the checking FET, respectively. In the case of the checking FET shown, the area of 2At is about 0.2.
5mm × 0.3mm, DPt, SPt area is about 0.1
mm × 0.24 mm. In the case of this example, the area of the chip 100 is
0.95mm x 0.8mm to about 1.25mm x 0.8
mm.

[0007]

In the conventional power FET described above, a check FET having a small gate width is arranged in the vicinity of the FET of the main body, but three pads (DPt, GPt and SPt of the check FET are provided. ) Occupies a certain area because it needs to be brought into contact with the measuring prober, so that there is a problem that the chip area becomes large.

A similar problem occurs in a semiconductor device such as an integrated circuit in which a plurality of power FETs are formed on the same chip together with a matching circuit.

[0009]

The present invention includes a MES field effect transistor having an active layer formed on the surface of a semi-insulating compound semiconductor substrate and a gate electrode deposited on the active layer. In the semiconductor device, a resistance layer formed independently of the active layer on the surface of the semi-insulating compound semiconductor substrate and having substantially the same impurity concentration and thickness as the active layer, and a resistance layer at both ends of the resistance layer, respectively. A check element having a connected measuring pad is provided.

[0010]

1 is a plan view of a chip showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG. 1, and FIG. 3 (a) is an enlarged plan view of a Z portion of FIG. FIG. 3B is A-A of FIG.
It is a line sectional view.

In this embodiment, instead of the checking FET in the conventional example described with reference to FIG. 8, a resistor formed in the same step as the active layer 2A and therefore having substantially the same impurity concentration n and pressure t. A check element having a layer 2R and measuring pads 5R1 and 5R2 provided at both ends of the resistance layer 2R is provided.

Next, the manufacturing method of this embodiment will be described.

Impurity concentration of 1 × 10 ¹⁷ cm is obtained by implanting Si ions into the surface of the semi-insulating GaAs substrate 1 and performing heat treatment.
^-3, 200 nm thick N-type active layer 2A and resistive layer 2
Form R. The area of the active layer 2A is about 250 μm × 0.
8 mm, the area of the resistance layer 2R is about 70 μm × 0.65 mm
Is.

Next, a tungsten silicide film 3 having a thickness of 80 nm is deposited and patterned to form a finger-shaped gate electrode G (width 1 μm) 48 across the surface of the active layer 2A.
Form a book. Next, a photoresist film having a predetermined opening is formed, an Au—Ge alloy film having a thickness of 150 nm is formed by a vapor deposition method, and a Ni film having a thickness of 40 nm is subsequently formed, and lift-off is performed to perform ohmic electrode 4D. , 4S, 4R2 are formed. Next, a silicon oxide film having a thickness of 1 μm is deposited, flattening treatment is performed by an etch back method, and 400 nm of silicon oxide is deposited again to form an insulating film 6. Next, by providing a predetermined opening and performing gold plating, the ohmic electrode 4S,
Gold film (5S, 5D, 5R1, 5 connected to 4D, 4R2
R2) and electrode pads SP, GP, DP are formed.
The size of the measuring pads 5R1 and 5R2 of the check element is about 100 μm × 100 μm.

Next, in the wafer state, the measuring pad 5R
The probe is brought into contact with 1, 5R2, the sheet resistance of the check element is measured, the defective chip is marked with an inker, pelletized, and the mounting process proceeds.

FIG. 4 is a graph showing the correlation between the maximum current Imax of the FET of the main body and the sheet resistance R _N of the check element in this embodiment. Gate width 100 μm on vertical axis
The maximum current Imax is shown. The number of samples measured is 4
It is 2. The regression line is as follows.

Imax = 61.250−0.031 × R _N The area of the chip 100a of this embodiment is about 1.08 × 0.8.
mm, and a reduction of about 14% was achieved compared to the conventional example.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

In this embodiment, a tungsten silicide film 3R (having a width substantially the same as that of the resistance layer 2R) is provided on the surface of the resistance layer 2R and connected to the ohmic electrode 4R1a. Therefore, by applying a ground potential to the measuring pad 5R1 and applying a positive potential to the measuring pad 5R2 and measuring the current flowing between 5R2 and 5R1, the I of the FET of the main body is measured.
It can be used as a guide for _DSS (drain current when the gate potential is zero). The check element of this embodiment is FE
Since it is T, there is an advantage that data more closely related to the FET of the main body can be obtained as compared with the case where a resistance element is used, and in that sense, more accurate selection can be performed.

FIG. 6 is a plan view showing a second embodiment of the present invention, and FIG. 7 is a sectional view taken along the line AA of FIG.

In this embodiment, the resistance layer 2Ra is arranged below the drain electrode pad DP, and the measuring pads 5R1 and 5R2 of the check element are arranged near both ends of the drain electrode pad DP. Since the area occupied by the check element can be made small, when used as one of the power FETs as a constituent element of the monolithic integrated circuit, there is an advantage that the degree of integration can be improved. In this embodiment, similarly to the second embodiment, one of the measurement pads 5R1 and 5R2 is provided by providing the surface of the resistance layer 2Ra with a tungsten silicide film formed of the same material and in the same process as the gate electrode of the FET of the main body. It is also possible to connect to one side.

Although the case where GaAs is used as the semiconductor material has been described above, it will be apparent to those skilled in the art that other compound semiconductors such as InP can be used. Further, an impurity diffusion layer having a higher concentration than the active layer may be used as the drain region.

[0023]

As described above, the present invention provides a two-terminal check element in which a measurement pad is connected to both ends of a resistance layer having substantially the same impurity concentration and thickness as the active layer of the MES field effect transistor. Since such a check element is provided, there is an effect that the chip area can be reduced as compared with a check element provided with a small MES field effect transistor.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

3 is an enlarged plan view (FIG. 3 (a)) and a sectional view (FIG. 3 (b)) of a Z portion of FIG.

FIG. 4 is a graph showing the relationship between Imax and RN in the first embodiment.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

FIG. 6 is a plan view showing a third embodiment of the present invention.

FIG. 7 is a sectional view taken along line AA of FIG. 6;

FIG. 8 is a plan view showing a conventional example.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2A, 2At active layer 2R, 2Ra resistance layer 3 tungsten silicide film (gate electrode) 4D, 4R1, 4R2, 4S ohmic electrode 5D, 5R1, 5R2, 5S gold film (electrode pad) 6 insulating film D Drain electrode DP, DPt Drain electrode pad G Gate electrode GP, GPT Gate electrode pad S Source electrode SP, SPt Source electrode pad 100, 100a, 100b Chip

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/66 Y 7514-4M 29/80

Claims (3)

[Claims] 1. A semiconductor device including an MES field effect transistor, comprising: an active layer formed on a surface of a semi-insulating compound semiconductor substrate; and a gate electrode deposited on the active layer. A resistance layer independently formed on the surface of the semi-insulating compound semiconductor substrate and having substantially the same impurity concentration and thickness as the active layer, and measurement pads respectively connected to both ends of the resistance layer. A check element having a resistance layer and the resistance layer having the MES field effect.
Provided under the drain electrode pad of the transistor
Wherein a is. 2. The semiconductor device according to claim 1, wherein a film made of the same material as that of the gate electrode is deposited on the resistance layer and is connected to either one of the two measurement pads. 3. The compound semiconductor is GaAs.
Alternatively, the semiconductor device according to item 2.