JPH081561B2 - Programmable controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a programmable controller that incorporates a counter that counts an externally input clock and that cyclically performs input, execution of a user program, and output. .

[Conventional technology]

In a programmable controller having a counter that takes in a clock input from the outside and counts it, a method of comparing the current value of the counter with a set value and outputting the same has been conventionally performed by software.

Therefore, when scanning the input, the execution of the user program, and the output as one cycle, the output is performed depending on this scan time. Therefore, when the current value of the counter reaches the set value and when it is output, In addition, a deviation of several count clocks occurs.

When the counter of such a programmable controller is used, for example, when measuring a fixed length, a delay in comparison output causes an error in the measurement.

This means that the higher the counter is, the larger the deviation of the count value at the time of output and the larger the measurement error.

[Problems to be Solved by the Invention]

In view of the above problems, the present invention compares a count value of a counter with a set value in a programmable controller having a counter that counts clock inputs, generates an output when they match, and shifts the count value. It is an object of the present invention to provide a programmable controller capable of eliminating the error and preventing the occurrence of an error and performing accurate measurement.

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention has a ROM for storing a control program and the like, a RAM for storing a user program, input / output data and the like, and a user program execution means for inputting data and a user program. In a programmable controller that cyclically executes and outputs, a data input unit from the outside, a counter that counts an input clock from the data input unit, and a current value of the counter is compared with a set value and a result is output. And a comparison output control means for controlling the output of the comparison means from a user program, and an output means driven by the output from the comparison output control means.

[Action]

The programmable controller according to the present invention has the above-described configuration, and when the counter value counted by the counter and the set value match, the comparison output control unit is controlled from the user program to drive the output unit to reduce the output error. Lost
It is an accurate measurement.

〔Example〕

 The details of the present invention will be described based on illustrated embodiments.

FIG. 1 is a simplified block diagram of an embodiment of a programmable controller according to the present invention.

In the figure, reference numeral 1 denotes a central processing procedure (hereinafter referred to as CPU) for executing a user program and controlling data input / output.

Reference numeral 2 is a ROM that stores control programs and the like, and 3 is a RAM that stores user programs, input / output data, and the like.

Reference numeral 4 is data input means from the outside, and 5 is output means provided with an output relay and the like.

Reference numeral 7 is a counter that counts the data input from the input means 4, and is controlled by a clock signal and a reset signal input by the counter control circuit 6.

Reference numeral 8 is a comparison means for comparing the current value of the counter input from the counter 7 with a set value and outputting the result to the comparison output control means 9.

The comparison output control means 9 outputs the comparison result of the comparison means 8 to the CPU 1
Is output from the output means 5 by being controlled by the user program.

Reference numeral 10 is a chip select circuit that generates a select signal.

FIG. 2 is a main part explanatory circuit of the present invention, and FIG. 3 is a ladder chart showing an example of a user program used in the present invention.

In the programmable controller of the present invention, CTR86, C
It has two counters of TR87, and the data selection means 14
The current value data of the two counters is selected by the data selector 11 of.

These counters CTR86 and 87 are set in the user program and are instructions for operating the auto-reset-up counter from 1 to the set value. They have fixed clock input and reset input and are input from the user program. It has possible ENB input and reset input.

The count value of this counter is incremented by 1 when the ENB input is turned ON and the clock input is turned from OFF to ON, and the count value becomes 0 when either hardware or software reset is turned ON.

Then, the output turns on only for the next one scan that has been counted up.

For example, the CTR86 shown in FIG. 3 is automatically reset when the ENB input is ON and the clock is counted up to the count value 20.

Further, the programmable controller of the present invention has instructions CTR88 to 95 for comparing the current value of the high speed counter with the set value. When the OVE input is ON and the set value is equal to or less than the current value, the address No. 0500 to 0507 is set. Output of one of the contacts of
When the input is ON and the set value ≤ the current value <the set value of the next No counter, one of the contacts No. 0500 to 0507 is output.

In Figure 3, CTR88 has OVE input ON and OLE input O
It is FF, and when the counter value of the counter CTR86 reaches 6, it outputs to the output relay No. 0500.

As shown in FIG. 2, the data selector of the data selecting means 14
The current value of the count value of CTR86 selected by 11 is
It is input to the input A of the comparator 12 of the comparison means 8.

Here, B to which the set value of CTR88 is given is compared with the above-mentioned input A and the current value of the counter CTR86 immediately, and when the coincidence or the count value is larger, the comparator 12 causes the comparison output control means. Generate output to 9.

The output control circuit 13 of the comparison output control means 9 is the comparator.
Driven based on 12 outputs, but OVE input of CTR88 is O
Since the N and OLE inputs are OFF, the output control circuit 13 turns ON the contact of CTR88 and the output relay No.0550.

Since the contact of CTR88 is on the software of the user program, it is turned on by being taken in during the scan time of the programmable control, which causes a delay from the time when the actual comparison coincides and the measurement error similar to the conventional example. Is caused.

Here, the output relay No. 0500 is connected to the external terminal and is driven and output by the output control circuit 13 when the comparator 12 is turned on, so there is no delay depending on the scan time. It is a thing.

I used it with OVE input ON and OLE input OFF of CTR88,
If this is changed, the output can be changed using the same comparator.

Further, since the CTRs 88 to 95 are provided as comparators, the output method can be changed by changing the output control circuit 13, and a more complicated output method is also possible.

〔The invention's effect〕

The programmable controller according to the present invention is configured as described above, and controls the comparison output control means for comparing and outputting the count value counted by the counter with the set value. It eliminates the error.

This eliminates the delay in the output due to the scan, and enables accurate measurement.

Further, even if the built-in counter is operated at a high speed, it is possible to output accurately.

[Brief description of drawings]

FIG. 1 is a simplified block diagram of an embodiment of a programmable controller according to the present invention, FIG. 2 is a circuit diagram for explaining main parts of the present invention, and FIG. 3 is a ladder chart showing an example of a user program used in the present invention. is there. 1: CPU, 2: ROM, 3: RAM, 4: Input means, 5: Output means, 6: Counter input control means, 7: Counter, 8: Comparison means, 9: Comparison output control means, 10: Chip select circuit , 11: data selector, 12: comparator, 13: output control circuit, 14: data selection means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Taiji Kuki 2-13, Akedacho, Takatsuki-shi, Osaka, inside Keyence Co., Ltd. (72) Inventor Shigeaki Tani, 2-13 Akedacho, Takatsuki-shi, Osaka Keyence, Inc. (56) References JP-A-62-256102 (JP, A) JP-A-63-116210 (JP, A) JP-A-61-161507 (JP, A)

Claims (1)

[Claims] 1. A ROM for storing a control program and the like, a RAM for storing a user program, input / output data and the like, and a user program execution means for cyclically inputting data, executing the user program and outputting the data. In the programmable controller, the external data input means, a counter for counting the input clock from the data input means, a comparison means for comparing the current value of the counter with a set value and outputting the result, A programmable controller comprising: comparison output control means for controlling the output of the means from a user program; and output means driven by the output from the comparison output control means.