JPH0816895B2 - Data transfer device - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to data transfer devices, and more particularly to the use of expansion cards in computer systems.

[0002]

2. Description of the Related Art Generally, in a computer system, especially in a personal computer system, data is stored in various elements such as a central processing unit (CPU), an input / output (I / O) adapter, and an I / O.
/ O device, bus controller (ie, bus master or computer such as direct memory access (DMA) controller and DMA slave)
Elements that control the system) and elements such as memory devices such as system memory. These elements are often connected via a system bus that is part of the system architecture. The architecture is designed to allow data and address and command information to move within or between the above elements. In personal computer systems, some of these architectures have become the industry standard, known as the Family I or IBM / AT bus architecture.

The Family I bus architecture is a personal computer such as an 8-bit IBM PC and a 16-bit PC / AT.
It is becoming more widely used by computers. This Family I bus architecture uses 8 parallel paths (8-bit wide bus) or 16 parallel paths (16-bit wide bus) to transfer information. This Fami
The key features of the ly I bus architecture are:
There is a requirement that all transfers be performed in synchronization with one basic clock signal called the K signal. The CLK signal is an 8 MHz signal and is supplied to all the elements connected to the bus.

The widespread use of the Family I bus architecture has made it more convenient to extend it to a 32-bit wide format. However, some users have
Some want to maintain backward compatibility with the Family I bus architecture. One such extended Family I architecture is the Extended Industry Standard Archi
tecture (EISA). This EISA is EISA Specificat
ion, BCPR Services, Inc. (1989).

As another architecture, Micro Channe
The l (trademark of IBM Corporation) architecture is commercially available. This Micro Channel provides a 32-bit format that is not compatible with the Family I architecture.

[0006]

SUMMARY OF THE INVENTION Here, a connector configured for connection with an EISA type bus and a Micro Chan
A connector configured for connection with a nel-type controller element, and converting an input signal conforming to EISA into an input signal conforming to Micro Channel architecture and Micro Ch
It is known that elements according to the Micro Channel architecture can be used in EISA-compliant systems by using an adapter comprising an output signal according to the annel architecture and a circuit configured to convert the output signal to an EISA-compliant output signal.

It is therefore an object of the present invention to provide an apparatus for transferring data between a computer system having a first architecture and a controller element having a second architecture.

[0008]

In order to achieve the above object, a data transfer apparatus according to the present invention comprises a first connector corresponding to a first architecture and a second connector corresponding to a second architecture. And a conversion circuit arranged between the first connector and the second connector. The conversion circuit converts a signal corresponding to the first architecture into a signal corresponding to the second architecture,
Signal corresponding to the first architecture is converted into a signal corresponding to the first architecture.

In the specification and the accompanying drawings, the symbol # indicates an active low signal,
All 16-bit addresses are given in hexadecimal notation.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT As shown in FIGS. 1 and 2, a computer system 10 comprises a system board 12 having system control circuitry and a CPU and memory, and a bus compliant with the first architecture, preferably EISA. 16 and a plurality of expansion slots 18 connected to the bus 16. The computer system 10 further includes expansion cards 20a, 20b, 20c (collectively referred to as "20") conforming to a second architecture, preferably the Micro Channel architecture, expansion cards 21 and expansion cards 20a conforming to EISA. , 20b, 20c mechanically and electrically connecting the expansion slots 18 of the board 12 with the adapters 22a, 22b, 22c (collectively referred to as "22"). Computer system 1
It is understood that the 0 is not limited to this configuration and can include any combination of expansion cards 20,21.
The combined height of the adapter 22 and the expansion card 20 is less than or equal to the height of the expansion card 21, and thus the combined adapter 22 and expansion card 20
It can be applied to a computer designed for the expansion card 21.

Each adapter 22 includes a Micro Channel connector 24, which supports the Micro Channel architecture,
EISA connector 26 corresponding to EISA, and Micr
An interface conversion logic circuit 28 (28a, 28b, 28c) for converting a signal conforming to the Channel architecture into a signal conforming to the EISA and vice versa. The interface conversion logic circuit 28 may be the expansion card 20 is a slave card 20a or a controller card such as a master card 20b, or a DM.
It changes depending on the A slave card 20c. The controller card can gain control of the bus 16 via arbitration.

Referring to FIG. 2, the interface conversion logic circuit 28b for the adapter 22b is configured to adapt the Micro Channel controller cards 20b, 20c to the bus 16, and further includes an initialization circuit 30, an address translation circuit 32, Data translation circuit 34 and arbitration circuit 35
It has. The initialization circuit 30 receives the EISA initialization signal and the control signal, and further converts these signals.
Provides Micro Channel initialization and control signals. The address translation circuit 32 receives the EISA address information, converts it into Micro Channel address information, and further
The icro Channel address information is converted into EISA address information. The data translation circuit 34 receives the EISA data transfer control information, converts it to Micro Channel data transfer control information, further receives the Micro Channel data transfer control information, and converts it to EISA data transfer control information. The arbitration circuit 35 receives the EISA arbitration information, and receives the Micro
It gives Channel arbitration information, receives Micro Channel arbitration information, and gives EISA arbitration information.

Further, the interface conversion logic circuit 28b.
Provides a direct connection between the EISA control signal and the Micro Channel control signal. The direct connection control signal includes an oscillator signal (OSC) and a reset signal (C for Micro Channel).
RESDRV for HRESET and EISA),
Error reporting signals (CHCK # for Micro Channel and IOCHK # for EISA) and interrupt request signals (I for both Micro Channel and EISA).
RQ3-7, 9-12, 14, 15). Since the system control circuit 14 is programmed to receive the interrupt signal shared active low on the interrupt line used by the expansion card 20, the interrupt request signal is directly connected.

Referring now to FIGS. 1 and 3, each Micro Channel expansion card 2 using an initialization circuit 30.
0 is initialized. Initialization of computer system 10 with Micro Channel expansion card 20 and EISA card 21 is a multi-step process. The system control circuit 14 first requests a first identification (ID) signal from each expansion card of the system 10. Each expansion card 21 provides a 32-bit EISA identification signal. Each adapter 22 also responds to the system 10 with a 32-bit interface conversion logic ID signal indicating the presence of a Micro Channel card in the system 10. The system control circuit 14 then requests the Micro Channel slot ID signal from the slot containing the Micro Channel card, and the 16-bit Micr from each expansion card 20 of the system 10.
o Receive channel expansion card ID signal. Therefore,
The system control circuit 14 will have an ID for each expansion card 20, 21 of the system 10.

Next, the system control circuit 14 calls a configuration program which initializes the identified card. This configuration program can be stored on diskette or in non-volatile RAM.

More specifically, the initialization address used to request the first slot ID signal is X.
C80-XC83 (X is associated with a particular slot 18 of system 10) and each of the four addresses requires one byte of the four byte ID signal. The system control circuit 14 sends the first initialization address to a specific slot by sending an address enable (AENX #) signal unique to each slot. The match between the AENX # signal and the negation signal of the memory or I / O display signal (M-IO) indicates to the slot that the I / O operation scheduled for this slot has been started on the bus 16. It means that. Address signal is decoded by AND gate 40 Address bits 8, 9, 1
If 0 and 11 contain the value "C" (ie, "1100") and at the same time the AENX # signal and the negation of the M-IO signal match, then the address is the slot that the adapter 22 requires to respond. Recognized as a unique address and therefore active adapter response signal (A
DRESP) is given. The system control circuit 14
When the START # signal is activated to indicate the start of the transfer, the ADRESP signal is provided to the flow register 42 and latched to provide the LADRESP signal.

The 4-byte ID signal is provided by the initialization circuit 30. At this time, the ID signal is given byte by byte through the eight 4-to-1 multiplexers 44.
Each multiplexer 44 produces one bit of data and is connected to a respective data line (D0-D7) of the bus 16. The latched address bits LA0 and LA1 act as multiplexer select signals, which are provided by an address latch and decode circuit (ADDR LCH & DEC) 46 based on the two lower address bits of addresses XC80-XC83.
That is, the bits LA0 and LA1 select which byte is read from the ID circuit 48. ID
Circuitry 48 is physically hardwired into a specific 32-bit pattern that uniquely defines the ID signals of all adapters 22.
The ID signal determined by the ID circuit 48 is the Micro Chan.
nel controller cards 20b and 20c are adapters 2
The system control circuit 14 is instructed to be connected to a specific slot 18 via 2.

Address latch decode circuit 46 is also used to latch and store the eight low order address bits and decode address bits A2-A7 so that the two low order bytes of the address signal are 80 and 83. Address signal (IDADDR) that specifies when
give. The IDADDR signal is A7, A6 #, A5.
#, A4 #, A3 #, and A2 # are ANDed.

The multiplexer 44 is a tristate
A driver is provided which drives the data lines D0-D7 and provides the first ID signal on the bus 16 byte by byte.
When the data transfer control circuit 34 gives an active read operation instruction signal (READ) at the same time as an active data transfer signal (CMD #), an active LADRESP signal, and an active ID ADDR signal,
The tristate driver is enabled by NAND gate 50. The CMD # signal is data on the bus 16
Is a signal supplied from the system control circuit 14 for instructing that it is being supplied to the device. The system control circuit 14 receives the first I provided by the multiplexer 44.
Read 4 bytes of D signal.

Next, the system control circuit 14 causes the slot-specific I / O addresses X000 and X001 (Micro Ch
(1 address for each byte of annel ID signal)
To issue a Micro Channel ID signal read command. The initialization circuit 30 receives the I / O address and instructs the address translation circuit 32 to generate the Micro Channel initialization addresses 0100 and 0101. Micro Chan
The nel expansion card 20 is in the range of 0100 to 0107 and has a slot-specific setup signal (CD SETUP).
The I / O address issued at the same time as #) is interpreted as an initialization command (called a Power-on Option Select (POS) command).

The CD SETUP # signal indicates that a slot-specific I / O address is given to the expansion card 20. These slot-specific I's sent by the system control circuit 14 to read the Micro Channel ID signal.
The / O address is 0000 to 000 together with the AENX # signal.
It is in the range of 7. The address translation circuit 32 detects the slot-specific addresses generated by the system control circuit 14 and adjusts bit 8 of these addresses to provide the expansion card 20 with an address in the range 0100-0107. The CD SETUP # signal that identifies the POS command to the Micro Channel card 20 is the negative of the ADRESP signal, the LA8 and LA9 signals (these are EISA).
(Which identifies the slot unique address at.), A negative signal on the AENX # signal, and a negative signal on the M-IO signal.

Further, the initialization circuit 30 determines whether the address given to the bus 16 is unique to the slot. E
The ISA defines I / O addresses that are not slot-specific as general I / O addresses. All expansion cards 20 of the system 10 are general I / O submitted to the bus 16.
Decode the address to determine if it is within the specified range of responses for the card. The interface conversion logic circuit 28 detects general I / O addresses and sends them to the expansion card 20 via the address translation circuit 32. Expansion card 20 uses these general I / O
Decode addresses and respond to them as needed. The NOR gate 51 uses the ADRESP signal and the CD
General I / O when the negative signal of the SETUP # signal is received and the address given to the bus 16 is not slot specific
An address signal (GEN I / O) is generated. ADRE
Either the SP signal is high (indicating that the address is the first initialization address) or the negation signal of the CD SETUP # signal is high (indicating that the address is the second initialization address). , This address is slot specific.

Upon receiving the POS command, the expansion card 20a returns the 2-byte ID code directly to the system control circuit 14. Next, the system control circuit 14 uses two I's.
D (32-bit ID from interface conversion logic 28 and 16-bit Micro Chan from expansion card 20)
nel ID) to give a unique Micro Channel card identifier.

Referring to FIG. 4, initialization circuit 30 further generates four control signals based on information from system control circuit 14 and each expansion card 20 provided at configuration time. These control signals include a signal (FORCE89) for controlling bit 8 and bit 9 to "0",
Master / slave control signals (MASTER and SLA
VE), master bit size control signal (16MAS
L * 32 MASL), and a fast end enable control signal (FAST TERM).

The FORCE89 control signal is a Micro Channel
Required because the card 20 may have a physical hardwired general I / O address range that is not within the EISA general I / O range (addresses with bits 8 and 9 0 as defined by EISA). It is a slot-specific address and cannot be a general I / O address.) Therefore,
If during system initialization the system control circuit 14 determines that the expansion card 20 has a physically hardwired general I / O address range that requires bits 8 and 9 to be 0, then the system The control circuit 14 uses the initialization circuit 32.
The 4-bit control register (CTL REG) 55 can be written and read. Control register 55
Provides the FORCE89 control signal.

More specifically, in the control register 55 of the initialization circuit 30, the control register 55 is a NAND gate 56.
When the system control circuit 14 sets the data line D7 while enabled by, it sets the FORCE89 signal. NAND gate 56, along with the active LADRESP signal, the active CMD # signal, and the active WRITE signal (the active CNTR provided by address latch decode circuit 46 when all eight lower address bits are low).
When the I / O address XC00 is provided by the system control circuit 14 (as indicated by the L REG ADDR signal), the control register 55 is enabled. To allow the system control circuit 14 to read,
The FORCE 89 signal is provided to tristate driver 57 which is enabled by NAND gate 58. The NAND gate 58 is a CNTRLREG ADDR.
Signal, LADRESP signal, CMD # signal, and RE
Receive an AD signal. In this way, the control register 55
Is enabled to be read, the tri-state driver 57 is also enabled and the FORC
If the E89 signal is sent on line D7 on bus 16 and control register 55 is not enabled for reading,
Tristate driver 57 is also not enabled, and F
The ORACLE 89 signal is also not sent on line D7 on bus 16. The FORCE 89 signal is supplied to the address translation circuit 32.

The MASTER and SLAVE control signals are set during configuration and serve to indicate whether the expansion card 20 interfacing with the translation logic 28 is a master or a slave. These MASTER and SLAV
The E signal is written via the EISA data line D6,
Is read.

When the expansion card 20 is the master, 16M
The ASL and 32MASL control signals further define whether the expansion card 20 is a 16-bit master or a 32-bit master. These 16 MASL and 32 MASL control signals are written and read via the EISA data line D4.

FAST TERM signal is PREMP
In some cases it may be necessary to terminate ownership of the bus sooner than can be achieved by the T # signal.
is necessary. FAST TERM signal for expansion card 2
A 0 indicates whether bus ownership can be preempted faster by responding to the inactivation of the ARB / GRANT signal than by responding to the activation of the PREEMPT # signal. This FAST T
The ERM signal is written and read via the EISA data line D5.

Referring to FIGS. 5 and 6, address translation circuit 32 translates addresses during initialization as well as during normal operation of computer system 10.

During initialization, the address translation circuit 32
Address bits LA12-LA for selecting slot X
15 predicts an address between 0100 and 0107,
Therefore, it is ensured that these 4 bits are not directly given to the expansion card 20 which predicts that they are 0. Therefore, the AND gates 61 and 6 of the address translation circuit 32
2, 64 and 66 are Micro Channel address bits A12 when the CD SETUP # signal is active.
~ Set each A15 low.

Further, during the first step of initialization,
Address translation circuit 32 ensures that address bit A8 is high. Therefore, OR gate 67 drives address bit A8 high when the CD-- SETUP # signal is active. After initialization and during normal operation of the computer system 10, the address translation circuit 32 transfers the EISA address information to the Micro Ch
Either the conversion to the annel address information or the conversion to the Micro Channel address information to the EISA address information is performed. The EISA address information includes 30-bit EISA address signals (LA2-LA23, LA24 #
-LA31 #) and the next transfer control signal, that is, a memory or I / O control signal (M-IO) indicating whether the related address is a memory address or an I / O address (memory address when "1") , A write or read transfer signal (WR) indicating whether the transfer operation is a write operation or a read operation (a write operation when it is "1"), and which of the 4 bytes in the 32-bit word should be written, or A 4-bit byte enable signal (BE) indicating whether it should be read (the byte is enabled when it is "0").
O # -BE3 #) is included. The 32-bit Micro Channel address signal (A
0-A31) and the next Micro Channel transfer control signal,
That is, the transmission byte high enable signal (SHBE
#), Address / bit width display signal (MADE24),
4-bit Micro Channel byte enable signal (BE
O # -BE3 #), write operation start control signal (SO
#), A read operation start control signal (S1 #), and an address latch signal (ADL #).

Referring to FIG. 5, there is shown an address translation circuit 32 for converting EISA address information into Micro Channel address information. Micro Channel Card 2
All Micro Channel address information given to 0 is
The master-owned bus signal (M
Driven through address tristate gate 68 enabled by ASTER OWNS BUS #). Therefore, when the master 20b does not own the bus 16, the Micro Channel card 2 is accessed through the gate 68.
The address information is given to 0b, and the master 20b receives bus 1
When owning 6, the output of gate 68 is left floating. Further, the DMA slave-owned bus signal (DSLAVE O provided by the arbitration circuit 35
IBM Personal Sy when WNSBUS) is active
As specified in the stem / 2 Hardware Interface Technical Reference Manual, the address translation circuit 32 uses Micr
o Set the channel address signal to 0000.

When the FORCE 89 signal is set, the address translation circuit 32 provides the MicroChannel card 20 with a general I / O address with bits 8 and 9 of zero. That is, the FORCE 89 signal is applied to the NAND gate 59, which further generates the GEN I / O signal,
It receives a negative signal of the AENX # signal and a negative signal of the M-IO signal. NAND gate 59 is AND gate 54
AND AND 60 the active low force address bits 8 and 9 to 0 signal (FAB
Give TZ #). The FABTZ # signal, when active, causes AND gates 54 and 60 to drive the A8 and A9 signals low, respectively.

The byte enable decode logic circuit 70 of the address translation circuit 32 uses the EISA byte enable signal to generate the Micro Channel address signal (A0,
A1) and the two lower bits of the SHBE # signal are provided. No conversion is required for the byte enable signal, and the EISA byte enable signal is provided to expansion card 20b via gate 68.

16 bits of EISA address signal (LA
2-LA7, LA10, LA11, LA16-LA2
No conversion is required for 3) and these 1
6 bits are Micro Channel address signals (A2-A7,
Expansion card 2 as A10, A11, A16-A23)
It is given directly to 0.

Eight high EISA address bits (L
A24 # -LA # 31) is NO because EISA uses the address bits and Micro Channel requires that this portion of the address signal be active high.
Eight Top Micro Chans Negated Via R Gate 79
nel address bits (A24-A31). N
Other input signals to the OR gate 79 are DSLAVE.
This is the OWNS BUS signal. These LA24 # ~ L
The A31 # address bits are also AND gate 80
And is used by the Micro Channel expansion card 20 to provide a 24-bit indicator signal (MADE 24) that determines whether the expansion card utilizes the Micro Channel 24-bit addressing option. The MADE 24 signal is activated when all eight EISA high address bits are inactive.

FIG. 6 shows a circuit for translating the Micro Channel address information into EISA address information.

The 30-bit wide data register 81 is M
ASTER OWNS BUS signal and HOLD A
It is enabled and disabled by the DDRESS signal. OR gate 82 drives the eight high order address bits (LA24 # -LA31 #) high when the MADE 24 signal is active indicating that expansion card 20b is presenting a 24-bit wide address signal. OR gate 82 negates the eight upper address bits when the MADE24 signal is low. The HOLD ADDRESS signal is generated by the RS latch 83 and the AND gate 84. The Micro Channel address bits are
Flow through register 81 until the ADL # signal goes low. These Micro Channel address bits are then latched and held until both the CMD # and BCLK signals go low (up to half to the data transfer portion of the sequence as shown in FIG. 10).

Micro Channel byte enable conversion circuit 85 uses the Micro Channel byte enable signal for 32 bit transfers and the A0, A1 and SBHE # signals for 8 and 16 bit transfers. Generate the EISA byte enable signal. Two lower Micro Channel address bits (A0 and A
1) and an EISA byte instead of the SBHE # signal
The enable signal is used. The EISA byte enable signal is buffered in the 4-bit flow register 86, which is latched by the HOLD ADDRESS signal, and the MASTER OWNS signal.
BUS signal and MISMATCH DELAYED #
Tristate enabled by signals (provided by arbitration circuit 35) and these signals are ANDed by AND gate 87. All EISA address information provided on bus 16 is MASTER OWNS BU.
It is enabled by the tristate registers 81 and 86 based on the S signal.

Referring now to FIGS. 1, 7 and 10, for transfers in which expansion card 20 acts as a slave, system control circuit 14 or master 20b:
EISA data transfer is initiated via bus 16 by providing EISA address information (ADDRESS1) on bus 16 for at least 10 ns before the rising edge of the BCLK signal and the falling edge of the START # signal. This E
The ISA address information includes a 30-bit address system and a next transfer control signal, that is, a memory or I / O control signal (M-IO) ("1" indicating whether the related address is a memory address or an I / O address). , Memory address), write or read transfer signal (WR) indicating whether the transfer operation is a write operation or a read operation (write operation when "1"), and which of the 4 bytes in a 32-bit word A 4-bit byte enable signal (BEO-B) that indicates whether the data is to be written or read.
E3 #) is included.

The Micro Channel expansion card 20 has a write operation start control signal (SO #), a read operation start control signal (S1 #), and an address latch signal (ADL).
#) Is required to start the data transfer. The data transfer control circuit 34 uses the START # signal and the BLCK signal together with the M-IO signal, the WR signal, and the ADRES signal.
The P signal is used to provide the SO #, S1 #, and ADL # signals.

That is, the NAND gate 90 has the XOR
An exclusive OR of the WR signal and the DSLAVE OWNS BUS signal, as provided by gate 93,
The negative signal of the ADRESP signal, the negative signal of the START # signal, and the negative logical product of the transfer control signal (TRANS) are taken to give the S0 # signal. The XOR gate 93 is
The WR signal is negated when the DSLAVE OWNS BUS signal is active. TRANS signal is AENX #
NAN from the logical product of the signal and the negative signal of the M-IO signal
Provided by D-gate 91, so TRANS is Micr
o It shows the data transfer to the Channel card. The NAND gate 92 uses the ADRESP signal, ST
The S1 # signal is given by performing the NAND operation of the negation signal of the ART # signal, the TRANS signal, the negation of the XOR of the WR signal, and the negation of the DSLAVE OWNS BUS signal. S
The timing of the 0 # and S1 # signals corresponds to the timing of the START # signal.

In the NAND gate 94, the ADL # signal is ANDed with the negation signal of the START # signal, the negation signal of the ADRESP signal, the TRANS signal, and the delayed BCLK signal to obtain the data transfer control circuit 34.
Generated by. The 25 nsec delay circuit 96 provides the delayed BCLK signal, and this delay is
It is necessary to provide the timing relationship between S0 #, S1 #, and ADL # defined in the tem / 2 Hardware Interface Technical Reference Manual.

The AND gate 95 ANDs the M-IO signal with the negative signal of the DSLAVE OWNS BUS signal to give the M / IO signal. In this way, the M / IO signal will track the M-IO signal except when the DMA slave owns the bus 16 which puts the M / IO signal in the I / O state (ie, low). Next, the system control circuit 14 generates an address signal, which is translated by the address translation circuit 32 to generate Micr.
The Channel address signal is given to the expansion card 20. Expansion card 20 determines if the Micro Channel address signal is within its range. If this address is not within the range of the expansion card 20, the expansion card 20 does nothing. On the other hand, when this Micro Channel address signal is within the range of the expansion card 20, the expansion card 20
Is the transmission feedback signal (CD SFDBK #)
Respond by activating and displaying that it is active. In addition, the expansion card 20 receives the first Micro Channel size signal (CD DS32 #).
, Which indicates that it will process 32-bit data information, and activates the second Micro Channel size signal (CD DS16 #), which causes 16
Indicates processing bit data information, or D
Neither the S32 # signal nor the CD DS16 # signal is active, which serves to indicate that it processes 8-bit data information.

CD DS322 # and CD DS16
The # signal is an EISA size signal (EX3 that notifies the system control circuit 14 of the data size that the slave 20a can support via the tri-state gate 114.
2 # and EX16 #). System control circuit 1
4 is 8-bit Micro Channel card 8-bit Fami
Although considered as a ly I card, the control circuit 14 still uses the START # and CMD # signals as well as the Family.
Supply I control signal. Therefore, the interface conversion logic circuit 28 uses the START # and CMD # signals to control 8-bit transfers in the same manner as it controls 16- and 32-bit transfers.

Furthermore, CD DS16 #, CD DS3
2 # and CD SFDBK # signals are NAND gate 9
Given to 8. NAND gate 98 flows the output
This flow register 100 is given to the register 100.
On the rising edge of START # latches a slave active signal (SLAVE ACTIVE) indicating whether the expansion card is responding to an ongoing transfer sequence. This SLAVE ACTIVE signal is S0
Reset when #, S1 #, and CMD # become inactive when detected by NAND gate 102.

The system control circuit 14 completes the data transfer by activating the CMD # signal. The expansion card 20 also uses the CMD # signal to indicate that the data transfer is complete, but the timing of the Micro Channel CMD # signal is different than that of the EIISACMD # signal. The interface conversion logic circuit 28 is EI
Adapted to the timing of SA CMD # signal, Micro Chan
nel CMD # signal. This Micro Channel CM
The D # signal is at the rising edge of the BCLK signal as detected by edge latch 106 and NAND gate 108 from the time ADL # becomes inactive as detected by AND gate 104, and then EISA CM.
It is sent until the D # signal and the EISA ready signal become active. Latch 106 is AND gate 10
The other input of 4 is given. The time used for data transfer can be extended by applying an active channel ready signal (CD-- CHRDY) to NAND gate 108. Micro Channel CD CH
The RDY signal corresponds to the EISA EXR DY signal, so the two signals are connected through tristate gate 114.

The Micro Channel card 20 has REFRE
SH # M / IO, S0 #, S1 #, ADL # and Mi
cro Channel CMD # signal is MASTER OWNS
It is provided through the Micro Channel data control tristate gate 112 which is enabled by the BUS signal. Thus, when master 20b does not own bus 16, these signals pass through gate 112 to expansion card 2
Given to 0. When master 20b owns bus 16, the system at gate 112 is left floating. Furthermore, Negative MASTER OWNS BUS #
EX16 to bus 16 via signal enabled EISA data control tristate gate 114
The #, EX32 #, and EXRDY signals are provided.
Therefore, when the master 20b does not own the bus 16,
These signals are provided on bus 16. When master 20b owns bus 16b, these signals are left floating.

By the way, as can be seen from FIGS. 2, 11 and 12, before the expansion card 20 can control the bus 16, the expansion card 20 must first obtain control of the bus 16 by arbitration. . Micro Channel and EISA utilize different arbitration schemes. The interface conversion logic circuits 28b and 28c are Micr
o Convert Channel arbitration scheme to EISA bus arbitration scheme and vice versa. The Micro Channel method uses the forced exclusion signal (PREEMPT #), 4-bit arbitration signal (A
RB), arbitration grant signal (ARB / GRANT #),
And a burst display signal (BURST #). In addition, the Micro Channel method controls the timing using the Micro Channel CMD # signal. The EISA method uses a master request signal (MREQX #) and a master acknowledgment signal (MA
CKX #), 8-bit DMA request signal (DRQO # -D
RQ7 #), and 8-bit DMA acknowledgment signal (DA
CK0 # -DRQ7 #) is used. In addition, the EISA method uses the BCLK signal to control timing.

Micro Channel Arbitration Scheme and EIS
Both A arbitration schemes include bus, bus master, and D
Two types of adapters that can arbitrate for MA slaves
Can support cards. The Micro Channel arbitration scheme has a common arbitration signal that supports both types of cards, while the EISA arbitration scheme has a separate arbitration signal for each type of card.

In the Micro Channel arbitration scheme, the bus
The master or DMA slave initiates the arbitration cycle by activating the PREEMPT # signal, thus informing the system control circuit 14 that the element wants to make a transfer using the bus. During initialization, each Micro Channel card is assigned a unique arbitration level of 0 to 14, which arbitration level is encoded in a 4-bit ARB signal. Micro Ch
When the annel card requests access to bus 16 via PREEMPT #, it provides the ARB signal. This ARB signal is provided when the ARB / GRANT # signal becomes active, and the expansion card 20
It defines the arbitration priority of b and 20c. When the expansion cards 20b, 20c become an acknowledged bus user, the ARB / GRANT # signal is deactivated (and thus transitions to the GRANT state). The use of the bus for the expansion cards 20b and 20c is permitted. Normally the grant is sent for a single bus operation, but by activating the BURST # signal,
It can be extended to longer times.

Micro Channel cards that have bus ownership can be forcibly removed from their ownership. This occurs when some other card or device activates the PREEMPT # signal line. Bus owner is PRE
The bus must be relinquished within a predetermined time after monitoring the EMP # signal and detecting the activation of this PREEMPT # signal.

In the EISA arbitration scheme, a request acknowledge signal is used to arbitrate for the bus. Individual signals are activated requesting use of the bus. The system control circuit 14 includes a central arbitration control circuit that detects all requests. When the bus 16 is enabled, the system control circuit 14 assigns the bus usage to the highest priority request by sending individual acknowledgments to the device with the highest priority request. In this case, a unique request acknowledge signal is provided to the bus master and another signal is provided to the DMA slave. A device requesting bus usage can extend its bus usage time by keeping its request signal active, which in turn
The acknowledgment signal remains active if no force exclusion is required. When forced exclusion is required, the acknowledge signal is deactivated even though the request signal remains active. When the bus owner detects this condition, it must abandon the bus within a certain amount of time.

EISA requests and acknowledges arbitration via different signal paths for bus masters and DMA slaves. Each EISA connector is MREQX #
For signals, use the master request signal path, and MACKX #
For signals, the master acknowledge signal path is physically connected to it. Each slot 18 has DRQ0 # -D
There are seven DMA slave request signal paths and seven DMA acknowledge signal paths for the RQ7 # signal and the DACK0 # to DACK7 # signals, respectively. DRQ
4 and DACK4 # are not used. In this way, any slot can be programmed during initialization to send its DMA slave request to any of the seven active lines.

Interface conversion logic circuits 28b, 28
The arbitration circuit 35 of c allows the above two arbitration mechanisms to be connected together and operate properly. This arbitration circuit 35
Comprises a bus master arbitration circuit 120 and a DMA slave arbitration circuit 122, and an arbitration control circuit 124 which is otherwise common to the independent bus master arbitration circuit 120 and DMA slave arbitration circuit 122.

Referring now to FIG. 11, a MicroChannel bus master attempting to initiate a transfer on bus 16 first requests bus ownership by activating its PREEMPT # signal. Active PREEM
The PT # signal is detected by the receiver 130 of the arbitration control circuit 124, which discriminates between the PREEMPT # signal activated by the Micro Channel card and the PREEMPT # signal activated by the driver 132. Receiver 130 is the active PRE
The EMPT signal (APREEMPT #) is sent to the NAND gate 134. NAND gate 134 provides an output signal to AND gate 136 of bus master arbitration card 120. The AND gate 136 receives the active MASTER signal generated in the initialization circuit 30 and the active P signal.
AND with the REEMPT signal. Active MAS
The TER signal is the AND gate 1 of the PREEMPT # signal.
Propagate through 36 and also through OR gate 138 to set latch 140, thus activating the MREQX # signal, allowing Micro Channel card 20b to indicate that it is requesting use of bus 16. Latch 140 synchronizes the MREQX # signal with the BCLK signal required by bus 16.

The transmission of the PREEMPT # signal by the expansion card 20 is also performed by the arbitration control circuit 124.
This results in the generation of the ARB / GRANT # signal applied to b. That is, the NAND gate 134 is ADREEM
The PT # signal is supplied to the AND gate 142. All other inputs to AND gate 142 are always active for bus master card 20b. Therefore,
AND gate 142 is an active MASTER ARB
The CONTROL signal is sent to the OR gate 144, and this OR gate 144 then outputs the high AR to the expansion card 20b.
Send the B / GRANT # signal. This informs expansion card 20b that it is in arbitration for bus 16 and also provides arbitration circuit 35 with an ARB signal. However, for the bus master card 20b, the ARB
The signal is don't care and is not used because the bus master arbitration level is established in the system control circuit 14. Therefore, the arbitration circuit 35 only needs to send out MREQX #.

The bus master arbitration circuit 120 waits until the system control circuit 14 acknowledges the request to use the bus by sending a MACKX # signal indicating that the expansion card 20b has ownership of the bus 16. , MAREQ
X # signal continues to be sent and ARB / GRANT #
Keep the signal in ARB state. The MACK # signal about to become active activates the NOR gate 146. The rising edge of the output signal of NOR gate 146 sets edge detect latch 148. As a result, the input signal from the latch 148 to the AND gate 142 becomes inactive and propagates through the OR gate 144 to change the state of the ARB / GRANT # signal to indicate GRANT. Expansion card 20b is GRANT
Is signaled that it is the owner of the bus 16 and thus completes the conversion of the arbitration scheme. Expansion card 20b can proceed to perform the transfer on demand.

The MREQX # signal is removed by the expansion card 2
0b shows how long you want to retain ownership of the bus. The expansion card 20b deactivates the PREEMPT # signal immediately after receiving the GRANT signal and activates the BURST # signal if it wishes to maintain bus ownership. BURST # and PREEMPT
# Signal is the active MR
NAND gate 13 to keep EQX # active
Combined at 4. BURST # signal is also AND gate 14
2 and thus BURST # is active, the ARB / GRANT # signal remains in the GRANT state. To compensate for the transition time between when the PREEMPT # signal becomes inactive and when the BURST # signal becomes active, the output signal of latch 148 is provided to OR gate 138 to activate MREQX #. maintain. Latch 148 provides Micro Channel CMD # during the first data transfer from expansion card 20b.
Reset by signal. This latch 148 is set only once per bus ownership time because it is edge triggered. Micro Channel CMD # signal is also ANDed
The ARB / GRANT # signal is fed to the gate 142 during the last data transfer of the bus ownership period and its GRAN
Guaranteed to remain in the T state.

The system control circuit 14 deactivates the MACKX # signal to cause the expansion card 20b to
Forced out of bus ownership. AND gate 150
MAC while BURST # signal is active
When it detects that the K # signal has become inactive, it gives a master forced exclusion signal. This makes PREMP
The T # signal is sent to the expansion card 20b via the OR gate 152 and the driver 132.

Here, as can be seen by referring to FIGS. 11 and 12, the Micro that desires to start the transfer on the bus 16.
The Channel DMA slave 20c first receives its PREEM.
Claim ownership of the bus by activating the PT # signal. The activated PREEMPT # signal is detected by the receiver 130 of the arbitration control circuit 124. The arbitration control circuit 124 sends the APREEMPT # signal to the AND gate 160 of the DMA slave arbitration circuit 122. AND gate 160 also receives the SLAVE signal from initialization circuit 30. For the DMA slave, the SLAVE signal is active and
The T # signal is passed through AND gate 160. AN
The output of the D gate 160 is 50n by the delay circuit 162.
It is delayed by sec. The delay of 50 nsec stabilizes the 4-bit ARB signal generated by the expansion card 20c.

PREEMPT # by the expansion card 20c
Signal transmission is also given to the expansion card 20c A
Causes the arbitration control circuit 124 to generate the RB / GRANT # signal. That is, NAND gate 134 provides AND gate 164 with the APREEMPT # signal. All other inputs to AND gate 164 are normally active to DMA slave card 20c. Therefore, AND gate 164 is active in the DMA ARB.
Pass the CONTROL signal through the OR gate 144,
This is a high ARB / GRANT for the expansion card 20c
# Send a signal. This notifies expansion card 20c that it is arbitrating for bus 16 and will provide the ARB signal to arbitration circuit 34. ARB
Of the 4 bits of the signal, 3 bits are coded 3-bit input to decode the 7 output signals (DRQ0 # -DR
Q3 # and DRQ5 # to DRQ7 #) (decoder 16
The eighth output from 6 is unused) and has meaning for DMA slave operation when decoded by the 3 to 8 decoder 166 which activates one of the two. AR
The B signal is assigned to the expansion card 20c during initialization. Here, since the ARB signal is not given to the bus in this application (in the Micro Channel system, the ARB signal is given to the 4-bit ARB bus, which returns an indication whether the card has the highest priority or not). Note that expansion card 20c does not receive an indication that it is not the highest priority requestor, and thus continues to issue ARB signals until it issues a GRANT signal.

The active DRQ # signal is given to the system control circuit 14 via the bus 16 and the system control circuit 13 is informed by the expansion card 20c that the expansion card 20c uses the bus 16D.
Notify that an MA request is being generated. No synchronization latch is required for DMA slave arbitration requests.

The DMA slave arbitration circuit 122 until the system control circuit 14 acknowledges the request to use the bus by sending a corresponding DACK # signal indicating that the expansion card 20c has ownership of the bus 16. , DR
Q # signal is sent and ARB / GRANT # is AR
Continue to put it in state B. The DMA slave acknowledge signal simply needs to respond to the corresponding DMA slave request signal.

For example, assume that DRQ7 # is activated. The active DAC 7 # signal causes AND gate 168 to provide an active output signal to OR gate 170. Only one AND gate 168 provides one active output signal at a time. The output signal of the AND gate 168 is logically ORed by the OR gate 170. The rising edge of the output signal of the OR gate 170 sets the edge detection latch 172. The setting of the latch 172 causes the AND gate 164 to cause the inactive DMA ARB CONTR to the OR gate 144.
An OL signal is applied which changes the state of the ARB / GRANT # signal to GRANT.

A low ARB / GRANT # signal causes A
The RB signal becomes inactive. Therefore ARB / GR
When the ANT # signal is in its grant state and the decoder 16
6 is allowed to continue sending the DMA request signal, A
The RB signal is latched by flow register 174. Flow register 174 is a flow through register that allows the ARB signal to pass during the ARB state and be latched to the GRANT state. This GR
The transmission of the ANT # signal informs the expansion card 20c that it owns the bus 16 and can proceed with the transfer according to the instruction.

The removal of the DRQ # signal is performed by the expansion card 20c.
Shows how long they want to retain bus ownership.
The expansion card 20c does a PR immediately after receiving the GRANT signal.
The EEMPT # signal is deactivated, and then the BURST # signal is activated when it is desired to maintain the bus ownership. The BURST # and PREEMPT # signals are combined at NAND gate 134 so that whichever is active keeps DRQ # active. BURS
The T signal is also provided to AND gate 164, so that as long as the BURST # signal is active, ARBGRAN
The T # signal remains in the GRANT state. PREEMP
The output signal of latch 172 is provided to OR gate 176 to compensate for the transition time during which the T signal becomes inactive and the BURST # signal becomes active.
Keep the DRQ # signal active. Latch 172
Is an expansion card 2 by Micro Channel CMD # signal
Reset during the first data transfer from 0c. Also, the latch 172 is set only once per bus ownership period because it is edge triggered. MicroC
The hannel CMD # signal is also provided to the AND gate 164 so that the ARB / GRANT # signal is at its GRANT for an appropriate time during the last data transfer of the bus ownership period.
Guarantee to stay in state.

The system control circuit 14 deactivates the expansion card 20c from the bus ownership by inactivating the DAK # signal. AND gate 178 activates BURS when the selected DAK # signal becomes inactive.
In detecting that the T # signal becomes active, DM
A Forced exclusion signal (DMA PREEMPT) is given.
As a result, the PREEMPT # signal is sent to the expansion card 20c via the OR gate 152 and the driver 132.

In some cases, it may be necessary to terminate ownership of the bus 16 by the expansion card 20c faster than can be achieved with the PREEMPT # signal. Therefore, AND gate 180 is used to provide the programmable fast termination option. The AND gate 180 receives the FAST TERM signal from the initialization circuit 30 as well as the DMA PREEM.
It receives the PT # signal and the SLAVE signal. FAST
If the TERM signal is set during initialization, AND
The activation of the DMA PREEMPT # signal at gate 178 causes AND gate 180 to become active,
Further, the arbitration permission is retrieved from the expansion card 20c by returning the ARB / GRANT # signal to the ARB state. Card 20c must be able to understand the REVOKE GRANT sequence if the FAST TERM latch is set. G
The expansion card 20c, which detects the removal of RANT, terminates the word transfer in progress and then immediately relinquishes the bus.

The arbitration control circuit 124 receives the master bus ownership display signal (MASTER OWN BUS) and the DMA slave bus ownership display signal (DSLAVE).
OWNS BUS) to generate the bus master and D
Keep track of bus ownership for MA slaves.

The MASTER OWNS BUS signal is generated by the set / reset latch 190 and is set when the arbitration circuit 35 receives an active MAKX # signal. The high MASTER OWNS BUS signal indicates that the associated card has bus ownership, in which case it remains set as long as the ARB / GRANT # signal is in the GRANT state. This MASTER OW
The function of the NS BUS signal is to control the enable and disable operations of the tristate driver that switches the interface conversion logic 28 between master and slave functions. MASTER OWN
When the S BUS signal is high, this signal
Turn off tristate gate and enable master function. When the MASTER OWNS BUS signal is low, this signal turns on the slave mode feature and enables expansion card 20b to monitor bus 16 for instructions.

D by the set / reset latch 191
The SLAVE OWNS BUS signal is generated, which is set when the DMA slave arbitration circuit 122 generates an active DAK signal based on the DAK # signal. A high DSLAVE OWNSBUS signal indicates that the associated expansion card 20c has bus ownership, and this DSLAVE OWNS BUS signal remains set as long as the DMA ARB CONTROL signal is active. ..

Referring to FIGS. 1, 7, 8 and 9, when the expansion card 20b gains control of the bus 16 by arbitration, the expansion card 20b starts the transfer sequence. The expansion card 20b starts the transfer sequence by transmitting either the S0 # signal or the S1 # signal. The data translation circuit 34 uses these signals for STA.
Generate the RT # signal. That is, as shown in FIG. 8, AND gate 200 detects when either S0 # or S1 # becomes active. The output of AND gate 200, which is low when either S0 # or S1 # is active, is negated and provided to NAND gate 202. The output of AND gate 200, when low, pulls NAND gate 202 low, which resets edge latch 204 to low CD RDYR.
Provide a TN signal. When the CD--RDTRTN signal is low, bus 16 cannot operate at the default speed of expansion card 20b which is a 200ns transfer sequence. The fastest standard transfer sequence on which the bus 16 can operate is 240 nsec. Therefore, the expansion card 20b
The transfer between the bus 16 and the bus 16 is performed every 360 ns (3 EISA clock cycle).

The low CD RDYRTN signal also sets edge latch 206, indicating that the START # signal may be sent to bus 16 synchronously with the next rising edge of the BCLK signal. When the START # signal is sent, B
Reset latch 206 so that the START # signal is reset on the next rising edge of the CLK signal. In this way, START # is sent every BCLK cycle.

The CD RDYRTN signal goes high when the EXRDY signal received from bus 16 goes high and the BCLK
It stays low until it is clocked into the latch 204 by the negative signal of. In order for the EXRDY signal to clock latch 204, the reset signal provided by NAND gate 202 must go low. This reset signal is a CM applied to the XOR gate 210.
It goes low when the D # signal goes low.

Next, the expansion card 20b determines the size of the data to be transmitted based on the size display signal (DS16RTN # and DS32TRN #). DS16RTN
The # signal and the DS32RTN # signal are used in the initialization circuit 20.
16 MASL signal and 32 MASL provided by
Generated by NAND gates 212 and 214, respectively, based on the state of the signal. The DS16RTN # and DS32RTN # signals are negated and the adapter 22
The 16 MASTER and 32 MASTER signals indicating the size of the expansion card 20 are supplied to. The 16MASL signal is also negated by tristate gate 216 to indicate to system control circuit 14 the size of the card.

Referring now to FIG. 9, each of the 32 data bits has dual flow registers 220, 22.
Buffered at 2, tristate driver 224,
Gated at 226. One direction of buffer operation is provided for read operations and the other direction for write operations. Register 220 buffers the data from expansion card 20b and allows this data to pass when the Micro Channel CMD # signal is active. This data is latched when the Micro Channel CMD # signal is high. For the data received from bus 16, it is latched in register 222 when the EISA HOLD signal generated by OR gate 228 is active.

Data latches occur for four different states depending on the particular operation performed. For 32-bit master operation, AND gate 230
The SACMD # and EX32 # signals are both active, causing data to flow through register 234 until the 32-bit data is currently valid. AND gate 23 for 16-bit master operation
2 allows data to pass through register 225 until both the CMD # and EX16 # signals are active, indicating that 16-bit data is currently valid. D
AND gate 23 for operation in MA slave mode
SLAVE DATA ENABLE generated by 4
The EISA CMD # signal is the AND gate 236.
And 238 and OR gate 240 detect the active READ signal and DSLAVE OWNS B
Allow data to flow through register 224 until it becomes active associated with the US signal. For slave mode operation, the SLAVE DATA ENABLE signal is the active SLA from which the EISA CMD # signal was detected by AND gate 242 and OR gate 240.
Allow data to flow through register 224 until activated in association with the VE--ACTIVE and active--WRITE signals.

MCIN # is used for tristate enable and disable of the data buffers 224 and 226.
Signal and the MCOUT # signal. Selection of the appropriate tri-state control is based on the type of operation being performed (master transfer, slave transfer, or DMA slave transfer) and whether the operation is read or write. The timing of the MCIN # signal is Micro Channe
Controlled by the CMD # signal. The timing of the MCOUT # signal is the BCLK signal and the EISACMD # signal.
Controlled by signals.

That is, the MCIN # signal is generated for three types of transfer modes, master mode transfer, DMA slave mode transfer, and slave mode transfer. AND gate 244 for master mode transfer
Active MASTER OWNS detected by
Micro Channel with BUS signal and active READ signal detected by AND gate 246
OR gate 248 when the CMD # signal is active
Generates the MCIN # signal. Master DMA slave
For mode transfer, OR gate 248 is active when the Micro Channel CMD # signal is active, along with the active DSLAVE OWNS BUS signal detected by AND gate 250 and the active READ signal detected by AND gate 252.
Generate the CIN # signal. For slave mode operation, the active SLAVE ACTIVE signal detected by AND gate 254 and AND gate 25.
OR gate 248 generates an active MCIN # signal when the Micro Channel CMD # signal is active, along with an active WRITE signal detected by 6.

The MCOUT # signal is generated by latch 260 clocked by the falling edge of the BCLK signal. The MCOUT # signal is set by the EISA HOLD signal becoming active and is held active on the subsequent falling edge of the BCLK signal by the feedback loop provided through AND gate 262. The MCOUT # signal remains active until it is reset by AND gate 264. The CMD # signal is ORed as determined by EISA.
It becomes inactive with detection of any of the three cases detected by gate 266. For master transfer,
MASTER OWNS BUS signal is OR gate 2
Active with the WRITE signal detected by AND gate 268 which provides the input signal to 66. For master DMA slave transfer operation, DSLAVE OWN
The S BUS signal is active with the WRITE signal detected by AND gate 270. For slave transfer operations, the SLAVEACTIVE signal is active along with the READ signal detected by AND gate 272.

READ / WRITE flow register 1
Reference numeral 10 latches the WR signal at the trailing edge of the START # signal and supplies the READ signal and the WRITE signal. The READ and WRITE signals, which are further provided to the initialization circuit 30, indicate whether the transfer is a read operation or a write operation, and the register 110 supplies these signals throughout the entire transfer sequence.

For inconsistent data transfers (ie,
A special consideration needs to be added where the data size of the transmitter is different from the data size of the receiver (eg 32 bit vs 16 bit transfer). Latch 280 is STA
This condition is detected when the RT # signal becomes inactive and the EX32 # signal is not activated by the receiving device in response to the START # signal, and the receiving device receives 32
Indicates that the bit transfer cannot be accepted. When this occurs, the master 20b acts to relinquish control of the bus 16 and return control to the system control circuit 14 which clears the mismatch.

The interface conversion logic circuit 28 uses ST
Tristate driver 28 driving the ART # signal
Disable 2 and drive the byte enable signal, giving up control of bus 16 by disabling the tri-state driver located in register 86. AND gate 283 disables tristate gate 282 for the START # signal. Latch 284 and AND gate 87 accomplish this for the byte enable signal (FIG. 6).

If the mismatch is for a read operation, then C
The D RDYRTN signal is held inactive (low) during the mismatch to allow parallel data information to be incorporated into a complete 32-bit word for presentation to expansion card 20b. The system control circuit 14 uses the EIS
It is obtained by having both ACMD # and EX32 # signals active at the same time. The AND gate 230 detects the CMD # signal and the EX32 # signal together with the 32MASTER signal, and outputs the NAND gate 286.
A 32-bit data ready signal (32DRDY) given to (FIG. 8) is generated. NAND gate 286
Sends a signal to AND gate 288, which also receives the READ and MISMATCH signals. AND gate 288 receives the EXRDY signal and outputs a low signal to O
Transfer to R gate 290. OR gate 290 provides the output signal to latch 204. Latch 204 is CD RD
It sends the YRTN signal, which leads to the end of the transfer sequence.

The DMA slave transfer sequence is
It is different from the master transfer sequence. Both of these sequences arbitrate for use of the bus 16 and the bus master generates and controls the transfer sequence, but DM
The A slave does not do that. After arbitrating for the bus 16, the DMA slave 20c becomes a slave participant in a bus transfer to or from memory, where this transfer is located in the central DMA controller (which is located, for example, in the system control circuit 14). )
Controlled by, the controller acts as a master and generates the control sequences necessary to perform the data transfer.

Further, EISA DMA transfer is performed by Micro Ch
This is different from annel DMA transfer. EISA performs parallel DMA transfers (ie, complete transfers of data in a sequence that include both transmitter and receiver information), while Micro Channel provides serial DMA transfers (ie, individual sequences received by transmitter and receiver). Complete transfer of the data in the two sequences that are served by both devices. The interface conversion logic 28 tricks the expansion card 20c into a Micro Channel in which a single EISA DMA transfer sequence executes the expansion card 20c.
Think of it as a DMA transfer sequence. Bus 1 is sent by the system control circuit 14 to the DMA transfer sequence.
The information arranged on 6 is the memory address and M-
It is an associated memory control line such as IO or WR, and this information is transferred to the memory section of the system control circuit 14. This information is used by the DMA slave 20c because it knows that it has been included in the DMA transfer sequence and therefore does not request address information since the DMA slave 20c arbitrated for control of the bus.
Will never be transferred to. On the other hand, the expansion card 20c expects to receive the address and the M / IO # and WR signals. Address including all zero is DMA
Acceptable for slave card 20c.

Therefore, the address translation circuit 32 receives the DSLAVE OWNS BU generated by the arbitration circuit 35.
When the S signal is active, it presents an address containing all zeros to the expansion card 20c. In addition, M / IO #
When the DSLAVE OWNS BUS signal is active, the signal is low (I / I) by the NAND gate 95 in FIG.
O transfer is shown). XOR gate 93 has DSL
The WR signal is provided along with the AVE OWNS BUS signal, and thus the WR signal is effectively negated. This negative WR signal is applied to the NAND gate 90 and the AND gate 9.
2 and are used in providing the S0 # and S1 # signals.

Further, the gate terminal 105 negates the DMA terminal count signal (TC), and the Micro Channel DMA
It is given to the expansion card 20c as a terminal count signal TC #. These terminal count signals indicate the end of DMA transfer.

Other embodiments are possible and are described below.

For example, the interface conversion logic circuit 28
May be integrated with the system board 12 or the expansion card 20. In this embodiment, a first connection device is used to integrally connect the first architecture to the interface conversion logic circuit 28 and a second connection to allow connection with the second architecture. The device is used and vice versa.

Further, for example, the bus master arbitration circuit 1
20 and arbitration control circuit 124 can be used to provide an adapter that simply interfaces with bus masters, memory slaves, and I / O slaves.
Also, the DMA slave arbitration circuit 122 and the arbitration control circuit 124 can be used to provide an adapter that simply interfaces with the DMA slaves, memory slaves, and I / O slaves.

Further, for example, the register 55 can be replaced by a switch that is set at the time of installation and indicates whether the expansion card 20 is the master or the DMA slave.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system according to the present invention.

FIG. 2 is a block diagram of a controller adapter according to the present invention.

[Fig. 3] Micro Chan of the controller adapter of Fig. 2
FIG. 6 is a schematic diagram showing an initialization circuit used to initialize a nel expansion card.

FIG. 4 is a schematic diagram showing the initialization circuit of FIG. 3, which generates four types of control signals based on information from a system control circuit.

5 is a schematic diagram of an address translation circuit of the controller / adapter of FIG. 2. FIG.

FIG. 6 is a schematic diagram of an address translation circuit for converting Micro Channel address information into EISA address information.

FIG. 7 is a schematic diagram of a data translation circuit of the controller / adapter of FIG.

8 is a schematic diagram showing a data translation circuit of the controller / adapter of FIG. 2, when the card gains control of the bus by arbitration. FIG.

9 is a data translation circuit of the controller adapter of FIG. 2, in which 32 data bits are dual flow
FIG. 6 is a schematic diagram showing a data translation circuit buffered by a register and gated by a tri-state driver.

10 is a timing diagram of the controller adapter of FIG.

11 is a schematic diagram of an arbitration circuit of the controller adapter of FIG.

12 is a schematic diagram of the arbitration circuit of the controller adapter of FIG. 2, in which the card must first gain control of the bus via arbitration before the card can control the bus.

[Explanation of symbols]

 10 computer system 12 system board 14 system control circuit 16 bus 18 expansion slot 20 Micro Channel card 20a, 20b, 20c expansion card 22 adapter 24 Micro Channel connector 26 EISA connector 28 interface conversion logic circuit 30 initialization circuit 32 address translation circuit 34 data translation circuit 35 bus arbitration circuit 46 address latch / decode circuit 81 data register 120 master arbitration circuit 124 arbitration control circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Howard Thomas Ornowich Endwell Twilight Drive, New York, USA 2922 (56) References JP 62-194566 (JP, A)

Claims (9)

[Claims] 1. A computer system having an expansion connector adapted to a first bus architecture, said first system.
An expansion card adapted to a second bus architecture different from the bus architecture, the expansion card including a control element and a logic circuit for enabling the control element as a bus master for a bus adapted to the second bus architecture. A device for transferring data to and from a card, the device being connectable to the expansion connector of the computer system and electrically coupled to separate first and second connectors and the first and second connectors. An adapter device having a conversion circuit, the first connector adapted to the first bus architecture, and address information in a first format unique to the first bus architecture between the adapter device and the expansion connector. , For transferring information signals representing data information and control information, said computer Connecting to the expansion connector of the system, the control information of the information signal of the first format comprises a first bus control signal controlling a master access to a bus adapted to the first bus architecture, The second connector is adapted to the second bus architecture, is connected to the expansion card including the control element, and is in the second format unique to the second bus architecture between the expansion card and the conversion circuit. A second different from the first bus control signal for transferring an information signal, the control information of the information signal in the second format controlling a master access to the bus adapted to the second bus architecture; Bus control signals, wherein the first bus architecture is adapted to control the bus adapted to the first bus architecture In order to arbitration,
The first constituting a subset of the first bus control signal
A first arbitration scheme using a bus arbitration control signal in a format, wherein the second bus architecture arbitrates control of the bus adapted to the second bus architecture,
The second constituting a subset of the second bus control signal
A second arbitration scheme using a bus arbitration control signal of a format, wherein the conversion circuit includes an information signal received in the first format via the expansion connector and the first connector, via the second connector. Means for converting into a signal in the second format that is functionally compatible with the expansion card, and functionally compatible with transferring an information signal received in the second format from the expansion card to the expansion connector A data transfer device comprising: a unit for converting the signal into a signal in the first format; and a control signal translating unit for converting the bus arbitration control signal between the first format and the second format. 2. The first arbitration scheme is based on the first bus
An authorization in the first format that requests the provision of a bus arbitration control signal in the first format to the expansion connector of the computer that requests access to the bus that conforms to the architecture and that represents an approval of each request. Returning a signal to the computer system, the second arbitration scheme providing a bus arbitration control signal in the second format representing a force exclusion function requesting initiation of a bus arbitration process unique to the second bus architecture. Requesting and returning a grant signal in the second format indicating the start permission of the bus arbitration process to the control element, the control signal translating means transmitting the bus arbitration signal indicating the forced exclusion function to the bus access request. Represents the first
2. The data transfer device according to claim 1, further comprising: converting into a signal in the format, and converting the acknowledge signal received in response to the signal indicating the bus access request into the acknowledge signal in the second format. . 3. A computer having a first expansion connector adapted to a first bus arbitration scheme and a first bus architecture having first address information in a first format.
An apparatus for transferring data between a system and an expansion card having a control element adapted to a second bus arbitration scheme and a second bus architecture having a second address information in a second format different from the first format. And an adapter device having physically different first and second connectors and a conversion circuit electrically coupled between the first and second connectors, wherein the first connector is the first bus architecture. And is connected to the expansion connector of the computer system, the second connector is adapted to the second bus architecture, and is connected to the expansion card including the control element, and the conversion circuit is A signal adapted to the one-bus architecture is transmitted to a signal having a corresponding function in the second bus architecture. Converting the signal adapted to the second bus architecture to a signal having a corresponding function in the first bus architecture, and converting between the first and second arbitration schemes. A data transfer device comprising: an arbitration circuit having means, and an address translation circuit having means for converting the first and second address information between the first and second formats. 4. A first for allocating control of an adaptive bus.
A computer system having an expansion connector adapted to a first bus architecture having an arbitration scheme;
A second different from the first arbitration scheme for assigning control of the bus to accommodate the second bus architecture.
On the bus adapted to transfer the data information to and from an expansion card having an arbitration scheme and a control element adapted to a second bus architecture different from the first bus architecture and adapted to the first bus architecture And first
A data transfer device for transferring data information in a format and for transferring data information in a second format different from the first format on the bus adapted to the second bus architecture, the data transfer apparatus comprising: An adapter device having first and second connectors and a conversion circuit electrically coupled between the first and second connectors, wherein the control element acts as a bus master for the second bus architecture. Directly to the first bus architecture when used with the data transfer device, the first connector adapted to the first bus architecture. Configured to be connected to the expansion connector of the computer system, the second connector And a conversion circuit adapted to the first bus architecture, the converter circuit adapted to the second bus architecture and connected to the expansion card including the control element adapted to the second bus architecture. Means for converting a signal adapted to the second bus architecture to a signal adapted to the second bus architecture, means for converting a signal adapted to the second bus architecture to a signal adapted to the first bus architecture, the first arbitration Means for converting a scheme-adaptive signal into a functionally corresponding signal adapted to the second arbitration scheme and a signal adapted to the second arbitration scheme to the first
An arbitration circuit having means for converting into a signal corresponding functionally adapted to the arbitration scheme, and a data translation circuit for converting the signal representing the data information between the first and second formats. And a data transfer device. 5. Transferring data between a computer system having an expansion connector adapted to a first bus architecture and an expansion card including a control element adapted to a second bus architecture different from the first bus architecture. An adapter device having first and second connectors and a conversion circuit electrically coupled between the first and second connectors, wherein the control element is for the second bus architecture. Directly requested to act as a bus master, and indirectly used to act as a bus master for the first bus architecture when used with the data transfer device, the first bus architecture comprising: A first arbitration scheme and a first for use in automatically configuring the computer system. Matt first initialization information, wherein the second bus architecture has a second arbitration scheme different from the first arbitration scheme and a second format different from the first format for automatically configuring an application. Having second initialization information, the first connector interfacing with the expansion connector of the computer system and through the expansion connector to a bus adapted to the first architecture, the second connector Interface to the expansion card containing the control element and via the expansion card to a bus adapted to the second bus architecture, the conversion circuit comprising the computer via the first connector. The first bus received through the expansion connector of the system
Means for converting an architecture compatible signal into a signal having a corresponding function corresponding to the second bus architecture to be sent to the expansion card including the control element via the second connector; The first bus to be passed through the expansion connector of the computer system through the first connector, the signal being adapted to the second bus architecture received from the expansion card through the connector;
Means for converting into a functionally corresponding signal adapted to the architecture; and an arbitration signal adapted to the first arbitration scheme received via the expansion connector via the first connector via the second connector. Means for converting to a functionally related arbitration signal adapted to the second arbitration scheme to be sent to the expansion card and arbitration adapted to the second arbitration scheme received from the expansion card via the second connector An arbitration circuit having means for converting a signal into a functionally related arbitration signal adapted to the first arbitration scheme to be transferred to the expansion connector of the computer system via the first connector; And an initialization circuit for converting a signal representing the second initialization information between the first and second formats. Data transfer device to. 6. A computer system having an expansion connector adapted to a first bus architecture using a first address information and a first data information of a first format and a second address of a second format different from said first format. A device for transferring data between expansion cards including a control element adapted to a second bus architecture using information and a second data information, the first and second connectors having different structures and said first
And an adapter device having a conversion circuit electrically coupled between the second connector and the second connector, wherein the control element is configured to control the second bus architecture via a second arbitration signal process adapted to the second bus architecture. Competing with other devices to control a bus adapted to, is directly required by the first bus architecture to act as a bus master, and when used with the data transfer device, the second bus Indirectly requested by the architecture to act as a bus master, the first connector being the computer
Interfacing to the expansion connector of the system and via the expansion connector to a bus adapted to the first bus architecture, the second connector to the expansion card including the control element and to the Interfacing to a bus adapted to the second bus architecture via an expansion card, the conversion circuit comprising a signal related to contention for controlling a bus adapted to the first bus architecture, Means for converting a signal adapted to a one-bus architecture into a functionally related signal adapted to the second bus architecture, including a signal related to the second arbitration signal process, and related to the second arbitration signal process Signals adapted to the second bus architecture, including signals for Means for converting into a functionally related signal adapted to Kucha, and the second address information to be transferred via the second connector, the signal representing the first address information received via the first connector. And means for converting a signal representing the second address information received via the second connector into a signal representing the first address information to be transferred via the first connector. An address translation circuit having: and means for converting a signal representing the first data information received via the first connector into a signal representing the corresponding second data information to be sent via the second connector. And a corresponding first data information to be sent via the first connector, a signal representative of the second data information received via the second connector. It includes data translation circuit having means for converting to a signal, the data converter, characterized in that. 7. A computer system having an expansion connector adapted to a first bus architecture and a second bus system.
An apparatus for transferring data between expansion cards having control elements adapted to the architecture, the first and second connectors having different structures and said first
And an adapter device having a conversion circuit electrically coupled between the second connector and the second connector, wherein the first bus architecture is adapted for first address information and the first bus architecture. The transfer of a signal of a first format representing the first initialization information used for the second bus architecture, and the second bus architecture for automatic configuration of a computer system adapted to the second address information and the second bus architecture. Imposing a transfer of a second format signal representative of the second initialization information to use, the control element controlling the second bus architecture via an arbitration signal process uniquely associated with the second bus architecture. Contending for control of a bus having the first connector, the conversion circuit, the computer system. System to the expansion connector and via the expansion connector to a bus adapted to the first bus architecture, the second connector being connected to the expansion card including the control element and via the expansion card. Providing a connection between the conversion circuit and a bus adapted to the second bus architecture, the conversion circuit being a link bridge between the expansion card including the control element and the expansion connector of the computer system. And enabling the control element to act as a bus master for a bus adapted to the first bus architecture, the conversion circuit comprising: the first bus received via the first connector; The second bus architecture, in which signals adapted to the architecture are to be transferred to the control element via the second connector Means for converting into a functionally related signal adapted to Kucha, and transferring a signal adapted to the second bus architecture received via the second connector to the computer system via the first connector. Means for converting to a functionally-related signal adapted to the first bus architecture including a signal functionally corresponding to the arbitration signal associated with the arbitration signal process; An address translation circuit having means for converting a signal representing the second address information and a means for converting a signal representing the second address information into a signal representing the first address information, and representing the first initialization information. Means for converting a signal into a corresponding signal representative of said second initialization information and a signal representative of said second initialization information representative of said first initialization information It includes an initialization circuit comprising means for converting the response signal, the data converter, characterized in that. 8. An apparatus for transferring data between a computer system having an expansion connector adapted to a first bus architecture and an expansion card including a control element adapted to a second bus architecture, the apparatus having a different structure. First and second connectors and the first
And an adapter device having a conversion circuit electrically coupled between the second connector and the second connector, wherein the control element is via the arbitration signal process uniquely associated with the second bus architecture. Bus for the first bus architecture when used in conjunction with the data transfer device when competing for access to a bus that conforms to the requirements of the second bus architecture and acting as a bus master. Requested to act as a master, the first bus architecture is of a first format representing first data information and first initialization information used for automatic configuration of a computer system adapted to the first bus architecture. Imposing a transfer of signals, said second bus architecture comprising second data information and said second A transfer of a second format signal representative of second initialization information for use in automatic configuration of a computer system adapted to a computer architecture, wherein the first connector is adapted to the first bus architecture. Interfacing to the expansion connector of a system, the second connector being connected to the expansion card including the control element adapted to the second bus architecture, the conversion circuit being the expansion card and the computer
Providing a link bridge between the expansion connectors of the system, enabling the control element to act as a bus master for the first bus architecture, wherein the conversion circuit is via the first connector Functionally responsive to the second bus architecture including a received signal that is adapted to the first bus architecture and is associated with the arbitration signal process that is uniquely associated with the second bus architecture. And a signal functionally corresponding to the signal associated with the uniquely associated arbitration signal process of the signal received via the second connector and adapted to the second bus architecture. Means for converting to a functionally related signal adapted to the first bus architecture, and the first data information A data translating circuit having means for converting a signal representing the second data information into a corresponding signal representing the second data information and a signal representing the second data information into a corresponding signal representing the first data information, Means for converting a signal representing the first initialization information into a corresponding signal representing the second initialization information and a signal representing the second initialization information into a corresponding signal representing the first initialization information. A data conversion device comprising: an initialization circuit having means. 9. A computer system having an expansion connector adapted to a first bus architecture and a second bus system.
An apparatus for transferring data between expansion cards including control elements adapted to the architecture, the first and second connectors having different structures and the first
And an adapter device having a conversion circuit electrically coupled between a second connector, the control element being required to act as a bus master for the second bus architecture, and the data transfer device. Is required to act as a bus master when used in conjunction with the first bus architecture having a first arbitration scheme for storing address information, data information and initialization information. Processing in a first format specific to the first bus architecture, the second bus architecture having a second arbitration scheme different from the first arbitration scheme, address information,
Processing data information and initialization information in a second format specific to the second bus architecture, the first connector being connected to the expansion connector of the computer system to include the conversion circuit and the first bus. Providing a connection between the architecture-adapted buses, the second connector being connected to the expansion card containing the control element to provide a connection between the conversion circuit and the second bus-adapted bus. The conversion circuit includes the expansion card and the computer
Providing a link bridge between the expansion connectors of the system, allowing the control element to act as a bus master for a bus adapted to the first bus architecture, the conversion circuit comprising: Means for converting a signal adapted to the first bus architecture received via a connector into a functionally corresponding signal adapted to the second bus architecture; and the signal received via the second connector. An arbitration circuit having means for converting a signal adapted to a second bus architecture into a functionally related signal to be transferred to said computer system adapted to said first bus architecture and said first arbitration scheme; Means for converting a signal representing the first address information into a signal representing the second address information, and the second address information Address translating circuit having means for converting a signal representing information into a signal representing the first address information; means for converting a signal representing the first data information into a corresponding signal representing the second data information; and A data translation circuit having means for converting a signal representative of second data information into a corresponding signal representative of the first data information; and a signal representative of the first initialization information corresponding signal representative of the second initialization information. And an initialization circuit having means for converting into a signal representing the second initialization information into a corresponding signal representing the first initialization information.