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JPH0817575B2 - Inverter protection method - Google Patents
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JPH0817575B2 - Inverter protection method - Google Patents

Inverter protection method

Info

Publication number
JPH0817575B2
JPH0817575B2 JP61062436A JP6243686A JPH0817575B2 JP H0817575 B2 JPH0817575 B2 JP H0817575B2 JP 61062436 A JP61062436 A JP 61062436A JP 6243686 A JP6243686 A JP 6243686A JP H0817575 B2 JPH0817575 B2 JP H0817575B2
Authority
JP
Japan
Prior art keywords
polarity
load
period
voltage
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61062436A
Other languages
Japanese (ja)
Other versions
JPS62221877A (en
Inventor
雅裕 長田
一行 荻原
武浩 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sawafuji Electric Co Ltd
Original Assignee
Sawafuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sawafuji Electric Co Ltd filed Critical Sawafuji Electric Co Ltd
Priority to JP61062436A priority Critical patent/JPH0817575B2/en
Publication of JPS62221877A publication Critical patent/JPS62221877A/en
Publication of JPH0817575B2 publication Critical patent/JPH0817575B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は,インバータ保護方式,特にブリッヂ接続さ
れたスイッチング素子を有しかつコンデンサを含む負荷
を接続されてなる。インバータ回路において,上記スイ
ッチング素子を制御する発振回路の出力の極性と負荷に
生じている電圧の極性とを比較し,スイッチング素子の
オン・オフ転換期に休止期間をもうけるようにしたイン
バータ保護方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention comprises an inverter protection system, in particular a bridge-connected switching element, to which a load including a capacitor is connected. In an inverter circuit, the present invention relates to an inverter protection method in which the polarity of the output of the oscillation circuit controlling the switching element is compared with the polarity of the voltage generated in the load, and a rest period is provided at the on / off switching period of the switching element. .

〔従来の技術〕 従来から,第3図図示の如き構成をもつインバータ回
路が知られている。
[Prior Art] Conventionally, an inverter circuit having a configuration as shown in FIG. 3 has been known.

第3図において,符号1−1ないし1−4は夫々トラ
ンジスタ,2−1ないし2−4は夫々フリーホイリング・
ダイオード,3は負荷であって3−Rは抵抗負荷で3−C
はコンデンサ負荷,4は直流電源を表している。
In FIG. 3, reference numerals 1-1 to 1-4 are transistors, 2-1 to 2-4 are free-wheeling transistors, respectively.
Diode, 3 is a load and 3-R is a resistive load 3-C
Is a capacitor load and 4 is a DC power supply.

従来上記の如き構成のインバータ回路が知られている
が,負荷としてコンデンサ負荷3−Cが接続される場合
には,次の如き問題が内在している。
Conventionally, an inverter circuit having the above-mentioned configuration is known, but when the capacitor load 3-C is connected as a load, the following problems are inherent.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

第3図図示の如くコンデンサ負荷3−Cが接続されて
いる場合において,今,トランジスタ1−2と1−3と
がオンされていた状態からオフされかつそれに伴ってト
ランジスタ1−1と1−4とがオンされるとき,第3図
図示icの如き大きい放電電流が生じる。これは,第3図
図示(+)(−)の如くコンデンサ負荷3−Cが充電さ
れている状態において,トランジスタ1−1と1−4と
がオンされることから,いわば2倍の電圧によってコン
デンサ負荷3−Cが逆方向に充電されようとする形とな
るからである。第4図はこの間の状況をタイムチャート
で表したものである。
In the case where the capacitor load 3-C is connected as shown in FIG. 3, the transistors 1-2 and 1-3 are now turned off, and accordingly, the transistors 1-1 and 1- when 4 and is turned on, a large discharge current, such as Figure 3 illustrated i c occurs. This is because the transistors 1-1 and 1-4 are turned on when the capacitor load 3-C is charged as shown in (+) and (-) in FIG. This is because the capacitor load 3-C is about to be charged in the opposite direction. FIG. 4 is a time chart showing the situation during this period.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は,上記の点を解決しており,上記電圧検出抵
抗を配置し,負荷に生じる電圧の極性を検出して上述の
如き場合における問題点を解決している。
The present invention solves the above problems, and solves the problems in the above cases by arranging the voltage detection resistor and detecting the polarity of the voltage generated in the load.

第1図は,本発明の原理構成図であって本発明の実施
例を構成するものである。図中の符号1−1ないし1−
4は夫々トランジスタ,2−1ないし2−4は夫々フリー
ホイリング・ダイオード,3は負荷,5−1ないし5−4は
夫々電圧検出抵抗を表している。また6は負荷電圧の極
性を検出する極性検出部,7は矩形波発振回路部,8は極性
比較回路部を表している。
FIG. 1 is a principle block diagram of the present invention and constitutes an embodiment of the present invention. Reference numerals 1-1 to 1- in the figure
Reference numeral 4 is a transistor, 2-1 to 2-4 are freewheeling diodes, 3 is a load, and 5-1 to 5-4 are voltage detection resistors. Further, 6 is a polarity detection unit for detecting the polarity of the load voltage, 7 is a rectangular wave oscillation circuit unit, and 8 is a polarity comparison circuit unit.

第1図図示の回路における動作,特にトランジスタ1
−1と1−4との第1群のスイッチング素子およびトラ
ンジスタ1−2と1−3との第2群のスイッチング素子
が交互にオンされることに関して,従来の構成と実質的
に変わりはない。ただ,抵抗5−1ないし5−4がもう
けられ,負荷3上に生じている電圧の極性を検出するよ
うにしている。
Operation in the circuit shown in FIG. 1, especially transistor 1
-1 and 1-4 of the first group of switching elements and transistors 1-2 and 1-3 of the second group of switching elements are alternately turned on, which is substantially the same as the conventional configuration. . However, the resistors 5-1 to 5-4 are provided to detect the polarity of the voltage generated on the load 3.

即ち負荷3の図示右側の電圧(RV)と図示左側の電圧
(LV)とを抽出し, RV−LV≧+ΔV となる期間を第1の極性とみなし,また LV−RV≧+ΔV となる期間を第2の極性とみなし,極性検出部6がこの
旨を極性比較回路部8に通知する。
That is, the voltage (RV) on the right side of the load 3 and the voltage (LV) on the left side of the load 3 are extracted, the period of RV−LV ≧ + ΔV is regarded as the first polarity, and the period of LV−RV ≧ + ΔV is determined. Considering the second polarity, the polarity detection unit 6 notifies the polarity comparison circuit unit 8 of this fact.

矩形波発振回路部7は矩形波出力を発しており,極性
比較回路部8は,当該矩形波発振回路部7の出力の極性
と上記極性検出部6からの極性とを比較する。そして,
両者の極性が異なっている期間はちょうど負荷に存在す
るコンデンサからの放電が行なわれている期間に対応し
ていることから、その期間だけ,スイッチング素子全体
をオフ状態におく所の休止期間を与えるようにしてい
る。
The rectangular wave oscillation circuit unit 7 emits a rectangular wave output, and the polarity comparison circuit unit 8 compares the polarity of the output of the rectangular wave oscillation circuit unit 7 with the polarity from the polarity detection unit 6. And
The period in which the polarities of both are different corresponds to the period in which the capacitor existing in the load is being discharged. Therefore, only during that period, a rest period is set in which the entire switching element is turned off. I am trying.

〔作用〕[Action]

上記の動作状況は,第2図図示のタイムチャートによ
って明らかにされている。第2図において,「休止」と
している期間が,上記休止期間に対応している。そし
て,当該休止期間は,負荷3に存在するコンデンサの電
圧が,図示ハッチングで示すように,放電によって減衰
してゆく期間に相当している。
The above operation status is clarified by the time chart shown in FIG. In FIG. 2, the period of “pause” corresponds to the pause period. Then, the pause period corresponds to a period in which the voltage of the capacitor existing in the load 3 is attenuated by the discharge as shown by the hatching in the figure.

このために,負荷3に存在するコンデンサが放電する
期間を待って,例えばトランジスタ1−2と1−3との
組からトランジスタ1−1と1−4との組に転換される
こととなる。即ちコンデンサが放電する期間と、スイッ
チング素子がオンされて充電される期間とが分離される
形となり,過大な電流が流れることが防止される。
For this reason, after a period in which the capacitor existing in the load 3 is discharged, for example, the set of transistors 1-2 and 1-3 is changed to the set of transistors 1-1 and 1-4. That is, the period in which the capacitor is discharged and the period in which the switching element is turned on and charged are separated, and an excessive current is prevented from flowing.

〔発明の効果〕〔The invention's effect〕

以上説明した如く,本発明によれば,上述の休止期間
を置くように制御するに当たって,発振回路部出力の極
性と負荷の極性とを照合するだけの処理によって,上記
休止期間を生じさせることができる。このために,例え
ば,上記休止期間を置くに当たって,発振回路部出力波
形自体に,予め定めた電圧零の期間をもうけるようにす
るなどの,従来公知の構成にくらべて,回路構成がきわ
めて簡単になる。即ちデジタル処理によっても所期の目
的を達成することが可能になっている。
As described above, according to the present invention, in controlling so as to place the above-described pause period, the pause period can be generated by the process of only comparing the polarity of the output of the oscillation circuit unit with the polarity of the load. it can. For this reason, the circuit configuration is much simpler than that of the conventionally known configuration, for example, in which the output waveform itself of the oscillation circuit section is provided with a predetermined voltage zero period when the pause period is set. Become. That is, it is possible to achieve the intended purpose even by digital processing.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の原理構成図であって本発明の実施例を
構成するもの,第2図はその動作を説明するタイムチャ
ート,第3図は従来の構成,第4図はその動作を説明す
るタイムチャートを示す。 図中,1はスイッチング素子(トランジスタ),2はフリー
ホイリング・ダイオード,3は負荷,3−Cはコンデンサ負
荷,4は直流電源,5は電圧検出抵抗,6は極性検出部,7は矩
形波発振回路部,8は極性比較回路部を表す。
FIG. 1 is a principle configuration diagram of the present invention, which constitutes an embodiment of the present invention, FIG. 2 is a time chart explaining its operation, FIG. 3 is a conventional configuration, and FIG. 4 is its operation. The time chart to demonstrate is shown. In the figure, 1 is a switching element (transistor), 2 is a freewheeling diode, 3 is a load, 3-C is a capacitor load, 4 is a DC power supply, 5 is a voltage detection resistor, 6 is a polarity detection unit, and 7 is a rectangle. The wave oscillating circuit section, 8 represents a polarity comparing circuit section.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−148591(JP,A) 特開 昭60−249874(JP,A) 特開 昭60−229676(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-57-148591 (JP, A) JP-A-60-249874 (JP, A) JP-A-60-229676 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】フリーホイリング・ダイオードが外付けさ
れあるいは内蔵されるスイッチング素子をそなえ、 当該スイッチング素子をブリッヂ接続し、 当該ブリッヂ接続の中性点間にコンデンサを含む負荷を
接続したインバータ回路において、 上記ブリッヂ接続における非対向位置に存在する少なく
とも上記スイッチング素子に夫々並列に電圧検出抵抗を
接続し、 当該夫々の電圧検出抵抗上に発生した検出電圧を抽出し
て上記負荷に生じている電圧の極性を検出し、 かつ当該極性と上記スイッチング素子を制御する発振回
路出力の極性とを比較するよう構成してなり、 該比較結果にもとづいて、上記発振回路出力の極性に対
して上記負荷に生じている電圧の極性が異なる極性とな
っている期間をもって休止期間として決定し、 当該休止期間に対応して、上記ブリッヂ接続されている
第1群のスイッチング素子がオフされた後に第2群のス
イッチング素子をオンせしめない期間を与えた ことを特徴とするインバータ保護方式。
1. An inverter circuit comprising a switching element having a freewheeling diode externally attached or built therein, the switching element being bridge-connected, and a load including a capacitor being connected between neutral points of the bridge connection. , Voltage detection resistors are connected in parallel to at least the switching elements existing at non-opposing positions in the bridge connection, and the detection voltage generated on each of the voltage detection resistors is extracted to detect the voltage generated in the load. The polarity is detected, and the polarity is compared with the polarity of the oscillation circuit output that controls the switching element. Based on the comparison result, the polarity of the oscillation circuit output is generated in the load. The period in which the polarity of the applied voltage is different is determined as the rest period, and the rest period In response to the above, an inverter protection method is characterized in that a period during which the switching elements of the second group are not turned on after the switching elements of the first group connected by the bridge are turned off.
JP61062436A 1986-03-20 1986-03-20 Inverter protection method Expired - Lifetime JPH0817575B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61062436A JPH0817575B2 (en) 1986-03-20 1986-03-20 Inverter protection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61062436A JPH0817575B2 (en) 1986-03-20 1986-03-20 Inverter protection method

Publications (2)

Publication Number Publication Date
JPS62221877A JPS62221877A (en) 1987-09-29
JPH0817575B2 true JPH0817575B2 (en) 1996-02-21

Family

ID=13200136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61062436A Expired - Lifetime JPH0817575B2 (en) 1986-03-20 1986-03-20 Inverter protection method

Country Status (1)

Country Link
JP (1) JPH0817575B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5696485B2 (en) * 2011-01-12 2015-04-08 株式会社安川電機 Inverter device and electric motor drive system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412166A (en) * 1981-02-26 1983-10-25 International Business Machines Corporation Stepper motor drive circuit for synchronous switching of core winding
JPS60229676A (en) * 1984-04-26 1985-11-15 Mitsubishi Electric Corp Pwm inverter
JPH0642783B2 (en) * 1984-05-24 1994-06-01 神鋼電機株式会社 Method of preventing magnetic bias in inverter transformers

Also Published As

Publication number Publication date
JPS62221877A (en) 1987-09-29

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