JPH081954B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device, particularly a high electron mobility transistor (hereinafter referred to as HEMT) having good characteristics while suppressing a short channel effect, improving α-ray resistance. That said).

[Conventional technology]

FIG. 3 is a side sectional view of a conventional heat resistant gate self-aligned HEMT.

In this figure, 21 is a substrate made of semi-insulating GaAs, 22
Is an undoped GaAs layer, 23 is a p-type GaAs layer, and 24 is undoped
GaAs layer, 25 is an undoped AlGaAs layer, 26 is an n-type AlGaAs layer,
27 is an n-type GaAs layer, 28 is a heat resistant gate electrode, for example WSi
It is composed of Reference numeral 29 is a source / drain n ⁺ layer formed by ion implantation, and reference numerals 30 and 31 are a source electrode and a drain electrode, both of which are made of AuGe alloy. 32
Is a 2DEG (Two Dimensional Electron Gas) layer.

Next, a manufacturing process of the conventional heat resistant gate self-aligned HEMT will be described.

First, on the substrate 21 made of semi-insulating GaAs, undoped
After epitaxially growing the GaAs layer 22, the p-type GaAs layer 23
Are grown epitaxially. The p-type GaAs layer 23 is for increasing the potential on the substrate 21 side and improving the 2DEG confinement effect.

Next, an undoped GaAs layer 24, an undoped AlGaAs layer 25 which is a buffer layer, and an n-type AlGaAs layer 26 are sequentially grown.

At this time, electrons are supplied from the n-type AlGaAs layer 26 to the undoped GaAs layer 24 due to the difference in electron affinity, so that undoped Ga
A 2DEG layer 32 is formed in the As layer 24. And this 2DEG layer
Since 32 is formed in the undoped GaAs layer 24, electrons flowing therethrough are not affected by impurity scattering, and high mobility can be obtained.

Next, n-type GaAs for the cap layer and the contact layer
Heat-resistant gate electrode after epitaxial growth of layer 27
Form 28.

Then, the heat-resistant gate electrode 28 is used as a mask to form the source / drain n ⁺ layers 29 in a self-aligned manner by the ion implantation method, and the source electrode 30 and the drain electrode 31 are formed, as shown in FIG. Heat resistant gate self-aligned HEMT
Is obtained.

Further, in this heat resistant gate self-aligned HEMT, the heat resistant gate electrode 28, the source electrode 30, and the drain electrode 31 are
Since the source / drain n ⁺ layer 29 having a low resistance value can be formed in a self-aligned manner between and, a high mutual conductance can be obtained relatively easily.

[Problems to be solved by the invention]

Conventional heat resistant gate self-aligned HEMT as described above
, The potential on the substrate 21 side is raised by the p-type GaAs layer 23 to improve the confinement effect of 2DEG. However, the leak between the source / drain n ⁺ layer 29 and the source / drain n ^+.
The short channel effect caused by the supply of electrons from the layer 29 to the 2DEG layer 32 is unavoidable.

Therefore, when the gate length is shortened, the threshold voltage V _th is shifted to the negative side, the drain conductance is deteriorated, and the device characteristics are deteriorated, which is a serious problem.

In addition, since the depletion layer spreads directly under the source / drain n ⁺ layer 29, the charges generated by the incidence of α rays are easily collected, and when a memory or the like is configured, there is a problem that it is vulnerable to a soft error.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device which can obtain excellent characteristics even with a short gate length (for example, 1 μm or less) and at the same time has improved resistance to soft errors. And

[Means for Solving Problems] A semiconductor device according to the present invention has a p-type semiconductor layer formed around a source layer and a drain layer formed in an undoped semiconductor layer.

[Action]

According to the present invention, the np junction surrounding the source layer and the drain layer is formed in the undoped semiconductor layer, the potential barrier prevents leakage between the source layer and the drain layer, and the source layer and the drain layer form the 2DEG layer. The supply of electrons to is blocked.

Further, the expansion of the depletion layer below the source layer and the drain layer is alleviated by the interposition of the p-type semiconductor layer.

〔Example〕

FIG. 1 is a side sectional view of an embodiment of HEMT as a semiconductor device of the present invention.

In this figure, 1 is a substrate made of semi-insulating GaAs, 2
Is an undoped GaAs layer, 3 is an undoped AlGaAs layer, 4 is n
-Type AlGaAs layer, 5 is an n-type GaAs layer, 6 is a heat-resistant gate electrode made of, for example, WSi, 7 is a p-layer as a p-type semiconductor layer, 8 is a source / drain n ⁺ layer, 9 and 10 Is a source electrode and a drain electrode, both of which are made of AuGe alloy. 11 is a 2DEG layer.

2A to 2C are side sectional views for explaining the method for manufacturing the semiconductor device of the present invention shown in FIG.

In these figures, the same symbols as those in FIG. 1 indicate the same parts, and 12 is an insulating film.

 Next, the manufacturing process will be described.

First, as shown in FIG. 2A, an undoped GaAs layer 2 to an n-type GaAs layer 5 are sequentially epitaxially grown on a substrate 1 made of semi-insulating GaAs.

Next, as shown in FIG. 2B, after the heat resistant gate electrode 6 is formed, ion implantation is carried out by using the heat resistant gate electrode 6 as a mask so that the undoped GaAs layer 2 and the undoped AlGaAs layer 3 are formed. The p layer 7 is formed in a self-aligned manner.

At this time, the n-type AlGaAs layer 4 and the n-type GaAs layer 5 remain n-type because the concentration of the implanted p-type ions is low. In addition, p-type ions are undoped GaAs on which the 2DEG layer 11 is formed.
Since it is not injected into the interface between the layer 2 and the undoped AlGaAs layer 3, the interface is not disturbed by the ion implantation.

Next, as shown in FIG. 2 (c), an insulating film 12 (for example, SiN2000Å) having an appropriate thickness is formed on the entire surface of the device, and then n-type ions are implanted through the insulating film 12 to form the source / drain n. ⁺ Layer 8 is formed.

At this time, since the heat-resistant gate electrode 6 and the insulating film 12 attached to the side surface thereof serve as a mask, the source / drain n ⁺ layer 8
Is separated from the gate by the thickness of the insulating film 12 attached to the side surface of the heat resistant gate electrode 6.

Moreover, since the n-type ions are implanted at a higher concentration than the p-type ions, the p-type is inverted to the n-type in the region where the n-type ions are implanted.

Then, if the source electrode 9 and the drain electrode 10 are formed after removing the insulating film 12, the HEMT having the structure shown in FIG.
Is obtained.

 Next, the operation of the present invention will be described.

Also in the HEMT shown in FIG. 1, electrons are supplied from the n-type AlGaAs layer 4 to the undoped GaAs layer 2 due to the difference in electron affinity, and the 2DEG layer 11 is formed in the undoped GaAs layer 2. Since the 2DEG layer 11 is formed in the undoped GaAs layer 2, the electrons flowing therein are not affected by the impurity diffusion and a high mobility can be obtained.

By injecting through the insulating film 12 between the heat-resistant gate electrode 6 and the source electrode 9 and the drain electrode 10, the source / drain n ⁺ layer 8 having a low resistance value is self-aligned sufficiently near the heat-resistant gate electrode 6. Since it is formed to be high, a high transconductance can be obtained relatively easily.

 Up to this point, it is similar to the conventional HEMT.

However, in this invention, the source-drain n ⁺ for the layer 8 surrounds the p layer 7 undoped GaAs layer 2 and the undoped AlGaAs layer 3, the source-drain n between ⁺ layer 8 leaks and source-drain n ⁺ The electron supply from the layer 8 to the 2DEG layer 11 is significantly reduced by the potential barrier formed by the p-layer 7.

Therefore, even if the gate length is shortened (1 μm or less), the short channel effect is reduced, the amplifying action of the electrons generated by the incidence of α rays is suppressed, and the α ray resistance is also improved to obtain excellent characteristics. be able to.

Further, at the same time, the spread of the depletion layer below the source / drain n ⁺ layer 8 is relaxed by the presence of the p layer 7, so that it is difficult to collect the generated charges even when the α ray is incident, and the memory or the like is configured. The resistance to soft errors in the case of doing is also improved.

In the case of HEMT, the source / drain n ⁺ from the 2DEG layer 11
The region that occupies layer 8 is n-type AlGaAs when current is flowing.
Since electrons are supplied from the layer 4, it is n-type, but when electrons are not supplied when pinch off by applying a gate voltage (negative voltage), it is p-type. Therefore, at the time of pinch-off, n ⁺ -p-i-p-
It becomes n ⁺ , and an np junction is generated in the current path, which shows a very excellent pinch-off effect. On the other hand, in MESFET, p under the n ⁺ layer
Although there are layers, the current path is n ⁺ -i- even at pinch-off.
Since it is n ⁺ , the effect is small when proportional to HEMT. As described above, the short channel effect of the HEMT of the present invention can be further suppressed.

Although the GaAs HEMT has been described in the above embodiment, the same applies to the InP HEMT and the like.

Further, the present invention is not limited to HEMT, and may be applied when other compound semiconductor devices (for example, MISFET) are self-aligned.

〔The invention's effect〕

As described above, the present invention provides p around the source and drain layers formed in the undoped semiconductor layer.
Type semiconductor layer is formed, leakage does not occur between the source and drain layers, the supply of electrons from the source and drain layers to the 2DEG layer is blocked, and the depletion layer spreads under the source and drain layers. There is an effect that the short channel effect can be suppressed even if the gate length is shortened, excellent characteristics can be obtained, and resistance to a soft error can be improved when a memory or the like is configured.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an embodiment of a HEMT as a semiconductor device of the present invention, FIG. 2 is a side sectional view for explaining a manufacturing method for realizing the structure shown in FIG. 1, FIG. 3 is a side sectional view showing a conventional semiconductor device. In the figure, 1 is a substrate, 2 is an undoped GaAs layer, 3 is an undoped AlGaAs layer, 4 is an n-type AlGaAs layer, and 5 is an n-type GaAs.
Layer, 6 is a heat resistant gate electrode, 7 is a p layer, 8 is a source / drain n ⁺ layer, 9 is a source electrode, 10 is a drain electrode, 11 is
The 2DEG layer, 12 is an insulating film. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A plurality of semiconductor layers for forming a two-dimensional electron gas layer including an undoped semiconductor layer on which a two-dimensional electron gas layer is formed, and source layers formed on both sides of the two-dimensional electron gas layer. And a drain layer, a source electrode and a drain electrode formed on the source layer and the drain layer, and a gate electrode formed in a region on the two-dimensional electron gas layer on the plurality of semiconductor layers. In the high electron mobility transistor according to claim 1, a p-type semiconductor layer is formed around the source layer and the drain layer formed in the undoped semiconductor layer, and the p-type layer-the undoped semiconductor layer-the p-layer. A semiconductor device, wherein the mold layer is an active layer.