JPH0820662B2 - Control device - Google Patents

Description

The present invention relates to an improvement of a control device for controlling a camera or the like.

[Prior Art] Conventionally used as a control device for a camera or the like.
The CPU is configured so that power is supplied only when the release button of the camera is pressed and the oscillation circuit operates at the same time in order to prevent battery consumption and the like. Here, when an oscillator such as X'tal or Ceralock is used in the oscillator circuit, the operation of the CPU is stopped until the oscillation frequency reaches a predetermined value, and the CPU does not run away with a clock other than the predetermined frequency component. It has become.

[Problems to be Solved by the Invention] In the conventional camera described above, the stabilization time until the oscillation circuit reaches a predetermined frequency is greatly affected by the power supply voltage. If the power supply voltage rise timing after the start of oscillation is different, such as when charging, providing a constant oscillation stabilization time that matches the longest oscillation stabilization time causes a very long release time lag. was there.

The present invention is intended to solve such a problem.

[Means for Solving the Problems] An oscillation circuit, a control circuit that operates according to the oscillation circuit, and a control circuit that causes the control circuit to perform a control operation until a predetermined period elapses after the oscillation circuit starts operating. The control device is provided with a blocking unit that is not provided and a variable unit that changes the predetermined period in which the blocking unit operates according to a power supply voltage.

[Operation] According to the present invention, the waiting time from the start of the operation of the oscillating circuit to the start of the control operation of the control circuit operating according to the oscillating circuit is changed according to the power supply voltage. Is intended to be shortened.

[Embodiment] FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. That is, in FIG. 1, the output VBAT of the battery 8 loaded in the camera is supplied to the motor drive circuit 1 and the strobe circuit 2 through the capacitor 9, and the VDD output is supplied to the VCC detection circuit through the backflow prevention diode 10 and the capacitor 16. 3, linear control drive circuit 4, VDD detection circuit 5,
It is supplied to the operating frequency switching circuit 6 and the sequence control circuit 7. Further, the output of VCC is supplied to the VCC detection circuit 3 and the linear section control drive circuit 4 through the VCC conducting circuit composed of the transistor 11 and the resistors 12 and 13, the choke coil 14, and the capacitor 15, Output V
CCNG is supplied to the linear control drive circuit 4 and the VDD detection circuit 5, and the output VDDNG of the VDD detection circuit 5 is the linear control drive circuit 4, the operating frequency switching circuit 6, and the sequence control circuit 7.
It is connected to the.

FIG. 2 shows the details of the VCC detection circuit 3 which detects the level of VCC. That is, in FIG. 2, the constant current generation circuit
The reference current IS1 of 17 is supplied as the bias current of the comparators 34, 42, 48, 57, and the output VC of the reference voltage generation circuit 18 is connected to the respective inverting input terminals as the reference comparison voltage of each comparator. In addition, VCC is a resistor 22,23,24,25,2
Outputs V1, V2, V3, V4 divided by 6 are resistors 29, 30, 3 respectively.
It is connected to the non-inverting input terminals of comparators 57, 48, 42, and 34 via 1, 32 and detects the predetermined voltage of VCC, but the output of comparator 57 is VC via transistor 56 and resistor 58.
It becomes the output of CNG1, and similarly the output of the comparator 48 is the output of VCCNG2 via the transistor 49 and the resistor 50, the output of the comparator 42 is the transistor 43, the output of VCCNG3 is via the resistor 44, the output of the comparator 34 is the transistor 37 and the resistor 37. 38
Becomes the output of VCCNG4 via.

Resistors 19,20,21, transistor 59, resistors 35,40,46,5
The PUC circuit composed of 4, MOS transistors 36, 41, 47, 55 is a false judgment prevention circuit when VCC drops.

FIG. 3 shows the details of the VDD detection circuit 5 for detecting the VDD level. That is, in FIG. 3, the constant current generating circuit 60
The reference currents IS2 and IS3 are supplied as the bias currents of the comparators 78, 79, 80 and 81, and the output ΣVt of the reference voltage generation circuit 61.
h is VDD to the non-inverting input terminal of comparator 78,79,80,81
Output voltage divided by resistors 73,74,75,76,77 V5, V6, V7, V
8 is connected to the inverting input terminals of the comparators 81, 80, 79, 78, respectively.

Here, the output of VCCNG1 and the output of comparator 81 are output of VDDNG1 through the OR gate 68, the output of VCCNG1 and the output of comparator 80 are output of VDDNG2 through the OR gate 67,
The output of VCCNG1 and the output of the comparator 79 are output of VDDNG3 through the OR gate 66, and the output of VCCNG1 and the output of the comparator 78 are output of VDDNG4 through the OR gate 65.

FIG. 4 shows an oscillator circuit and a clock switching circuit. In FIG. 4, the NAND gate 126, X'tall2
2.Feedback resistor 125 and capacitors 123 and 124 form an oscillator circuit, and input to NAND gate 126 ▲ ▼
Controls the operation of oscillation. When both VDDNG1 and VDDNG3 are L level, inverter 127, AND gate 13
7. Through the OR gates 139 and 140 and the AND gate 141, the output of the same frequency as the oscillation circuit appears in XiN, and when only VDDNG3 is at the H level, through the inverter 127, the frequency divider 128, the AND gate 138, the OR gates 139 and 140, and the AND gate 141. The output obtained by dividing the frequency of the oscillator circuit by 2 appears in XiN and V
When DDNG1 is H level, inverter 127, frequency divider 128,12
9,130,131,132, the output was 2 ⁵ divides the frequency of the oscillator circuit through the AND gate 141 appears at XIN.

FIG. 5 shows details of the sequence control circuit 7 including the oscillation stabilization waiting circuit. That is, in FIG. 5, the state of the switch is the CPU 20 through the switch interface 209.
Captured in 0, counter 201, comparator 202, register 203, RS flip-flop 204, NAND gate 20
5. The inverter 206 constitutes an oscillation stabilization standby circuit.

FIG. 6 shows a series of operations of the camera,
When the switch SW1 is turned on in the SW1WAIT state, battery check, distance measurement, and photometry are performed, and if it is determined that flash photography is necessary, charging is immediately started. After charging, when the switch SW2 of the camera is turned on, AF control, SH control, and winding are performed, and the camera returns to SW1WAIT again. Where SW1WA
If the IT does not turn on the predetermined switch for a predetermined time, or if the power supply voltage drops below a predetermined level due to flash charging, the operation of the oscillation circuit is stopped.

Next, these oscillation control methods will be described with reference to the flowcharts of FIGS. 7 and 8.

FIG. 7 is a flow chart in the SW1WAIT state. First, the timer 1 built in the CPU 200 of FIG. 5 is initialized and then started, and then the MAI is executed in flow 502.
I will check the status of NSW. If the MAIN SW is on, the flow proceeds to step 503 to check the state of the switch SW1, and if the switch SW1 is also on, BC is set as shown in FIG.
Start operation. If either MAINSW or SW1 is off, check the status of ALENDL in flow 504, and if it is reset, then check the status of the back cover in flow 505, and check that this back cover is closed. And and the flow
Only when the DX code is detected at 509, as shown in FIG. 6, the film idling operation is started. See also ALENDL
If is set, check the condition of the back cover with flow 506. If the back cover is opened here, use ALENDL with flow 507.
Is reset and after waiting for a certain period of time for absorbing chattering, the flow proceeds to flow 511. In the flow 511, it is determined whether or not the value of the timer 1 has reached Th, and the switch detection operation is continued until the timer value reaches Th. When timer 1 reaches Th, proceed to flow 512 to stop the counting operation of timer 1 and set VCCEN to L at flow 513.
To level.

In FIG. 5, when the switch SW1 is off, the SW10N output goes to L level and VCCEN goes to L level.
The output of 07 also becomes L level, therefore the output VCCL of the VCC latch transistor 208 becomes high impedance,
The power supply to the VCC system shown in FIG. 1 is stopped, and the level of VCC gradually decreases as shown in the timing chart of FIG.

When VCC drops in the VCC detection circuit of FIG. 2 and the divided voltage value V1 of VCC becomes lower than the reference voltage VC, the output VCCNG1 through the comparator 57, the transistor 56 and the resistor 58 becomes H level.

Further, in the VDD detection circuit of FIG. 3, when VCCNG1 becomes H level, the transistors 70 and 69 are turned on via the inverters 62 and 64, and the output currents IS2 and IS3 of the constant current generation circuit 60 are not supplied. Outputs of 78, 79, 80, 81 are all H
As a result, the output VDDNG1 of the OR gate 68 also becomes H level.

Returning again to the flowchart of FIG. 7, the flow 513
After turning off the power to VCC, reset the timer 2 built in the CPU200 and then start it. Flow 51
It waits until the value of timer 2 reaches TDC at 6, but during this time, after turning off the power supply to VCC, as described above, VDD
The time is set such that VCC drops to a level close enough to NG1 going to H level, and when timer 2 reaches this time, the counting operation of timer 2 is stopped, and flow 51
At 8, the CPU 200 sets the oscillation stabilization waiting time ts in the register 203. Next, in step 519, the output of the CPU 200 is set to L level to reset the RS flip-flop 204 and the counter 201 via the inverter 206. Then, in flow 520, the ▲ ▼ output of the CPU 200 is set to H.
When set to level, the output of the NAND gate 205 becomes L level, and this output is added to the input of the NAND gate 126 which constitutes the oscillation circuit of FIG. 4, and oscillation is stopped. In this state, the clock is not supplied to the CPU 200 via XiN, so the CPU 200 stops its operation and is set to the hold state, and the execution of the program is stopped in the flow 520 of FIG. In this state, for example, when the switch SW1 is turned on, SW10N is passed through the switch interface 209.
The output becomes H level, and the transistor 208 is turned on through the OR gate 207.

When VCCL becomes L level in FIG. 1, the transistor 11 is turned on through the resistors 12 and 13, and the power supply to the VCC system is started. Also, as shown in the VCC waveform in Fig. 9, when VCC reaches a predetermined level, the VCC voltage divider in the VCC detection circuit in Fig. 2
V1 exceeds the reference voltage VC, the output of the comparator 57 is inverted, and the output of VCCNG1 is L through the transistor 56 and the resistor 58.
Level.

On the other hand, in the VDD detection circuit of FIG. 3, since VCCNG1 becomes L level, the constant current generation circuit 60, the reference voltage generation circuit 61, the resistors 73,74,75,76 via the inverters 62,63,64. ,
All 77 are enabled. Where the comparator
In 81, the output of the reference voltage generation circuit 61 is divided by ΣVth and VDD.
When V5 is higher than V5, the output of the comparator 81 becomes L level, and the output VDDNG1 of the NOR gate 68 also becomes L level.

Here, when VDDNG1 becomes L level, the RS flip-flop 204 of FIG. 5 is set and the output thereof becomes L level, so that the output of the NAND gate 205 is at H level.
The oscillator circuit shown in FIG. 4 is activated. When the clock supply from XiN is started, the counter 201 flows
Start the counting operation as indicated by 21. The comparator 202 compares the value of the counter 201 with the value ts set in the register 203, and the value of the counter 201 is ts.
When it becomes equal to, the START output becomes H level. Immediately after this output is transmitted to the CPU 200, the CPU 200 starts executing the program, proceeds to flow 524, and sets VCCEN to the H level to keep the VCC system energized. Then, the process proceeds to the flow 500 to operate the timer 1 to start the sensing of each switch as described above.

Next, a strobe charging control method will be described with reference to the flowchart of FIG.

First, when the start of strobe charging is started in flow 600, the charging of a strobe charging circuit (not shown) is started, and subsequently, the value of timer 1 is reset in flow 601 and then timer 1 is started in flow 602. Flow 603
Checks whether the charge level of the strobe main capacitor has reached the specified value. At the end of charge, CGUP becomes H level. At that time, proceed to flow 606 to stop timer 1, and then At 607, the charging is terminated by controlling the strobe charging stop. flow
When the strobe is not charged in 603, the flow 604 checks whether the value of timer 1 has reached TC, and when it is,
Similar to the case where the charging is completed, the flow proceeds to Steps 606 and 607 to end the charging of the strobe.
Check the status of VDDNG1 with.

Here, as shown in the timing chart of FIG.
When the strobe charge is started, VCC drops rapidly. Therefore, in the VCC detection circuit in Fig. 2, the divided voltage value V1 of VCC is the reference voltage.
It becomes lower than VC, the output of the comparator 57 is inverted to the L level, and the output of VCCNG1 goes high through the transistor 56 and the resistor 58.
Level.

On the other hand, when VCCNG1 becomes H level in the VDD detection circuit in FIG. 3, the constant current generation circuit 60 is disabled via the inverters 62, 64 and transistors 69, 70, and its output current IS2, IS3 is no longer supplied. , The output of the comparator 81 becomes H level. Therefore, the output VDDNG1 of the OR gate 68 becomes the H level, and when this is detected in the flow 605, the process immediately proceeds to the flow 606, and the oscillation stabilization waiting time t _L is set from the CPU 200 to the register 203. However, the value of t _L is set to a value longer than the oscillation stabilization wait time t _S during SWWAIT described above. Then, in Flow 607, CPU ▲
▼ When the output is at L level, RS flip-flop 20
4 is reset, while the counter 201 is also reset via the inverter 206.

Then, when the output ▲ ▼ is set to the H level in the flow 608, the output ▲ ▼ of the NAND gate 205 becomes the L level, and the operation of the oscillation circuit of FIG. 4 is stopped.
The program execution operation of the CPU 200 is also stopped. Where CPU2
As shown in Fig. 10, the drive power supply voltage VDD of 00 drops at the same time as the start of strobe charging, but the VCC output drops faster due to the consumption current and the reverse transistor effect of the transistor 11, so the above VCC rises to a predetermined level. The drive power supply voltage VDD of the CPU 200 is sufficient even when it reaches the limit, and when oscillation stops, the current consumption of the CPU 200 becomes very small, so the backup capacitor 16 enables sufficient backup, as shown in Fig. 10. As described above, when the charging of the strobe progresses and the charging of the capacitor reaches a predetermined level, the battery voltage VBAT recovers and VCC rises.

When the divided voltage value V1 of VCC becomes higher than the reference voltage VC in the VCC detection circuit of FIG. 2, the output of the comparator 57 is inverted to H level, and the output VCCNG1 via the transistor 56 and the resistor 58 becomes L level. At the same time, in the VDD detection circuit in Fig. 3, VCCNG1
By reversing the output, inverters 62, 64, transistors 69,
The constant current generation circuit 60 is enabled via 70, and the transistors 71, 72 are turned on via the inverters 62, 63, so that the reference voltage generation circuit 61 and the resistors 73, 74, 75, 76, 77 are enabled. . The comparator 81 compares the divided voltage value V5 of VDD with the reference voltage ΣVth. When VDD is higher than that value, the output of the comparator 81 becomes L level and the output VDDNG1 of the OR gate 68 also becomes L level.

In FIG. 5, when VDDNG1 becomes L level, the RS flip-flop 204 is set and its output becomes L level,
The output of the NAND gate 205 is inverted to H level.

In the oscillator circuit shown in FIG. 4, oscillation is started by this output, and a clock is supplied to the CPU 200 and the counter 201 through the XiN output. The driving power supply voltage VDD of the CPU 200 rapidly drops at the same time as the oscillation starts and reaches the CPU operation minimum guaranteed voltage or less, but at this point the count value of the counter 201 has not reached the value of t _L set in the register 203, so ,CPU
The program execution operation of 200 is not started, and CPU 200 does not run away. When the count of the counter 201 progresses and reaches the oscillation stabilization time t _L set in the register 203, the START output of the comparator 202 becomes H level, and this output signal causes the CPU 200 to start the program execution operation.

In the flowchart of FIG. 8, flows 609 to 611 correspond to the above-mentioned hardware processing, and when the START output becomes the H level, the flow proceeds to flow 603 again to check whether or not the strobe charging is completed. Start.

In the above embodiment, in order to set the oscillation standby time when the hold state is set by the strobe charging operation to be longer than the standby time of the clock oscillation circuit when returning from the normal switch input standby state, oscillation is generated in the program. Before stopping, the oscillation stabilization time corresponding to the voltage level was secured by setting the time to wait in advance in the register.However, in addition to this, during switch input standby and strobe charging. Varying the voltage level for releasing the hold is also an effective means for waiting for oscillation stabilization. That is, the level at which the hold is released during normal switch input standby is defined by the VCC divided voltage value V1 and VCCNG1 is set to L.
It is configured to release when it reaches the level, on the other hand, when returning from the hold state at the time of strobe charging,
If the divided voltage value V2 of VCC is compared with the reference voltage VC and configured to be released by VCCNG2, the return voltage from the hold state at the time of strobe charging becomes higher, so VDD drops to a low level at the start of oscillation. Becomes relatively high,
This is an advantageous direction for the oscillation state. Therefore, in this case, it is not necessary to intentionally change the oscillation stabilization waiting time at the time of switch input waiting and at the time of strobe charging.

[Effects of the Invention] As described above, according to the present invention, it is possible to shorten the waiting time from the start of the operation of the oscillation circuit to the start of the control operation of the control circuit that operates according to the oscillation circuit. Is.

[Brief description of drawings]

The drawings show an embodiment of the present invention. FIG. 1 is an explanatory diagram of the entire configuration, FIG. 2 is an explanatory diagram of a VCC detection circuit for detecting a VCC level, and FIG. 3 is a VDD level. FIG. 4 is an explanatory diagram of a VDD detection circuit, FIG. 4 is an explanatory diagram of an oscillation circuit and a clock switching circuit, FIG. 5 is an explanatory diagram of a sequence control circuit including an oscillation stabilization standby circuit, and FIG. 6 is an explanatory diagram of the operation of the entire camera. FIG. 7 is an explanatory diagram when the camera is on standby until the release operation is performed, FIG. 8 is an explanatory diagram during strobe charging control, and FIG. 9 is an explanatory diagram of timing when the camera is in the release operation standby state, FIG. 10 is an explanatory diagram of timings during strobe charging. 1 ... Motor drive circuit, 2 ... Strobe circuit, 3 ... VC
C detection circuit, 4 ... Linear control drive circuit, 5 ... VDD detection circuit, 6 ... Operating frequency switching circuit, 7 ... Sequence control circuit, 8 ... Battery, 17,60 ... Constant current generation circuit, 1
8,61 …… Reference voltage generation circuit, 200 …… CPU, 201 …… Counter.

Claims (1)

[Claims] 1. An oscillation circuit, a control circuit that operates according to the oscillation circuit, and a blocking circuit that prevents the control circuit from performing a control operation until a predetermined period has elapsed after the oscillation circuit started operating. A control device comprising: means and variable means for changing the predetermined period in which the blocking means operates according to a power supply voltage.