JPH0820948B2 - Advance control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prior control device, and more particularly to a pipeline control prior control device used in an information processing device.

[0002]

2. Description of the Related Art Conventionally, various measures have been taken in this type of advanced control device in order to improve the efficiency of pipeline processing.

For example, when executing an instruction for performing an operand fetch with a time difference between the operand fetch for the main memory and the operand fetch for the register, the address arithmetic unit is used during the idle time during the processing of the previous instruction. A method for calculating the address of the main memory operand of an instruction and sending a fetch request to the main memory
It is disclosed in Japanese Patent Publication No. 27429.

Further, by decoding a plurality of instructions at the same time, and when the decoded plurality of instructions are identified as executable in parallel, the plurality of instructions are combined and executed in synchronization with a plurality of pipeline processes at all times. A technique for improving the efficiency of pipeline processing is disclosed in Japanese Patent Application Laid-Open No. 2-130635.

In addition to the above-mentioned techniques, as a technique for improving the efficiency of pipeline processing, the technique disclosed in Japanese Patent Laid-Open No. 2-89133 and the technique disclosed in Japanese Patent Laid-Open No. 2-268329 are known. Has been.

However, in the operand prefetching process in this type of advance control device, when a wait factor occurs in each stage of the pipeline, that is, when the pipeline is disturbed, the wait factor is eliminated. During this period, the processing in the stage in which the wait factor has occurred and its upper stage is stopped.

[0007]

In the above-described prior art control apparatus, when a wait factor is generated in each stage of the pipeline, the stage in which the wait factor is generated and its upper layer are waited until the wait factor is resolved. Since the processing in the stage is stopped, there is a problem that the performance is remarkably deteriorated when executing a program in which the pipeline is often disturbed.

Therefore, an object of the present invention is to make effective use of the waiting time when a waiting factor occurs in each stage of the pipeline, and to significantly improve the performance of pipeline processing. Is provided.

[0009]

A preceding control device according to the present invention is a preceding control device of an information processing device for prefetching operands by pipeline processing, which is sequentially sent.
Means for imparting <br/> processing consecutive numbers to prefetch processing request each of the operands come, the process number assigned to prefetch processing request each provided and said operand to each stage of the pipeline process Beyond the operand
At each stage for the processing request and the processing request
Means for around have to correspond to the kicking process result, and detecting means for detecting the occurrence of the waiting factor of the processing for the prefetch processing request for the operand at each stage of the pipeline process, provided in each stage of the pipeline process
And a means for receiving and processing a prefetch processing request of the subsequent operand and its processing result from the upper stage of the stage when the occurrence of the wait factor is detected by the detection means, and an operand extracted by the pipeline processing Is stored in association with the processing number given to the prefetch processing request of the operand, and means for reading the operand in the order of the processing number from the storage means.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the I stage receives an instruction sent from the instruction fetch stage, which is an upper stage, in the instruction registers (IR) 1 and 2, and decodes the instruction and the logical address of the operand specified by the address syllable in the instruction word. Is a stage for generating.

That is, the register number and displacement (displacement) of each of the base register (BR) 4 and the index register (XR) 5 are held in the instruction registers 1 and 2 and based on the address syllable in the instruction word selected by the selector 3. And are extracted. The adder (AD) 6 adds the index result of the base register 4 and the index register 5 based on the register number and the displacement and the displacement to obtain the logical address of the operand. Input to the L stage.

The L stage stores the logical address of the operand sent from the I stage in the logical address register (L
AR) 7, 8 to receive the absolute address translation buffer (T
LB) 10 is the stage for obtaining the absolute address of the operand by indexing.

That is, the absolute address of the operand is obtained by indexing the absolute address translation buffer 10 with the logical address of the operand held in the logical address registers 7 and 8 and selected by the selector 9.
The absolute address of that operand becomes the input to the next P stage.

The P stage stores the absolute address of the operand obtained in the L stage in the absolute address register (PA
R) 11, 12, receive the operand cache (O
C) The stage where the operand is obtained by indexing 14.

That is, the absolute address registers 17, 1
The operand is obtained by indexing the operand cache 14 with the absolute address of the operand held in 2 and selected by the selector 13, and that operand becomes the input to the next O stage.

The O stage is a stage for buffering the operand obtained in the P stage in the operand buffer (OB) 15, and the output of the operand buffer 15 is sent to the operation stage which is a lower stage. In the O stage, when the operands cross word boundaries, the data output from the operand buffer 15 is aligned.

In this embodiment, a processing number is given to a processing request from each stage of the above-mentioned pipeline to its lower stage. The processing number of the I stage is given to the L stage from the processing number register (IN) 21 (initial value “0”), and is incremented by the counter 22 every time one processing request is sent to the L stage.

The processing numbers generated in the I stage are processing number registers (LN) 2 in the L stage and the P stage, respectively.
5, 26 and process number registers (PN) 28, 29, and are used as write addresses for the operand buffer 15 in the O stage.

The I stage is sent to the L stage, the L stage is sent to the P stage, and the P stage is sent to the O stage via selectors 24, 27, 30, and 33, respectively. However, in the O stage selector 33, one of the processing number from the P stage selector 30 and the read address generated by the address register 31 and the counter 32 is selected, and the operand buffer 1
5 is supplied.

When a wait factor is generated in each stage of the above pipeline, the detection circuit 16 detects the occurrence of the wait factor. When the detection circuit 16 detects the occurrence of a wait factor in each stage, it outputs a hold signal to the register of each stage and a process number register, and outputs a select signal to the selector of each stage, thereby waiting time due to the occurrence of the wait factor. Then, control is performed so that the subsequent instruction in each stage is processed first.

2 to 4 are diagrams showing the processing operation of an embodiment of the present invention. 2 shows a processing operation when a wait factor occurs in the I stage, FIG. 3 shows a processing operation when a wait factor occurs in the L stage, and FIG. 4 shows a process when a wait factor occurs in the P stage. It shows the operation. A processing operation when a wait factor occurs in each stage of the pipeline will be described with reference to FIGS.

In the I stage, when the instructions A to E are sequentially sent from the instruction fetching stage which is the upper stage, the processing numbers "0" to "4" are given to the instructions A to E by the processing number register 21 and the counter 22, respectively. Is added. As shown in FIG. 2, when the detection circuit 16 detects the occurrence of a wait factor when the instruction B is held in the instruction register 1 at the I stage, the instruction B is returned in response to the hold signal from the detection circuit 16. Holds to 1. The instruction B is held in the instruction register 1 until the wait factor is resolved.

At this time, the processing number "1" given to the instruction B by the processing number register 21 and the counter 22.
Is stored in the process number register 23 and held in response to a hold signal (not shown) from the detection circuit 16. Similarly to the instruction B stored in the instruction register 1, the processing number “1” of the instruction B is also held in the processing number register 23 until the wait factor is resolved.

As the wait factor in the I stage, for example, the processing of the instruction word of the instruction register 1 is performed until the base register 4 and the index register 5 designated by the address syllable of the instruction word of the instruction register 1 are updated by the preceding instruction. There is a waiting factor that is kept waiting, that is, a register hazard.

When the instruction B is held in the instruction register 1, the instruction C following the instruction B is stored in the instruction register 2. Unless a new wait factor occurs in the instruction C stored in the instruction register 2, the processing of the instruction C is performed prior to the processing of the instruction B by using the waiting time of the processing of the instruction B. . That is, the instruction C stored in the instruction register 2 is selected by the selector 3 according to the select signal from the detection circuit 16, and the adder 6 generates the logical address C1 of the operand of the instruction C and sends it to the L stage. .

At this time, the processing number "2" of the instruction C generated by incrementing the processing number "1" of the processing number register 21 by the counter 22 is generated according to the select signal (not shown) from the detection circuit 16. Selected by the selector 24,
It is sent to the L stage.

Even if the logical address C1 of the operand of the instruction C is generated and sent to the L stage, if the wait factor of the instruction B is not resolved, the instruction D next to the instruction C is the same as the processing of the instruction C. It is stored in the register 2 and selected by the selector 3. The adder 6 generates the logical address D1 of the operand of the instruction D and sends it to the L stage.

In this case as well, like the processing number of the instruction C,
The processing number “2” of the processing number register 21 is counted by the counter 22.
The processing number "3" of the instruction D generated by incrementing by is sent to the L stage via the selector 24.

When the wait factor for the instruction B is eliminated when the processing of the instruction D is completed in the I stage, the detection circuit 1
The hold signal from 6 to the instruction register 1 and the processing number register 23 and the select signal to the selectors 3 and 24 are released. Therefore, since the selectors 3 and 24 select the processing number “1” of the instruction B of the instruction register 1 and the processing number B of the processing number register 23, the logical address B1 and the processing number “1” of the operand of the instruction B are transferred to the L stage. Sent out.

As described above, when a waiting factor occurs in the instruction B at the I stage, the waiting time is used in the I stage until the waiting factor of the instruction B is eliminated, and the subsequent instruction C,
Since D is processed in advance, the processing is performed in the order of instructions A, C, D, B, and E in each stage after the I stage. At this time, the processing numbers of the instructions A, C, D, B and E are carried around by the processing number registers 25 and 28.

That is, in the I stage, instructions A, C,
Logical addresses A1, C1, D of operands D, B, E
1, B1, E1 are sequentially generated and sent to the L stage.
In the L stage, the absolute addresses A2, C2, D2, B2, E2 of the operands of the instructions A, C, D, B, E are sequentially obtained and sent to the P stage. In the P stage, instructions A, C,
Operands A3, C3, D3, B3, E3 of D, B, E
Are sequentially obtained and sent to the O stage.

At the O stage, the operands A3, C3, D3, B3, and E3 of the instructions A, C, D, B, and E are the processing numbers "0" and "2" of the instructions A, C, D, B, and E, respectively. ，
"3", "1", and "4" are sequentially buffered in the operand buffer 15 as write addresses. However, instruction A
Operands A3 to E3 of ~ E are operand buffers 15
When read from, the order is read addresses "0" to "4" generated by the address register 31 and the counter 32.

As shown in FIG. 3, when the detection circuit 16 detects the occurrence of the wait factor when the logical address B1 of the operand of the instruction B is held in the logical address register 7 in the L stage, the detection circuit 16 holds it. The logical address B1 is held in the logical address register 7 in response to the signal. The logical address B1 is held in the logical address register 7 until the wait factor is resolved.

At this time, the processing number "1" sent to the L stage together with the logical address B1 is stored in the processing number register 25 and held in response to a hold signal (not shown) from the detection circuit 16. . Similarly to the logical address B1 stored in the logical address register 7, the processing number "1" of the instruction B is also held in the processing number register 25 until the wait factor is resolved.

As the wait factor in the L stage, there is, for example, a wait factor such that the processing of the logical address stored in the logical address register 7 is delayed due to a miss hit of the absolute address translation buffer 10.

When the logical address B1 is held in the logical address register 7, the logical address C1 of the operand of the instruction C next to the instruction B is stored in the logical address register 8. If a new wait factor does not occur at the logical address C1 stored in the logical address register 8, the processing of the logical address C1 precedes the processing of the logical address B1 by using the waiting time of the processing of the logical address B1. Will be done. That is, the logical address C1 stored in the logical address register 8 is selected by the selector 9 according to the select signal from the detection circuit 16, and the absolute address C2 of the operand of the instruction C is obtained by the index of the absolute address translation buffer 10. It is sent to the P stage.

At this time, the processing number "2" of the instruction C sent from the I stage and held in the processing number register 26 is the select signal (not shown) from the detection circuit 16.
Is selected by the selector 27 in accordance with the above, and is sent to the P stage.

Even if the absolute address C2 of the operand of the instruction C is generated and sent to the P stage, the logical address B1
If the wait factor of is not eliminated, the logical address D1 of the operand of the instruction D next to the instruction C is stored in the logical address register 8 and selected by the selector 9 as in the processing of the logical address C1. The absolute address D2 of the operand of the instruction D is obtained by the index of 10 and is sent to the P stage.

Also in this case, like the processing number of the instruction C,
The processing number “3” of the instruction D sent from the I stage and held in the processing number register 26 is sent to the P stage via the selector 27.

When the waiting factor for the logical address B1 is eliminated when the processing of the logical address D1 is completed in the L stage, the hold signal from the detection circuit 16 to the logical address register 7 and the processing number register 25 and the selectors 9, 27. The select signal to is released. Therefore, since the selectors 9 and 27 select the logical address B1 of the logical address register 7 and the processing number "1" of the instruction B of the processing number register 25, the absolute address B2 and the processing number "1" of the operand of the instruction B become P. It is sent to the stage.

At this time, in the I stage, the wait factor of the logical address B1 is eliminated, so that the L stage of the lower stage is cleared.
Since the processing of the logical address B1 is performed in the stage, the processing of the instruction E held in the instruction register 1 is held by the hold signal from the detection circuit 16. L
When the processing of the logical address B1 in the stage is completed, I
The hold state of the processing of the instruction E in the stage is released, the logical address E1 of the operand of the instruction E is generated and sent to the L stage together with the processing number "4" of the instruction E.

As described above, when a wait factor occurs in the logical address B1 of the operand of the instruction B in the L stage, the subsequent instruction C is used in the L stage by using the waiting time until the wait factor of the logical address B1 is resolved. , D, the logical addresses C1 and D1 of the operands are processed in advance, so that the instructions A, C, D, and
The processing is performed in the order of B and E. At this time, command A,
The processing number of each of C, D, B, and E is the processing number register 28.
Carried around by.

That is, in the I stage, the logical addresses A1 to E1 of the operands of the instructions A to E are sequentially generated and sent to the L stage. In the L stage, instructions A, C, D,
Absolute addresses A2, C2, D2 of B and E operands,
B2 and E2 are sequentially obtained and sent to the P stage. In the P stage, the operands A3, C of the instructions A, C, D, B, E
3, D3, B3, E3 are sequentially obtained and sent to the O stage.

At the O stage, the operands A3, C3, D3, B3, and E3 of the instructions A, C, D, B, and E are the processing numbers "0" and "2" of the instructions A, C, D, B, and E, respectively. ，
"3", "1", and "4" are sequentially buffered in the operand buffer 15 as write addresses. However, instruction A
Operands A3 to E3 of ~ E are operand buffers 15
When read from, the order is read addresses "0" to "4" generated by the address register 31 and the counter 32.

As shown in FIG. 4, when the detection circuit 16 detects the occurrence of a wait factor when the absolute address B2 of the operand of the instruction B is held in the absolute address register 11 in the P stage, the detection circuit 16 holds it. In response to the signal, absolute address B2 is absolute address register 1
Holds to 1. The absolute address B2 is held in the absolute address register 11 until the wait factor is resolved.

At this time, the processing number "1" sent to the P stage together with the absolute address B2 is stored in the processing number register 28 and held in response to a hold signal (not shown) from the detection circuit 16. . Similarly to the absolute address B2 stored in the absolute address register 11, the processing number "1" of the instruction B is also held in the processing number register 28 until the wait factor is resolved.

The wait factor in the P stage is, for example, a wait factor such that the processing of the absolute address stored in the absolute address register 11 is delayed due to a miss hit of the operand cache 14.

When the absolute address B2 is held in the absolute address register 11, the absolute address C2 of the operand of the instruction C next to the instruction B is stored in the absolute address register 12. If no new wait factor occurs in the absolute address C2 stored in the absolute address register 12, the processing of the absolute address C2 precedes the processing of the absolute address B2 by using the waiting time of the processing of the absolute address B2. Will be done. That is, the absolute address C2 stored in the absolute address register 12 is selected by the selector 13 in response to the select signal from the detection circuit 16, the operand C3 of the instruction C is obtained by the index of the operand cache 14, and is sent to the O stage. It

At this time, the processing number "2" of the instruction C sent from the L stage and held in the processing number register 29 is the select signal (not shown) from the detection circuit 16.
Is selected by the selector 30 according to the above, and is sent to the O stage.

Even if the operand C3 of the instruction C is generated and sent to the O stage, if the wait factor of the absolute address B2 is not resolved, the operand D of the instruction D next to the instruction C is processed as in the processing of the absolute address C2. The absolute address D2 is stored in the absolute address register 12 and selected by the selector 13, and the operand D3 of the instruction D is obtained by the index of the operand cache 14 and sent to the O stage.

Also in this case, like the processing number of the instruction C,
The processing number “3” of the instruction D sent from the L stage and held in the processing number register 29 is sent to the O stage via the selector 30.

If the wait factor for the absolute address B2 is eliminated when the processing of the absolute address D2 is completed in the P stage, the detection circuit 16 causes the absolute address register 11
Also, the hold signal to the process number register 28 and the select signal to the selectors 13 and 30 are released. Therefore, in the selectors 13 and 30, the absolute address register 11
Absolute address B2 and instruction B of the processing number register 28
Since the processing number "1" is selected, the operand B3 of the instruction B and the processing number "1" are sent to the O stage.

At this time, in the L stage, the wait factor of the absolute address B2 is eliminated, so that the P of the lower stage is removed.
Since the processing of the absolute address B2 is performed in the stage, the processing of the logical address E1 of the operand of the instruction E held in the logical address register 7 is held by the hold signal from the detection circuit 16. When the processing of the absolute address B2 in the P stage is completed, the hold state of the processing of the logical address E1 in the L stage is released, the absolute address E2 of the operand of the instruction E is obtained, and the processing number "4" of the instruction E and P It is sent to the stage.

In the I stage, the processing of the logical address E1 is held in the L stage of the lower stage due to the elimination of the wait factor of the absolute address B2. Therefore, the processing of the instruction F held in the instruction register 1 is detected. It is held by the hold signal from the circuit 16. P
When processing of absolute address B2 on the stage is completed, L
Since the hold state for processing the logical address E1 in the stage is released, the hold state for processing the instruction F in the I stage is released. As a result, the logical address F1 of the operand of the instruction F is generated and sent to the L stage together with the processing number "5" of the instruction F.

As described above, when a wait factor occurs in the absolute address B2 of the operand of the instruction B in the P stage, the subsequent instruction C is used in the P stage by using the waiting time until the wait factor of the absolute address B2 is resolved. , D, the absolute addresses C2 and D2 of the operands are processed in advance, so that in each stage after the P stage, instructions A, C, D,
Processing is performed in the order of B, E, and F.

That is, in the I stage, the logical addresses A1 to F1 of the operands of the instructions A to F are sequentially generated and sent to the L stage. In the L stage, the absolute addresses A2 to F2 of the operands of the instructions A to F are sequentially obtained and sent to the P stage. In the P stage, instructions A, C, D, B, E,
The operands A3, C3, D3, B3, E3, and F3 of F are sequentially obtained and sent to the O stage.

At the O stage, instructions A, C, D, B, E,
Operands A3, C3, D3, B3, E3, and F3 of F are processing numbers "0" of instructions A, C, D, B, E, and F, respectively.
"2", "3", "1", "4", and "5" are sequentially buffered in the operand buffer 15 as write addresses. However, when the operands A3 to F3 of the instructions A to F are read from the operand buffer 15, the read addresses "0" to "5" generated by the address register 31 and the counter 32 are in order.

When a new wait factor occurs in a subsequent processing request from the upper stage stored in the instruction register 2, the logical address register 8, and the absolute address register 12, the processing request is issued to the instruction register 2 Is held in the logical address register 8 and the absolute address register 12 until the wait factor is resolved. In this case, the process numbers in the process number registers 21, 26, 29 are also held.

Further, those processing requests are sent to the instruction register 1
And logical address register 7 and absolute address register 11
The processing is performed after waiting for the processing of the preceding processing requests stored in and respectively.

By performing the control as described above, in the embodiment of the present invention, when a waiting factor occurs in each stage of the pipeline, the waiting time can be effectively used.

In this way, the processing numbers "0" to "5" are given to the instructions A to F from the instruction fetch stage of the upper stage by the processing number register 21 and the counter 22, respectively, and the processing given to the instructions A to F is performed. Numbers are carried around in each stage of the pipeline, and when the occurrence of a wait factor for the prefetch processing request of an operand in each stage of pipeline processing is detected, the prefetch processing of the subsequent operand from the upper stage of the stage is detected. Operands A3 to F3 of each instruction A to F fetched and processed in the P stage of the pipeline
Are stored in the operand buffer 15 in correspondence with the processing numbers assigned to the instructions A to F, and the operands A3 to F3 of the respective instructions A to F are processed from the operand buffer 15 by the processing number "0".
By reading in the order of "5", it is possible to effectively use the waiting time when a waiting factor occurs in each stage of the pipeline, and it is possible to greatly improve the performance of the pipeline processing.

[0063]

As described above, according to the present invention, a process number is given to each of the operand prefetching processing requests so as to be carried around to each stage of the pipeline processing and each stage of the pipeline processing. When the occurrence of a wait factor for the prefetch processing request of the operand is detected, the prefetch processing request of the subsequent operand is received from the upper stage of the stage and processed, and the operand fetched by this processing is prefetched for the operand. If the wait factor occurs in each stage of the pipeline, the waiting time can be effectively used by storing the data in association with the process number assigned to the process and reading it in order of the process number. There is an effect that can be greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a processing operation of an embodiment of the present invention.

FIG. 3 is a diagram showing a processing operation of an embodiment of the present invention.

FIG. 4 is a diagram showing a processing operation of an embodiment of the present invention.

[Explanation of symbols]

1, 2 Instruction register 3, 9, 13, 27, 30, 33 Selector 4 Base register 5 Index register 6 Adder 7, 8 Logical address register 10 Absolute address translation buffer 11, 12 Absolute address register 14 Operand cache 15 Operand buffer 16 Detection circuit 21,23,25,26,28,29 Processing number register 22,32 Counter 31 Address register

Claims (3)

[Claims] 1. A preceding control device of an information processing device for prefetching operands by pipeline processing, comprising :
For each prefetch request for the operand sent next
Said means for imparting a continuous process number, the process number assigned to prefetch processing request each provided and said operand to each stage of the pipeline processing opera
Pre-processing request of the command and each step for the processing request.
Means for carrying around the processing result in the pipeline processing, detecting means for detecting the occurrence of a processing wait factor for the prefetch processing request of the operand in each stage of the pipeline processing, and each stage of the pipeline processing. means for the provided and said detecting means for processing receiving a prefetch processing request and the processing result of the subsequent operand from the upper stage of the stage when the occurrence of the waiting factor is detected, picked up by the pipeline processing Storage means for storing the operand in association with the processing number given to the prefetch processing request of the operand, and means for reading the operand from the storage means in the order of the processing number. Advance control device. 2. A first holding means for holding a processing result of a prefetch processing request of the operand in a higher stage of the stage before processing in the stage, and the processing result held in the first holding means. Second holding means for holding the processing result of the prefetch processing request of the operand subsequent to the prefetch processing request of the corresponding operand;
Each stage of the pipeline processing includes selection means for selecting one of the contents held in each of the first and second holding means according to the detection result of the detection means ,
The selection means causes the detection means to generate the waiting factor.
Is held by the second holding means when is detected.
The advance control apparatus according to claim 1 , wherein the volume is selected . 3. A prefetch processing request for each of the operands
First processing number holding that holds the given processing number
Means and subsequent operations from the stage above it.
Keep the processing number given to the land advance processing request.
Second processing number holding means held and detection by the detecting means
It is held in the first processing number holding means according to the result.
The processing number and the processing stored in the second processing number storage means.
Select one of the physical number and send it to the lower stage
A selection means is included in each stage of the pipeline processing.
The selection means causes the detection means to cause the waiting factor.
Second processing number holding means when the occurrence of
The advance control device according to claim 1 or 2 , wherein the process number held in (3) is selected .