JPH0821010B2 - Adapter control method - Google Patents

Description

DETAILED DESCRIPTION [Overview] The present invention relates to an adapter control method for controlling an adapter in which a plurality of CPUs are connected via a common bus, and control information of an adapter function for each CPU connected to the adapter via a common bus. Each CPU individually resets the control information of this adapter function or resets the corresponding control information in response to the reset of the control bus, and notifies the relevant CPU of that fact, and each CPU mutually communicates. For the purpose of enabling the adapter function and control bus to be reset without awareness, multiple CPUs connected to the adapter via a common bus
Interface registers provided in association with each of the CPUs, a control area for storing control information of adapter functions corresponding to a plurality of CPUs, and a control circuit, and a CPU has set an adapter function reset instruction in the interface registers. In response to the above, the control information and the control circuit of the corresponding adapter function in the control area are cleared by an interrupt. Further, in response to a certain CPU setting a reset instruction of a predetermined file control bus i in the interface register, the file control bus i instructed by the interrupt is reset and the control information in the related control area is reset. After clearing, the CPU corresponding to the cleared control information is notified of this.

[Industrial applications]

The present invention relates to an adapter control system that controls an adapter to which a plurality of CPUs are connected via a common bus.

[Problems to be Solved by Conventional Techniques and Inventions]

In recent years, with the demand for faster computer systems,
Control using the CPU is performed. Therefore, even if there are multiple CPUs, it is necessary to be able to run the software independently without being aware of the other CPUs.

Conventionally, when resetting a file control adapter connected from multiple CPUs via a common bus, the issuing CPU had to confirm that the other CPUs were not in the process of accessing. For this reason, there has been a problem that exclusive control must be performed between the CPUs, which is complicated and mutually aware.

The present invention is a CP connected to an adapter via a common bus.
Each U has adapter function control information, and each CPU individually resets the control information of this adapter function or resets the corresponding control information in response to the reset of the control bus, and informs the corresponding CPU to that effect. The purpose is to notify each CPU so that each CPU can reset the adapter function and control bus without being aware of each other.

[Means for solving the problem]

 Means for solving the problems will be described with reference to FIG.

In FIG. 1, CPU (0) 0 and CPU (1) 1 are connected to the adapter 2 via a common bus and perform various controls / processes.

The adapter 2 controls access to the disk devices connected via the file control buses 0, 1 and the like.

The interface registers 3-0 and 3-1 are individually provided in association with CPU (0) 0 and CPU (1) 1 connected to the common bus. It is an interface for setting a command to this and notifying the MPU 9 by an interrupt or the like to request a predetermined processing, or receiving a notification of the result.

The adapter function reset flags 4-1 and 5-1 indicate the CPU
(0) 0 and the CPU (1) 1 give control information reset instructions.

File control bus reset status 4-2, 5-2
Is for notifying the relevant CPU of this when the file control bus is reset.

The control area 7-1 is an area for storing control information of the adapter function.

[Action]

The present invention, as shown in FIG.
By setting the adapter function reset flag 4-1 of the corresponding interface register 3-0.
Notify MPU9 by (non-maskable interrupt). Upon receiving this notification, the MPU 9 sets the control information of "file control bus 0 system, CPU0 system" in the control area 7-1 corresponding to the set adapter function reset flag 4-1 to "0".
clear.

Further, for example, the CPU (0) 0 sets the reset command of the file control bus 0 in the corresponding interface register 3-0 to notify the MPU 9 by NMI. Upon receiving this notification, the MPU 9 resets the corresponding file control bus 0 and sets the control information corresponding to this file control bus 0 in the control area 7-1 to "0".
After clearing, the other corresponding to this cleared control information
File control bus reset status 5-2 in the interface register 3-1 for the CPU, eg, CPU (1) 1,
Set. As a result, this is notified to the CPU (1) 1 by INT (interrupt).

Therefore, the CP connected to the adapter 2 via the common bus
Control area 7 for storing control information of adapter function for each U
By preparing 1, each CPU can easily reset the control information individually. In addition, by resetting the corresponding control information in response to resetting the file control bus and notifying the other CPUs to that effect, each CPU resets the file control bus without being aware of each other. It becomes possible.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be sequentially described in detail with reference to FIGS. 1 to 3.

In FIG. 1, CPU (0) 0 and CPU (1) 1 are adapters (file control adapter, etc.) 2 via a common bus.
And performs various controls and processings.

The adapter 2 is, for example, a file control adapter that controls access to an input / output device such as a disk device.
In this adapter 2, multiple CPU (0) 0, CPU (1)
Interface registers used individually by 1 etc. 3-
0, 3-1 and the control area 7-1, ROM6, MPU9, bus control unit 11, AND circuit 12 which are commonly used.
Etc. Here, by commonly using ROM6, MPU9, etc., the amount of hardware is reduced,
The cost can be reduced.

The interface registers 3-0 and 3-1 are provided individually for the CPU (0) 0, the CPU (1) 1 and the like connected to the common bus. This interface register 3
-Set the command to 0, 3-1 and set MPU9 by NMI.
To request processing, or CPU (0) 0, CPU (1)
1 receives the result by interruption. The adapter function reset flags 4-1 and 5-1 are
It is for resetting the adapter function. The file control bus reset statuses 4-2 and 5-2 are for notifying the corresponding CPU of this because the control information of the adapter function is also cleared to "0" when the file control bus is reset.

The ROM 6 is a read-only memory that stores control programs and the like.

The RAM 7 is a readable / writable memory and stores the program read from the ROM 6 and the control information of the adapter function according to the present embodiment.

The control area 7-1 is an area for storing control information of the adapter function. In the control area 7-1, control information is separately stored for each CPU and file control bus connected to the common bus, as shown in the figure. For example, control information (file control bus 0 system, CPU0 system)
(0) 0 means the control information necessary for accessing the disk device via the file control bus 0.

The MPU 9 performs various controls / processes, and is notified by the NMI in response to the command being set in the interface registers 3-0 and 3-1. According to the contents of, the corresponding control / processing is performed.

The controllers 10-1 and 10-2 are for controlling access to the disk device.

The bus control unit 11 controls a file control bus (control bus) that connects the adapter 2 and the disk device.

The AND circuit 12 generates all reset signals when reset signals are sent from all CPU systems to the adapter 2. When this all reset signal is generated, all the circuits (control area 7-
(Including 1) is cleared by hardware.

Next, the operation when the CPU (0) 0 issues a reset command for resetting the control information will be described with reference to FIG.

In FIG. 2, the adapter function reset flag (CPU0 system, file control bus 0 system) is set. This means that CPU (0) 0 in FIG. 1 designates "CPU0 system, file control bus 0 system" and sets the adapter function reset flag 4-1 in the interface register 3-0.

Is notified to the MPU 9 by the NMI for the set of, and the corresponding control area 7-1 is cleared to “0”. As a result, the control information (file control bus 0 system, CPU0 system) in the control area 7-1 of FIG. 1 is cleared to "0" and reset.

 Notifies the end of CPU (0) 0.

Through the above processing, the CPU can easily individually reset the control information necessary for access control of the disk device via the file control bus. still,
The adapter 2 prepares the interface register 3 and the control area 7-1 for each CPU as described above.
File control bus 0 from (0) 0 and CPU (1) 1
Access to the disk devices connected to the disk can be processed simultaneously. CPU (0) 0 and CPU (1) 1 operate with independent software, and if the software on the CPU (0) 0 side detects any abnormality, the CPU
Initialize only (0) 0 and its subordinate adapters (CPU0 system control area 7-1, control circuit 13) so that the software operation on the CPU (1) 1 side and the subordinate adapters are not affected. In addition, the adapter function makes it possible to configure a multiple CPU system. The state where the CPU0 system and the file control bus 0 are reset and the CPU1 system and the file control bus 0 are not reset is necessary in the above case.

Next, the reset process of the file control bus will be described in detail with reference to FIG.

In FIG. 3, CPU (0) 0 gives an instruction to reset the file control bus 00 (CPU0 system, file control bus 0 system). This is because the CPU (0) 0 shown in Fig. 1 sends "file control bus 0 system" to the interface register 3-0.
It means to set to reset.

Is notified to the MPU 9 by the NMI and resets the file control bus 0 system in correspondence with the set of.

Clears "0" in the control area (file control bus 0 system, CPU0 system). This corresponds to the resetting of the file control bus 0 system, and stores the control information relating to this file control bus 0 system in the illustrated control information (file control bus 0 system in the control area 7-1 in FIG. 1). , CPU0 system area and control information (file control bus 0 system, CPU1 system) area are cleared to "0".

Sets the file control bus reset status 5-2 of the CPU1 system which is the other system CPU of the file control bus 0 system.

Uses INT to notify the CPU1 system (CPU (1) 1) that the control information (file control bus 0 system, CPU1 system) area has been cleared to "0".

By the above processing, the file control bus is reset and the control information related to the reset file control bus is cleared to "0" and "0" in response to the CPU instructing to reset the file control bus. "It becomes possible to notify other related CPUs that they have been cleared.

〔The invention's effect〕

As described above, according to the present invention, each CPU connected to the adapter via the common bus has the control information of the adapter function and the corresponding control corresponding to the reset of the instructed file control bus. Since it adopts a configuration that resets the information and notifies the other CPUs to that effect, each CPU connected to the common bus can easily reset the control information individually. Can reset the file control bus without being aware of each other.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a reset command processing explanatory diagram, and FIG. 3 is a file control bus reset processing explanatory diagram. In the figure, 0, 1 is a CPU, 2 is an adapter, 3, 3-0, 3-
1 is an interface register, 4-1, 5-1 is an adapter function reset flag, 4-2, 5-2 is a file control bus reset status, 7 is a RAM, 7-1 is a control area for storing control information, and 9 is MPUs 10-1 and 10-2 are controllers, 11 is a bus control unit, and 12 is an AND circuit.

Claims (2)

[Claims] 1. In an adapter control system for controlling an adapter to which a plurality of CPUs are connected via a common bus, an adapter (2) is associated with a plurality of CPUs connected via a common bus, respectively. It is provided with an interface register (3) provided and a control area (7-1) for storing control information of the adapter function corresponding to a plurality of CPUs, and a CPU sends an instruction to reset the adapter function to the interface register (3). An adapter control system characterized in that, in response to the setting, the control information of the corresponding adapter function in the control area (7-1) is cleared by an interrupt. 2. In an adapter control system for controlling an adapter to which a plurality of CPUs are connected via a common bus, each adapter (2) is associated with a plurality of CPUs connected via the common bus. A control area for storing the interface register (3) provided, a plurality of file control buses under the adapter (2), and adapter function control information corresponding to each combination of a plurality of CPUs and a plurality of file control buses. (7-1), which corresponds to a certain CPU setting a reset instruction of a predetermined file control bus i (i is a predetermined one of 1, 2, ...) In the interface register (3). Then, after resetting the file control bus i designated by the interrupt and clearing the related control information in the control area (7-1), the cleared control information Corresponding to
An adapter control method characterized by being configured to notify the CPU of this fact.