JPH0821200B2 - Digital recording / playback device - Google Patents

Description

The present invention relates to a digital recording / reproducing apparatus suitable for use in, for example, a dictation type.

[Conventional technology]

When the dictation type is used, a type document may be dictated and recorded on a recording medium using a microphone, and then a typist may reproduce the recording medium and perform typing while listening to the reproduced sound. A recording / reproducing device suitable for use in such a dictation type has been developed, and a fixed memory has been widely used as a recording medium in recent years. Therefore, in the recording / reproducing apparatus, the input audio signal is converted into a digital signal at the time of recording and recorded in the memory.

[Problems to be solved by the invention]

In a recording / reproducing apparatus suitable for use in the above-mentioned dictation type, when a dictation recording is performed and an audio signal is interrupted and becomes a silent period, this silent period is recorded as zero data in the memory for the length of the silent period. . In the case of dictation recording, this silent period frequently appears, which deteriorates the utilization rate of the memory capacity.

As a countermeasure for this, it is possible to detect the silent period during recording and record only the sound period excluding this silent period.However, in this case, the sound period continues for a long time without interruption during playback, so the typist Typing will not catch up. Therefore, when doing the dictation type,
At the time of reproduction, it is desirable that there is a silent period similar to that at the time of recording.

[Means for solving problems]

In the present invention, the marking data indicating the silent period and the data corresponding to the voiced period are sequentially recorded at the time of recording, and control is performed so that a predetermined number of data in the reproduction signal is not used from the reproduction start at the reproduction start time. And means are provided.

[Action]

Since the marking data is recorded on the recording medium such as the fixed memory for a time shorter than the actual silent period, it is possible to increase the utilization rate of the recording capacity of the recording medium and prevent malfunction during reproduction.

〔Example〕

An embodiment in which the present invention is applied to a suitable digital recording / reproducing apparatus using the dictation type described above will be described with reference to the drawings.

 First, the outline of this embodiment will be described with reference to FIG.

In this embodiment, during recording, a voiced period and a silent period are detected from the input audio signal S ₁ shown in FIG. 3A as shown in FIG. 3B. That is, the audio signal is converted into a 1-bit pulse train synchronized with a predetermined clock by the ADM modulator (adaptive delta modulator). This ADM modulator outputs a pulse train of 0 ... 0 in a silent period, outputs a pulse train in which 0 and 1 are arbitrarily arranged in a voiced period, and converts it as 1-bit audio data shown in FIG. . Also 00
The pulse train of 000001 is used as a code for resetting to zero volt after demodulation. Therefore, after the silent period is detected, an 8-bit silent start code consisting of a hexadecimal "01" code indicating the silent period is generated as a marking code as shown in FIG. T ₁ ,
An 8-bit silent time code TM ₁ , TM ₂ , TM ₃ ……… (hereafter represented by TM _N ) indicating T ₂ , T ₃ ……… (hereafter represented by T _N ) is generated as shown in FIG. After that, 1-bit pulse train audio data is divided into 8 bits and arranged. The silence start code “01” and the silence time code TM _{N of} FIG. 10C thus obtained are transferred to a data memory in a system controller using a microcomputer described later based on a data request signal. . The audio data is sequentially cyclically written in 8 bits at each address of the buffer memory having 256 addresses, and then the audio data is read and transferred to the data memory.

According to the above, since only the 8-bit silence start code “01” and the silence time code TM _N, which are shorter than the actual length T _N for the silence period, are recorded in the data memory, the buffer memory is used. As a result, the recorded contents of the data memory can be effectively used.

In this embodiment, the silent time code TM _N uses an 8-bit counter so that a value indicating a maximum of 4 seconds can be written. Further, it has been confirmed that the silent start code "01" is a code which is statistically extremely rarely generated in voice data. In the present embodiment, this code "01" is used as a silent start code. ing. Therefore, if there is a code of "01" in the audio data, this will be erroneously detected as a silence start code during reproduction, and this will cause a malfunction. Therefore, "01" is selected from the ADM-modulated voice data.
It detects the code, converts it to the "02" code, and then writes it to the buffer memory. As described above, it has been confirmed that the sound quality is not substantially affected even if the “01” code in the audio data is converted to the “02” code. still,
The “01” and “02” codes are 2-digit hexadecimal data written in the buffer memory in units of 8 bits, that is, the upper 4 bits represent “0” and the lower 4 bits represent “1” or “2”. Means code.

Next, during playback, the data read from the data memory
The silent start code "01" and the silent time code TM _N are detected from D ₁ , and based on the detection, only the audio data is sequentially and cyclically written in the buffer memory and the silent time code is also written.
Pseudo audio data is generated in a period according to the value indicated by TM _N. Read audio data from the buffer memory sequentially and add ADM
Supply it to the demodulator, and in the middle of it, the silence start code "01"
Based on the detection, the pseudo silent data is inserted and supplied to the ADM demodulator.

According to the above, since a pseudo silent period is inserted during reproduction in the same period as during dictation recording, typing becomes easier.

Further, in the present embodiment, the length of the silent period inserted by the pseudo silent data can be changed by a multiple when reproducing. That is, the actual length of the silent period at the time of dictation recording is freely expanded or contracted by a multiple at the time of reproduction, and fast listening or slow listening is performed, so that typing can be further facilitated.

The data written in the data memory are written in the order shown in FIG. 3C, but at the start of reproduction, the silent time code TM _N happens to be the silent start code “0”.
If it is the same as `` 1 '', change this to the silence start code `` 0
There is a case where it is erroneously detected as "1", and further the following 8-bit voice data is erroneously detected as the silence time code TM _N. In that case, there is a case where a silent period is suddenly set at the same time when the reproduction is started, and the pseudo-inserted silent period is completely different from the actual length. As a countermeasure against this, in the present embodiment, the code of "01" and the next 8-bit code detected from the first 256 pieces of data (data for one sequence of the buffer memory) read from the data memory during reproduction. Is ignored and is not written in the buffer memory.

As described above, the buffer memory is used during recording and reproduction. In the early stage of recording, data may not be stable due to unstable ADM modulation or click noise of switches. In addition, if the buffer memory does not transfer to the data memory in order from the first data after waiting for 256 data to be sent from the beginning at the start of recording, meaningless data will be transferred before that. Become. Also at the start of playback, if you wait until 256 pieces of data transferred from the data memory are accumulated and then transfer to the ADM demodulator in order from the first data, the meaningless data before that will be transferred. Become.

In order to solve these problems relating to the buffer memory, in this embodiment, the first 256 pieces of data sent to the buffer memory at the start of recording are all discarded so as not to be written in the data memory.

FIG. 2 shows an outline of a circuit for performing the above-mentioned recording and reproducing operations.

In FIG. 2, the third input terminal 1 is used for dictation recording.
The analog audio signal S ₁ of FIG. A is input. This signal S
₁ is supplied to the ADM modulator 2 to be converted into, for example, a 1-bit string digital signal D ₀ , and is also supplied to the silence detecting circuit 3 to detect a silent period as shown in FIG. 3B.

When the silence period is not detected by the silence detection circuit 3, the encoder 4 outputs the signal D ₀ of the 1-bit string during the voice period to 8
It is divided into bits and sequentially converted into 8-bit width parallel audio data, which is converted into "02" only when the parallel audio data is "01" in hexadecimal. When there is a change from a voice to a silence state, the silence start code "01" and the silence time code TM _N (maximum 4 seconds) according to the length T _N of the silence period are used by the microcomputer. The parallel audio data which is transferred to the data memory 7 provided in the system controller (hereinafter referred to as “syscon”) 6 and which can include the above “01” → “02” conversion is stored in the buffer memory 5 having 256 addresses at each address. On the other hand, 8 bits are written cyclically. The buffer memory 5 sequentially reads from the first address while writing the next data when the second 256 pieces of data are accumulated, and transfers the read data to the data memory 7 provided in the syscon 6.
Therefore, data D ₁ shown in FIG. 3 C in the data memory 7 is stored.

At the time of reproduction, the data read from the data memory 7 is circularly written in the buffer memory 5. In the buffer memory 5, when the first 256 pieces of data are accumulated, the next data is written while the data is sequentially read from the first address, and the read data is supplied to the decoder 8.

The decoder 8 detects the silence start code “01” and the silence time code TM _N from the data D ₁ , generates a pseudo silence code according to this detection, and inserts this pseudo silence code into the corresponding portion of the data. And supplies it to the ADM demodulator 9 as data D ₂ together with the voice data. The length of this pseudo silence code can be changed by the operation of the user.

In the ADM demodulator 9, the data D ₂ is converted into an analog voice signal, and this voice signal is passed through the amplifier 10 to the speaker.
Supplied to 11.

FIG. 1 shows a specific configuration of the circuit shown in FIG.
In particular, the concrete configurations of the encoder 4 and the decoder 8 surrounded by dotted lines are shown. Also, the input terminal 1 in FIG.
The ADM demodulation 2, the silence detection circuit 3, the buffer memory 5, the system controller 6, the data memory 7, the ADM demodulator 9 and the like are designated by the same reference numerals.

In FIG. 1, an operation unit 12 composed of a keyboard is connected to the syscon 6, and the operation unit 12 is operated by a user to select various operation modes such as recording, reproduction, and expansion / contraction of a silent period. It Also, all the various signals from the system controller 6, the encoder 4 and the decoder 8 are input / output circuits 13
Have been given and received through.

At the time of recording, the encoder 4 is operated and the ADM modulator 2 outputs the input audio signal S ₁ to the clock CL from the clock 8 generator 14.
Based on K ₁ , it is converted into a signal D ₀ consisting of 1-bit string serial data and supplied to the serial-parallel conversion shift register 15. The shift register 15 sequentially converts the 8-bit serial data of the signal D ₀ into parallel data having an 8-bit width based on the clock CLK ₁ and then converts the data into “01” → “02” conversion circuits 16 and “0”.
1 "detection circuit 17 and supply. The "01" detection circuit 17 detects the "01" code from the parallel data, and based on this detection, the "01" → "02" conversion circuit 16 detects "01" in the parallel data.
Convert code to "02" code. That is, the “01” detection circuit 17 includes an 8-input NOR circuit having seven inputs connected to the output bus of the upper 7 bits of the shift register 15,
The remaining one input terminal is connected to the output bus of the least significant bit of the shift register 15 via the inverter. Therefore, 8
The input NOR circuit outputs H when it detects a binary number 00000001 on the output bus. This H is "01" → "0
2 "Convert the lower 2 bits of the conversion circuit 16 output bus to binary 10
It is used as a signal to switch to. Therefore, this "0
In the 1 ”→“ 02 ”conversion circuit 16, the shift register 15
The upper 6-bit output bus of the buffer memory 5 is directly connected to the upper 6-bit data bus of the buffer memory 5, and the remaining lower 2-bit output bus is connected to the lower 2 of the buffer memory 5 via two switching circuits. Connected to the bit data bus. Of course, the "01" detection circuit 17 connects two TTL circuits such as 7485 in a cascade, and sets the comparison value to the binary number 00000001.
May be preset and compared. Also clock generator 18
Generates a clock CLK ₂ obtained by dividing the clock CLK ₁ into 1/8 and supplies the clock CLK ₂ to a control circuit 19 for controlling the buffer memory 5. The clocks CLK ₁ and CLK ₂ are also supplied to other circuits.

On the other hand, when the silence period is detected by the silence detection circuit 3, the encode data request generation circuit 20 is operated, and the 8-bit silence timer 21, for example, measures the time from the silence start time to the silence end time. The encoded data data request generation circuit 20 sends the data request signal RQ ₁ to the syscon 6 via the input / output circuit 13 and the timing signal ST ₁ to the switching signal generation circuit 22 in response to the detection of the silent period. The content of the signal RQ ₁ includes the transfer request of voice data from the buffer memory 5 to the data memory 7 in the sound period, and the code generation circuit 23 to the data memory 7 from the silent period to the sound period. The request is for the silent start code “01” and the silent time code TM _N , and the transfer is not required during the silent period.

When the silent period changes to the voice period, the switching signal generating circuit 22 outputs the silent start code “0” based on the signal ST _1.
A switching signal ST ₂ for switching between 1 ”and the silent time code TM _N is generated and supplied to the code generation circuit 23. Code generator 23
Generates a silence start code “01” and a silence time code TM _N on the basis of the signal ST ₂ and the timer value T _{N of the} silence period given from the silence timer 21. 7 and send the control signal to the control circuit
Send to 19. At this time, the silent time code TM _N is made up of a value indicating a maximum of 4 seconds.

In the buffer memory 5, the write timing and the address are controlled by the control circuit 19, and the audio data that can be converted into “01” → “02” is cyclically written. In this case, the start-up delay circuit is instructed by the system controller 6.
By operating 24 and controlling the control circuit 19,
The data is controlled so as not to be transferred from the buffer memory 5 to the data memory 7 until the buffer memory 5 stores the second 256 pieces of data.

When 256 pieces of data are accumulated in the buffer memory 5, the addresses are sequentially advanced from the first address and read out,
The read data is transferred to the data memory 7 in response to the request signal RQ ₁ . At this time, new data is cyclically written in the read addresses sequentially and sequentially read. With the above, the operation at the time of recording is completed.

Next, at the time of reproduction, the decoder 8 is operated and the data memory 7 is read, and the audio data in the read data D ₁ is stored in the buffer memory 5 via the input / output circuit 13 in the same manner as at the time of recording. It is written cyclically. At this time, the control circuit 19 is controlled by the startup delay circuit 24, and the data D ₂ is not transferred to the ADM demodulator 9 during the writing of the first 256 data. Of course, the above operation is executed by software by the system controller 6 and related programs. This discards the initial unstable data. Further, the "01" ignore signal generation circuit 26 sends a "01" ignore signal to the control circuit 19 so that the "01" detect circuit 25 does not detect "01" in the first 256 pieces of data. As a result, as described above, the playback start time is the silence time code.
When it is TM _N and the code content happens to be "01", the silent time code TM _N is prevented from being erroneously detected as the silent start code "01".

When the first 256 pieces of data are written in the buffer memory 5, they are sequentially written from the first address. The data is sequentially read from the read address and is sequentially written from the read address. The read data is converted into serial data D ₂ by the shift register 34, and the ADM demodulator 9
Is supplied to.

On the other hand, the “01” detection circuit 25 causes the silence start code “0
When the "1" is detected, the decode data request generation circuit 27 stops outputting the data request signal RQ ₂ , and the timer value detection circuit 28 detects the silence time code TM _N next to the silence start code "01". The length of the silent period, that is, the timer value measured by the silent timer 21 during recording.
Load T _N into silence time control circuit 29.

The silent time control circuit 29 controls the loaded timer value T _N according to the operation of the user, and changes the length of the silent period that is artificially inserted. This silence time control circuit 29, for example, a first counter to which the timer value T _N is loaded,
The second counter is loaded with the multiplication factor of the silent period. The first counter uses the clock CLK ₂
The clock divided by 1/32 is counted down from the value loaded above and the timer value T _N
Is loaded and the second counter is decremented, and when the second counter underflows, a signal is sent to the decode data request generation circuit 27 as the end of the pseudo silence period. Therefore, the second
If you set the magnification to be loaded to the counter of "8",
The pseudo silent period is reproduced by CLK ₁ ÷ 32 ÷ 8, which is one time the silent period at the time of recording. When the magnification is set to "0" to "7", the pseudo silent period becomes shorter than the silent period at the time of recording, and a fast listening state is set.

The pseudo silence data generation circuit 30 generates the pseudo silence data D ₃ according to the pseudo silence period controlled by the silence time control circuit 29. This data D ₃ is converted to serial data by the parallel-to-serial conversion shift register 34 and then inserted into the data D ₂ to add ADM.
It is supplied to the demodulator 9. When this pseudo silence period ends, the decode data request generation circuit 27 outputs the request signal RQ ₂ again.

According to the above, the ADM demodulator 9 can obtain the voice signal in which the pseudo silence period having the length controlled by the silence period control circuit 29 is inserted into the original voice signal.

In the figure, 31 is a timing signal generating circuit for writing the data D ₁ once latched in the input / output circuit 13 from the data memory 7 into the buffer memory 5, and 32 is an encode mode from the syscon 6, a decode mode, etc. 3 is a mode setting circuit including a register for storing the mode setting information of FIG.
Also, 33 indicates the mode set by the mode setting circuit 32.
It is an ADM control circuit that controls the ADM operation.

According to the embodiment described above, the following effects can be obtained.

(1) The data amount is reduced by, for example, 30% or more as compared with the case where the silent start code “01” and the silent time code TM _N are recorded without recording the actual silent period at the time of recording, and the buffer memory 7 is used. The rate can be increased.

(2) Since the silent start code "01" is the "01" code that is extremely rare in the audio data,
The silence start code “01” can be arranged at an arbitrary position in the data D ₁ without affecting the sound quality. still,
Codes such as "02" and "03" other than "01" have a low frequency of occurrence, and thus can be used as silence start codes.

(3) Since the maximum detection time of the silent period is set to, for example, 4 seconds, the efficiency in performing the dictation type is improved.

(4) Since the length of the pseudo silent period that reproduces the silent period is variable, it can be played back at a speed that matches the ability of the typist, and it may be possible to speed up the confirmation work after typing. it can.

(5) Since the voiced period is recorded as it is, the sound quality is not deteriorated.

(6) Since the buffer memory 5 is used, it is possible to prevent the head from being cut off at the start of voiced sound.

(7) Since the first 256 pieces of data transferred to the data memory 7 are discarded at the start of recording, unstable data can be removed to prevent malfunction.

(8) Since the silent start code “01” in the first 256 pieces of data transferred to the buffer memory 5 is ignored at the time of starting reproduction, malfunction can be prevented.

Next, an embodiment of the silence detecting circuit will be described with reference to FIGS. 5a to 5e show the output waveforms a to e of FIG.

A conventional silence detection circuit compares an input voice signal with a certain detection level, and when the voice signal is below the detection level is a silent period, and when the voice signal exceeds the detection level is a voiced period. Therefore, when the ambient noise is large, the noise level may exceed the detection level and may be erroneously detected as a voiced period even when the user is not speaking. The silence detection circuit 3 according to the present embodiment changes the detection level according to the ambient noise.

In FIG. 4, the input audio signal S ₁ input to the input terminal 35 (point a) is supplied to the amplifier 36, amplified to a level necessary for rectification described later, and then supplied to the band-pass filter 37. Band (for example, 300 to 3.4 kHz) is extracted. This audio signal is detected by the rectification detection circuit 38, and the detection output is smoothed by the smoothing circuit 39. This smoothing circuit 39 is composed of a switch 40 controlled by a switching signal SW described later, resistors R ₁ and R _{2, a} capacitor C _{1 and the} like. As will be described later, when the switch 40 is on in the noise state (silence state), the time constant T ₁ becomes T ₁ = R ₂ C ₁ , and when the switch 40 is off in the sound state, the time constant T _{2 is} Is T ₂ = (R ₁ + R ₂ ) C ₁ ＞ T ₁
It is designed to be.

The DC signal smoothed by the smoothing circuit 39 is taken out to the point b, then amplified by the DC amplifier 41, and then added to one input terminal of the comparison circuit 42 as a voice determination level. The voice signal extracted by the bandpass filter 37 is applied to the other input terminal of the comparison circuit 42, and is compared with the voiced judgment level.

The comparison circuit 42 outputs an "L" level signal when the voice signal exceeds the voice determination level, and outputs an "H" level signal when the voice signal is equal to or lower than the voice determination level. .

This "L" or "H" level signal controls the switch 40 as a switching signal SW. When it is "L" level, the switch 40 is turned off, and when it is "H" level, the switch 40 is turned on. That is, when the level of the voice signal is higher than the voice determination level and the voice is present, the switch 40 is turned off and the time constant of the smoothing circuit 39 is increased to T ₂ (> T ₁ ). This prevents the voice determination level from rapidly increasing due to the voice portion.

In the voiced state, the output of the comparison circuit 42 is "L".
Level, the resistor R _3, to discharge quickly through the capacitor C ₂ is diode 44 of a time constant circuit constituted 43 at capacitor C _2. The capacitor C ₂ when the output is "H" level of the comparison circuit 42 charges slower. As for the voltage of the capacitor C _2, a predetermined voltage V ₁ is applied to _one input terminal of the comparison circuit 45 from the DC bias voltage voicing circuit 46. Therefore,
From the comparison circuit 45, the silence detection signal S ₂ can be obtained at the output terminal 47 (point e). The voltage V ₁ is also supplied to other predetermined circuits as a bias voltage.

According to the above, it is possible to automatically follow the voiced judgment level in accordance with the steady noise or the slow fluctuation of the ambient noise.

〔The invention's effect〕

According to the present invention, the actual silence period is not recorded at the time of recording, and the marking such as the silence start code and the silence time code is recorded. Therefore, the amount of data is reduced as compared with the case of recording the actual silence period. Therefore, the utilization rate of the recording capacity of the recording medium can be increased. Further, at the start of reproduction, the marking code in the first 256 data of the reproduction signal is ignored, so that an erroneous operation can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic block diagram of FIG. 1, and FIG. 3 is a timing for explaining the present invention in principle. FIG. 4 is a circuit diagram showing an embodiment of the silence detecting circuit, and FIG. 5 is a timing chart for explaining the operation of FIG. In the symbols used in the drawings, 3 ... silence detection circuit 6 ... system controller 7 ... data memory 19 ... control circuit 23 ... code generation circuit 25 ... "01" detection circuit 26 ... "01" Ignore signal generation circuit 30: This is a pseudo silence data generation circuit.

Claims (1)

[Claims] 1. A detection means for detecting a no-signal period from an input signal during recording, a period excluding the no-signal period of the input signal and a signal indicating the no-signal period based on the detection of the no-signal period. A recording medium for recording, a detecting means for detecting a signal indicating the no-signal period from a reproduction signal reproduced from the recording medium at the time of reproduction, and a pseudo no-signal is generated based on the detection of the no-signal period. In a digital recording / reproducing apparatus provided with a pseudo no-signal generating means for inserting a no-signal into the reproduced signal, a control means for controlling not to use a predetermined number of data in the reproduced signal from the reproduction start at the reproduction start time. A digital recording / reproducing apparatus characterized by being provided with.