JPH0821201B2 - Digital recording / playback device - Google Patents

Description

The present invention relates to a digital recording / reproducing apparatus suitable for use in, for example, a dictation type.

[Conventional technology]

When the dictation type is used, a type document may be dictated and recorded on a recording medium using a microphone, and then a typist may reproduce the recording medium and perform typing while listening to the reproduced sound. A recording / reproducing device suitable for use in such a dictation type has been developed, and a fixed memory has been widely used as a recording medium in recent years. Therefore, in the recording / reproducing apparatus, the input audio signal is converted into a digital signal at the time of recording and recorded in the memory.

[Problems to be solved by the invention]

In a recording / reproducing apparatus suitable for use in the above-mentioned dictation type, when a dictation recording is performed and an audio signal is interrupted and becomes a silent period, this silent period is recorded as zero data in the memory for the length of the silent period. . In the case of dictation recording, this silent period frequently appears, which deteriorates the utilization rate of the memory capacity.

As a countermeasure for this, it is possible to detect the silent period during recording and record only the sound period excluding this silent period.However, in this case, the sound period continues for a long time without interruption during playback, so the typist Typing will not catch up. Therefore, when doing the dictation type,
At the time of reproduction, it is desirable that there is a silent period similar to that at the time of recording.

[Means for solving problems]

In the present invention, the marking data indicating the silent period and the data corresponding to the sound period are recorded on the second recording medium via the first recording medium during the recording, and the second data is recorded during the reproduction.
A signal for a predetermined period from the beginning of the reproduced signal of the recording medium is not used, and means for inserting pseudo silent data based on the detection of the marking data from the reproduced signal is provided.

[Action]

Since the second recording medium such as the fixed memory records the marking data in a shorter time than the actual silent period, the utilization rate of the recording capacity of the recording medium can be increased as compared with the conventional one and the malfunction at the time of reproduction can be prevented. To be done.

〔Example〕

An embodiment in which the present invention is applied to a suitable digital recording / reproducing apparatus using the dictation type described above will be described with reference to the drawings.

 First, the outline of this embodiment will be described with reference to FIG.

In this embodiment, during recording, a voiced period and a silent period are detected from the input audio signal S ₁ shown in FIG. 3A as shown in FIG. 3B. That is, the audio signal is converted into a 1-bit pulse train tuned to a predetermined clock by an ADM modulator (adaptive delta modulator). This ADM modulator outputs a pulse train of 0 ... 0 in the silent period, and outputs a pulse train in which 0 and 1 are arbitrarily arranged in the voiced period to output C.
Is converted into 1-bit audio data shown in. The pulse train of 00000001 is used as a code for resetting to zero volt after demodulation. Therefore, after the silent period is detected, an 8-bit silent start code consisting of a hexadecimal "01" code indicating the silent period is generated as a marking code as shown in FIG. T ₁ , T ₂ , T ₃・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (hereinafter referred to as T _N )
8-bit silence time code TM ₁ , TM ₂ , TM ₃ ...
........ (hereinafter referred to as TM _N ) is generated as shown in C of FIG.
It is divided into bits and arranged. The silence start code “01” and the silence time code TM _{N of} FIG. 10C thus obtained are transferred to a data memory in a system controller using a microcomputer described later based on a data request signal. . The audio data is sequentially cyclically written in 8 bits at each address of the buffer memory having 256 addresses, and then the audio data is read and transferred to the data memory.

According to the above, since only the 8-bit silence start code “01” and the silence period code TM _N, which are shorter than the actual length T _{N for the} silence period, are recorded in the data memory, the buffer memory is used. As a result, the recorded contents of the data memory can be effectively used.

In this embodiment, an 8-bit counter is used so that the silent time code TM _N can be written with a value indicating a maximum of 4 seconds. Further, it has been confirmed that the silent start code "01" is a code which is statistically extremely rarely generated in voice data. In the present embodiment, this code "01" is used as a silent start code. ing. For this reason, if there is a code of "01" in the audio data, this will be erroneously detected as a silence start code at the time of reproduction, causing a malfunction.
For this reason, the "01" code is detected from the ADM-modulated audio data, converted into the "02" code, and then written in the buffer memory. As described above, it has been confirmed that the sound quality is not substantially affected even if the “01” code in the audio data is converted to the “02” code. In addition, "0
"1" and "02" codes are 2-digit hexadecimal data written in the buffer memory in units of 8 bits, that is, the upper 4 bits represent "0" and the lower 4 bits represent "1" or "2". Means

Next, during playback, the data read from the data memory
The silent start code "01" and the silent time code TM _N are detected from D ₁ , and based on the detection, only the audio data is sequentially and cyclically written in the buffer memory and the silent time code is also written.
Pseudo audio data is generated in a period according to the value indicated by TM _N. Read audio data from the buffer memory sequentially and add ADM
Supply it to the demodulator, and in the middle of it, the silence start code "01"
Based on the detection of, the pseudo silence data is inserted and supplied to the ADM demodulator.

According to the above, since the pseudo silent period is inserted in the same period as in dictation recording during reproduction, typing is facilitated.

Further, in this embodiment, the length of the silent period inserted by the pseudo silent data can be changed at the time of reproduction. That is, the actual length of the silent period at the time of dictation recording can be freely expanded or contracted at the time of reproduction to perform fast listening or slow listening, so that typing can be further facilitated.

Although each data written in the data memory is written in the order shown in FIG. 3C, when the reproduction is started, the silent period code TM _N happens to be the silent start code “0”.
If it is the same as `` 1 '', change this to the silence start code `` 0
There is a case where it is erroneously detected as "1", and further the following 8-bit voice data is erroneously detected as the silence time code TM _N. In that case, there is a case where a silent period is suddenly set at the same time when the reproduction is started, and the pseudo-inserted silent period is completely different from the actual length. As a countermeasure against this, in the present embodiment, the code of "01" and the next 8-bit code detected from the first 256 pieces of data (data for one sequence of the buffer memory) read from the data memory during reproduction. Is ignored and is not written in the buffer memory.

As described above, the buffer memory is used during recording and reproduction. In the early stage of recording, data may not be stable due to unstable ADM modulation or click noise of switches. In addition, if the buffer memory does not transfer to the data memory in order from the first data after waiting for 256 data to be sent from the beginning at the start of recording, meaningless data will be transferred before that. Become. Also at the start of playback, if you wait until 256 pieces of data transferred from the data memory are accumulated and then transfer to the ADM demodulator in order from the first data, the meaningless data before that will be transferred. Become.

In order to solve these problems relating to the buffer memory, in this embodiment, the first 256 pieces of data sent to the buffer memory at the start of recording are all discarded so as not to be written in the data memory.

FIG. 2 shows an outline of a circuit for performing the above-mentioned recording and reproducing operations.

In FIG. 2, the third input terminal 1 is used for dictation recording.
The analog audio signal S ₁ of FIG. A is input. This signal S
₁ is supplied to the ADM modulator 2 to be converted into, for example, a 1-bit string digital signal D ₀ , and is also supplied to the silence detecting circuit 3 to detect a silent period as shown in FIG. 3B.

When the silence period is not detected by the silence detection circuit 3, the encoder 4 outputs the signal D ₀ of the 1-bit string during the voice period to 8
It is divided into bits and sequentially converted into 8-bit width parallel audio data, which is converted into "02" only when the parallel audio data is "01" in hexadecimal. When there is a change from a voice to a silence state, the silence start code "01" and the silence time code TM _N (maximum 4 seconds) according to the length T _N of the silence period are used by the microcomputer. The parallel audio data which is transferred to the data memory 7 provided in the system controller (hereinafter referred to as “syscon”) 6 and which can include the above “01” → “02” conversion is stored in the buffer memory 5 having 256 addresses at each address. On the other hand, 8 bits are written cyclically. The buffer memory 5 sequentially reads from the first address while writing the next data when the second 256 pieces of data are accumulated, and transfers the read data to the data memory 7 provided in the syscon 6.
Therefore, data D ₁ shown in FIG. 3 C in the data memory 7 is stored.

At the time of reproduction, the data read from the data memory 7 is circularly written in the buffer memory 5. In the buffer memory 5, when the first 256 pieces of data are accumulated, the next data is written while the data is sequentially read from the first address, and the read data is supplied to the decoder 8.

In this decoder 8, a silence start code "01" and a silence time code TM _N are detected from the data D ₁ , a pseudo silence code is generated according to this detection, and this pseudo silence code is inserted into the corresponding portion of the voice data. Then, it is supplied to the ADM demodulator 9 as data D ₂ together with the voice data. The length of this pseudo silence code can be changed by the operation of the user.

In the ADM modulator 9, the data D ₂ is converted into an analog voice signal, and this voice signal is passed through the amplifier 10 to the speaker.
Supplied to 11.

FIG. 1 shows a specific configuration of the circuit shown in FIG.
In particular, the concrete configurations of the encoder 4 and the decoder 8 surrounded by dotted lines are shown. Also, the input terminal 1 in FIG.
The ADM demodulation 2, the silence detection circuit 3, the buffer memory 5, the system controller 6, the data memory 7, the ADM demodulator 9 and the like are designated by the same reference numerals.

In FIG. 1, an operation unit 12 composed of a keyboard is connected to the syscon 6, and the operation unit 12 is operated by a user to select various operation modes such as recording, reproduction, and expansion / contraction of a silent period. It Also, all the various signals from the system controller 6, the encoder 4 and the decoder 8 are input / output circuits 13
Have been given and received through.

At the time of recording, the encoder 4 is operated and the ADM modulator 2 sends the input audio signal S ₁ to the clock CLK ₁ from the clock generator 14.
The signal is converted into a signal D ₀ consisting of 1-bit string serial data based on the above, and is supplied to the serial-parallel conversion shift register 15. This shift register 15 uses the above signal based on the above clock CLK _1.
After serially converting 8-bit serial data of D ₀ into parallel data of 8-bit width, "01" → "02" conversion circuit 16 and "01"
It is supplied to the detection circuit 17. The "01" detection circuit 17 detects the "01" code from the parallel data, and based on this detection, the "01" → "02" conversion circuit 16 converts the "01" code in the parallel data into the "02" code. To do. That is, the “01” detection circuit 17
Includes an 8-input NOR circuit having seven inputs connected to the output bus of the upper 7 bits of the shift register 15, and the remaining one input connected to the output bus of the least significant bit of the shift register 15 via an inverter. Has been done. Therefore, 8 inputs
The NOR circuit outputs H when it detects binary number 00000001 on the output bus. This H is used as a signal for switching the output bus of the lower 2 bits of the “01” → “02” conversion circuit 16 to the binary number 10. Therefore, this "01" →
In the “02” conversion circuit 16, the upper 6-bit output bus of the shift register 15 is directly passed through and connected to the upper 6-bit data bus of the buffer memory 5, and the remaining lower 2-bit output buses are two. It is connected to the data bus of the lower 2 bits of the buffer memory 5 via the switching circuit.
Of course, the "01" detection circuit 17 may be configured by connecting two TTL circuits such as 7485 in a cascade and setting the comparison value to binary number 00000001 in advance for comparison. The clock generator 18 also generates a clock CLK ₂ by dividing the clock CLK ₁ into 1/8 and supplies it to a control circuit 19 for controlling the buffer memory 5. The clocks CLK ₁ and CLK ₂ are also supplied to other circuits.

On the other hand, when the silence period is detected by the silence detection circuit 3, the encode data request generation circuit 20 is operated, and the 8-bit silence timer 21, for example, measures the time from the silence start time to the silence end time. The encoded data request generation circuit 20 sends the data request signal RQ ₁ to the syscon 6 via the input / output circuit 13 and the timing signal ST ₁ to the switching signal generation circuit 22 in response to the detection between the silencers. The content of the signal RQ ₁ includes the transfer request of voice data from the buffer memory 5 to the data memory 7 in the sound period, and the code generation circuit 23 to the data memory 7 from the silent period to the sound period. The request is for the silent start code “01” and the silent time code TM _N , and the transfer is not required during the silent period.

When the silent period changes to the voice period, the switching signal generating circuit 22 outputs the silent start code “0” based on the signal ST _1.
A switching signal ST ₂ for switching between 1 ”and the silent time code TM _N is generated and supplied to the code generation circuit 23. Code generator 23
Generates a silence start code “01” and a silence time code TM _N on the basis of the signal ST ₂ and the timer value T _{N of the} silence period given from the silence timer 21. 7 and send the control signal to the control circuit
Send to 19. At this time, the silent time code TM _N is made up of a value indicating a maximum of 4 seconds.

In the buffer memory 5, the write timing and the address are controlled by the control circuit 19, and the audio data that can be converted into “01” → “02” is cyclically written. In this case, the start-up delay circuit is instructed by the system controller 6.
By operating 24 and controlling the control circuit 19,
The data is controlled so as not to be transferred from the buffer memory 5 to the data memory 7 until the buffer memory 5 stores the second 256 pieces of data.

When 256 pieces of data are accumulated in the buffer memory 5, the addresses are sequentially advanced from the first address and read out,
The read data is transferred to the data memory 7 in response to the request signal RQ ₁ . At this time, new data is cyclically written in the read addresses sequentially and sequentially read. With the above, the operation at the time of recording is completed.

Next, at the time of reproduction, the decoder 8 is operated and the data memory 7 is read, and the audio data in the read data D ₁ is stored in the buffer memory 5 via the input / output circuit 13 in the same manner as at the time of recording. It is written cyclically. At this time, the control circuit 19 is controlled by the startup delay circuit 24, and the data D ₂ is not transferred to the ADM demodulator 9 during the writing of the first 256 data. Of course, the above operation is executed by software by the system controller 6 and related programs. This discards the initial unstable data. Further, the "01" ignore signal generation circuit 26 sends a "01" ignore signal to the control circuit 19 so that the "01" detect circuit 25 does not detect "01" in the first 256 pieces of data. As a result, as described above, the playback start time is the silence time code.
When TM _N and the code content happens to be "01",
This silence time code TM _N is prevented from being erroneously detected as the silence start code “01”.

When the first 256 pieces of data are written in the buffer memory 5, they are sequentially written from the first address. The data is sequentially read from the read address and is sequentially written from the read address. The read data is converted into serial data D ₂ by the shift register 34, and the ADM demodulator 9
Is supplied to.

On the other hand, the “01” detection circuit 25 causes the silence start code “0
When the "1" is detected, the decode data request generation circuit 27 stops outputting the data request signal RQ ₂ , and the timer value detection circuit 28 detects the silence time code TM _N next to the silence start code "01". The length of the silent period, that is, the timer value measured by the silent timer 21 during recording.
Load T _N into silence time control circuit 29.

The silent time control circuit 29 controls the loaded timer value T _N according to the operation of the user, and changes the length of the silent period that is artificially inserted. The silent time control circuit 29 includes a first counter in which the timer value T _N is loaded and a second counter in which the multiplication factor of the silent period is loaded. The first counter counts down the clock obtained by dividing the clock CLK ₂ by 1/32 from the loaded value, and the timer value T _N is loaded again each time it underflows. When it decrements and the second counter underflows, a signal is sent to the decode data request generating circuit 27 as the end of the pseudo silence period. Therefore, if the multiplication factor loaded in the second counter is set to "8", the pseudo-silent period becomes
With CLK ₁ ÷ 32 ÷ 8, it is reproduced in one time of the silent period at the time of recording. When the magnification is set to "0" to "7", the pseudo silent period becomes shorter than the silent period at the time of recording, and a fast listening state is set.

The pseudo silence data generation circuit 30 generates the pseudo silence data D ₃ according to the pseudo silence period controlled by the silence time control circuit 29. This data D ₃ is converted to serial data by the parallel-to-serial conversion shift register 34 and then inserted into the data D ₂ to add ADM.
It is supplied to the demodulator 9. When this pseudo silence period ends, the decode data request generation circuit 27 outputs the request signal RQ ₂ again.

According to the above, the ADM demodulator 9 can obtain the voice signal in which the pseudo silence period having the length controlled by the silence period control circuit 29 is inserted into the original voice signal.

In the figure, 31 is a timing signal generating circuit for writing the data D ₁ once latched in the input / output circuit 13 from the data memory 7 into the buffer memory 5, and 32 is an encode mode from the syscon 6, a decode mode, etc. 3 is a mode setting circuit including a register for storing the mode setting information of FIG.
Also, 33 indicates the mode set by the mode setting circuit 32.
It is an ADM control circuit that controls the ADM operation.

According to the embodiment described above, the following effects can be obtained.

(1) The data amount is reduced by, for example, 30% or more as compared with the case where the silent start code “01” and the silent time code TM _N are recorded without recording the actual silent period at the time of recording, and the buffer memory 7 is used. The rate can be increased.

(2) Since the silent start code "01" is the "01" code that is extremely rare in the audio data,
The silence start code “01” can be arranged at an arbitrary position in the data D ₁ without affecting the sound quality. still,
Codes such as "02" and "03" other than "01" have a low frequency of occurrence, and thus can be used as silence start codes.

(3) Since the maximum detection time of the silent period is set to, for example, 4 seconds, the efficiency in performing the dictation type is improved.

(4) Since the length of the pseudo silent period that reproduces the silent period is variable, it can be played back at a speed that matches the ability of the typist, and it may be possible to speed up the confirmation work after typing. it can.

(5) Since the voiced period is recorded as it is, the sound quality is not deteriorated.

(6) Since the buffer memory 5 is used, it is possible to prevent the head from being cut off at the start of voiced sound.

(7) Since the first 256 pieces of data transferred to the data memory 7 are discarded at the start of recording, unstable data can be removed to prevent malfunction.

(8) Since the silent start code “01” in the first 256 pieces of data transferred to the buffer memory 5 is ignored at the time of starting reproduction, malfunction can be prevented.

Next, an embodiment of the silence detecting circuit will be described with reference to FIGS. 5a to 5e show the output waveforms a to e of FIG.

A conventional silence detection circuit compares an input voice signal with a certain detection level, and when the voice signal is below the detection level is a silent period, and when the voice signal exceeds the detection level is a voiced period. Therefore, when the ambient noise is large, the noise level may exceed the detection level and may be erroneously detected as a voiced period even when the user is not speaking. The silence detection circuit 3 according to the present embodiment changes the detection level according to the ambient noise.

In FIG. 4, the input audio signal S ₁ input to the input terminal 35 (point a) is supplied to the amplifier 36, amplified to a level necessary for rectification described later, and then supplied to the band-pass filter 37. Band (for example, 300 to 3.4 kHz) is extracted. This audio signal is detected by the rectification detection circuit 38, and the detection output is smoothed by the smoothing circuit 39. This smoothing circuit 39 is composed of a switch 40 controlled by a switching signal SW described later, resistors R ₁ and R _{2, a} capacitor C _{1 and the} like. As will be described later, these values have a time constant T ₁ of T ₁ = R ₂ C ₁ when the switch 40 is on in the noise state (silence state), and a time constant T ₁ when the switch 40 is off in the voice state. ₂ is T ₂ = (R ₁ +
R ₂ ) It is set so that C ₁ > T ₁ .

The DC signal smoothed by the smoothing circuit 39 is taken out to the point b, then amplified by the DC amplifier 41, and then added to one input terminal of the comparison circuit 42 as a voice determination level. The voice signal extracted by the bandpass filter 37 is applied to the other input terminal of the comparison circuit 42, and is compared with the voiced judgment level.

The comparison circuit 42 outputs an "L" level signal when the voice signal exceeds the voice determination level, and outputs an "H" level signal when the voice signal is equal to or lower than the voice determination level.

This "L" or "H" level signal controls the switch 40 as a switching signal SW. When it is "L" level, the switch 40 is turned off, and when it is "H" level, the switch 40 is turned on. That is, when the level of the voice signal is higher than the voice determination level and the voice is present, the switch 40 is turned off and the time constant of the smoothing circuit 39 is increased to T ₂ (> T ₁ ). This prevents the voice determination level from rapidly increasing due to the voice portion.

In the voiced state, the output of the comparison circuit 42 is "L".
Level, the resistor R _3, to discharge quickly through the capacitor C ₂ is diode 44 of a time constant circuit constituted 43 at capacitor C _2. The capacitor C ₂ when the output is "H" level of the comparison circuit 42 charges slower. As for the voltage of the capacitor C _2, a predetermined voltage V ₁ is applied to _one input terminal of the comparison circuit 45 from the DC bias voltage voicing circuit 46. Therefore,
From the comparison circuit 45, the silence detection signal S ₂ can be obtained at the output terminal 47 (point e). The voltage V ₁ is also supplied to other predetermined circuits as a bias voltage.

According to the above, it is possible to automatically follow the voiced judgment level in accordance with the steady noise or the slow fluctuation of the ambient noise.

〔The invention's effect〕

According to the present invention, the actual silent period is not recorded at the time of recording, but the marking codes such as the silent start code and the silent time code are recorded instead. Therefore, the utilization rate of the recording capacity of the second recording medium can be increased. Since the first recording medium is used as the buffer memory, it is possible to prevent the sound from being cut off at the beginning of the sound. Furthermore, since the first 256 data to be transferred to the buffer memory is discarded at the start of recording, unstable data can be removed to prevent erroneous operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic block diagram of FIG. 1, FIG. 3 is a timing chart diagram for explaining the principle of the present invention, and FIG. FIG. 5 is a circuit diagram showing an embodiment of the silence detection circuit, and FIG. 5 is a timing chart diagram for explaining the operation of FIG. In the reference numerals used in the drawings, 3 ... silence detection circuit 5 ... buffer memory 6 ... system controller 7 ... data memory 19 ... control circuit 23 ... code generation circuit 24 ... startup delay circuit 25 ... "01" detection circuit 30: This is a pseudo silence data generation circuit.

Claims (1)

[Claims] 1. A detection means for detecting a no-signal period from an input signal during recording, a period excluding the no-signal period of the input signal and a signal indicating the no-signal period based on the detection of the no-signal period. A first recording medium for recording, a second recording medium for transferring signals to and from the first recording medium, and a signal of a reproduction signal reproduced from the second recording medium at the beginning for a predetermined period during reproduction. Control means for controlling not to use, a detection means for detecting a signal indicating the no-signal period from the reproduction signal, and a pseudo no-signal is generated based on the detection of the no-signal period. A digital recording / reproducing apparatus provided with a pseudo no-signal generating means to be inserted into the reproduction signal.