JPH0821817B2 - Muting circuit - Google Patents

Description

The present invention relates to a muting circuit, and more particularly to a muting circuit used in an input section of a GND reference input type amplifier circuit.

[Conventional technology]

As shown in FIG. 2, the conventional muting circuit used in the input section of the GND reference input type amplifier circuit is such that the non-inverting input terminal a and the first input terminal 1 of the GND reference input type amplifier circuit A are Is connected to the resistors R1 and R2, the second input terminal 2 is connected to the resistors R3 and R4, and the connection point between the resistors R1 and R2 is the collector of the grounded transistor Q1 of the emitter terminal. The terminals are connected, and the collector terminal of the transistor Q2 whose emitter terminal is grounded is connected to the connection point of the resistors R3 and R4. A transistor whose emitter terminal is connected to the power supply terminal 4 at the base terminal of the transistor Q1.
The collector terminal of the transistor Q4 of the current mirror circuit composed of Q4 and Q5 is connected, and the transistors Q4 and Q5
The collector terminal of the transistor Q5 is connected to the collector terminal of the transistor Q5 and the collector terminal of the transistor Q6 of the current mirror circuit configured by the transistors Q6 and Q7 whose constant current source I ₁ and emitter terminal are connected to the power supply terminals, respectively. To the common base terminal of the transistors Q6 and Q7, the collector terminal and the emitter terminal of the transistor Q7 are connected to the grounded collector terminal of the transistor Q9, and the base terminal of the transistor Q9 is connected to the emitter terminal via the resistor R8. Transistor Q10 collector terminal and control terminal 8
And the mute control terminal 6 is connected to the base terminal of the transistor Q10. Next, configuration of the base terminal of the transistor Q2, as shown in FIG. 2, the transistors Q4, Q5, Q6, the aforementioned, Q7, Q9, Q10, resistors R8, as for the constant current source I ₁ transistors Q11, Q12, Q13, Q14, Q16,
Q17, resistor R7, and constant current source I ₂ have the same configuration. However, the control terminal 7 is connected to one end of the resistor R7 and the collector terminal of the transistor Q17. Also, Rg ₁ and Rg ₂ connected to the first and second input terminals 1 and ₂ are signal source resistors on the input side, respectively, and resistors connected to the inverting terminal of the GND reference input type amplifier circuit A. R9 and R10 are for determining the amplification factor of the amplifier circuit A.

In this configuration, the operation during steady state will be described.
The input signal is still applied to the first and second input terminals 1 and 2, and the control terminals 7 and 8 are controlled to obtain the signal of the input terminal 1 or the signal of the input terminal 2 from the output terminal 3. It can be done by If a control signal is input to the control terminal 7 and no control signal is input to the control terminal 8, the transistor Q1 on the input terminal 1 side is a current mirror circuit in which the current of the constant current source I ₁ is composed of the transistors Q4 and Q5. The signal input to the input terminal 1 is attenuated by the signal applied to the base of the transistor Q1 and turned on.
Transistor Q2 on the side, the current of the constant current source I ₂ is supplied from the current mirror circuit consisting of transistors Q13, Q14, the OFF state can not be given current from the current mirror circuit consisting of transistors Q11, Q12 to the base of transistor Q2 The signal input to the input terminal 2 is transmitted to the non-inverting input terminal a, amplified, and output from the output terminal 3. Further, when the control signal is not input to the control terminal 7 and the control signal is input to the control terminal 8, the operation is reverse to the above-described operation, the signal input to the input terminal 1 is amplified and output from the output terminal 3. To be done. As described above, in the steady state, the signal input to the input terminal 1 or the signal input to the input terminal 2 is amplified and output to the output terminal 3. When the mute control signal is input to the mute control terminal 6, the transistors Q10 and Q17 are turned on, the transistors Q9 and Q16 are turned off, and the currents of the constant current sources I ₁ and I ₂ are respectively the current mirror transistor Q4. , Q5 and transistors Q11, Q12 are supplied to the base terminals of the transistors Q1, Q2, respectively, the transistors Q1, Q2 are turned on, the signals input to the input terminals 1, 2 are attenuated, and the signals from the output terminal 3 are output. It is no longer output, and muting has been applied.

[Problems to be Solved by the Invention]

In this muting circuit, the DC voltage Va ₁ which the non-inverting input terminal normally has is as shown in equation (1).

Here, I _IN is a current value that flows out from the GND reference input type amplifier circuit A, and V _{CESAT (Q1)} is a saturation voltage value that the transistor Q1 has.

Next, when muted, the DC voltage Va ₂ of the non-inverting input terminal
Becomes as shown in equation (2).

Here, V _{CESAT (Q2)} is the saturation voltage value of the transistor Q2.

The voltage value of the difference between Va ₁ and Va ₂ shown in the equations (1) and (2) is multiplied by the amplification factor of the amplification circuit A via the amplification circuit A, and the DC voltage of the output terminal 3 is changed. This fluctuation becomes a shock sound during mute.

Here, (1), (2) expression _{R2 = R4 = 10KΩ, Rg 2} = 1
0 KΩ, V _{CESAT (Q1)} = V _{CESAT (Q2)} = 3.2 mV, I _IN = 0.23 μA, A
Substituting a value of v = 100 times, Va ₁ = 3.88 [mV], Va ₂ = 4.3
It becomes 5 [mV], the difference between Va ₁ and Va ₂ is 0.47 [mV], and the DC change at the output terminal 3 is 47 [mV].

[Means for solving the problem]

A muting circuit according to the present invention includes first and second resistors connected between a non-inverting input terminal and a first input terminal of a GND reference input type amplifier circuit, the non-inverting input terminal and the second resistor. Third and fourth resistors connected between the input terminal and the fifth and sixth resistors connected between the non-inverting input terminal and GND.
A first transistor whose collector terminal is connected to the connection point of the first resistance and the second resistance, and a second transistor whose collector terminal is connected to the connection point of the third resistance and the fourth resistance. For supplying the current of the first constant current source to the transistor, the third transistor having the collector terminal connected to the connection point of the fifth resistor and the sixth resistor, and the base terminal of the first transistor. A first current mirror circuit, a circuit for supplying a current to the first constant current source by a control signal, and a circuit for cutting off the current supply by a mute control signal, and a second constant current source at the base terminal of the second transistor. Current mirror circuit for supplying a current to the second constant current source, a circuit for supplying a current to the second constant current source by a control signal, and a circuit for cutting off the current supply by a mute control signal, and a third and a base terminal of the transistor. Three The current mirror circuit for supplying the current of the constant current source and the circuit for supplying the current to the third constant current source by the mute control signal are included, and the emitters of the first, second and third transistors are It is grounded.

[Action]

As shown in the above configuration, the fifth and sixth resistors, the third transistor, the current mirror circuit for supplying the third constant current source to the base terminal of the third transistor, and the third resistor. By adding a circuit for supplying a current by the mute control signal to the constant current source, the level change at the time of mute switching of the non-inverting input terminal can be made smaller than that of the conventional one without them.

Preferably, the DC voltage that the non-inverting input terminal normally has
Since the DC voltage Va ₂ which Va ₁ and the non-inverting input terminal have at the time of mute are respectively expressed by the equations (4) and (5) described later, the resistance values of the second, fourth and sixth resistors are almost Equalize,
The resistance value of the fifth resistor is made substantially equal to the sum of the resistance value of the third resistor and the signal source resistance value of the second input terminal, and the first, second,
It is better to make the saturation voltage values of the third transistor substantially equal to each other, so that the DC voltages Va ₁ and Va ₂ become substantially equal to each other, and as a result, the shock at the time of mute switching can be almost eliminated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the muting circuit of the present invention, and the equivalent parts in FIG.

In the figure, resistors R5 and R6 are connected between the non-inverting input terminal a of the GND reference input type amplifier circuit A and GND, and the resistor R5
The collector terminal of the transistor Q3 whose emitter terminal is grounded is connected to the connection point between the resistor R6 and the resistor R6, and the base terminal of the transistor Q3 is composed of the transistors Q18 and Q19 whose emitter terminals are connected to the power supply terminal 4, respectively. The collector terminal of the transistor Q18 of the current mirror circuit is connected, and the common base terminals of the transistors Q18 and Q19 are
The collector terminal of the transistor Q19 and the collector terminal of the transistor Q20 of the current mirror circuit, which is composed of the transistors Q20 and Q21 whose constant current source I ₃ and emitter terminal are respectively connected to the current terminal, are connected to each other.
The common base terminal of 20, Q21 is the grounded transistor Q23 of the collector and emitter terminals of transistor Q21.
And the mute control terminal 6 is connected to the base terminal of the transistor Q23. The other circuit configuration is the same as that of FIG. 2 and is omitted. Where R2 = R4 = R
6, R5 = R3 + Rg ₂ , V _{CESAT (Q1)} = V _{CESAT (Q2)} = V _{CESAT (Q3)}
(V _{CESAT (Q3)} is set to be the saturation voltage value of the transistor Q3).

In such a configuration, in a steady state, the signal input to the input terminal 1 or the signal input to the input terminal 2 is amplified and output to the output terminal 3, as described in the conventional example. At this time, the current of the constant current source I ₃ is supplied to the base terminal of the transistor Q3 via the current mirror circuit composed of the transistors Q18 and Q19 and turned on. Also, when the mute control signal is input to the mute control terminal 6, current is supplied to the base terminals of the transistors Q1 and Q2 as in the conventional example to turn on, and the signals input to the input terminals 1 and 2 are attenuated. , No signal is output from the output terminal 3, and muting is applied. In this case the current supply to the base terminal of the transistor Q3, eliminates by being supplied to the constant current source I ₃ through the current mirror circuit transistors Q23 consists becomes transistors Q20, Q21 in the ON state, transistor Q3 and an off state Become.

Normally, the DC voltage Va ₁ of the non-inverting input terminal is (3)
As shown in the formula, The DC voltage Va ₂ at the non-inverting input terminal during mute is as shown in equation (4).

Comparing equations (3) and (4), R2 = R4 = R6, R5 =
Since R3 + Rg ₂ , V _{CESAT (Q1)} = V _{CESAT (Q2)} = V _{CESAT (Q3)} , Va ₁ = Va ₂ and DC fluctuation at output terminal 3 does not occur, that is, shock at mute switching. Can be eliminated.

〔The invention's effect〕

As described above, the present invention includes the fifth and sixth resistors, the third transistor, the current mirror circuit for supplying the current of the third constant current source to the base terminal of the third transistor, By adding a circuit for supplying current to the third constant current source by the mute control signal, shock noise at the time of switching mute is reduced, and further, the DC voltage of the non-inverting input terminal at the time of normal and mute is reduced. By making the values almost the same, it is possible to eliminate the shock noise when switching the mute.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an embodiment of a muting circuit of the present invention, and FIG. 2 is a circuit of a conventional muting circuit used for an input part of a GND reference input type amplifier circuit. It is a figure. Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q1
5, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23 …… Transistor, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10 …… Resistance, Rg ₁ , Rg ₂ … … Signal source resistance, I ₁ , I ₂ , I ₃ …… Constant current source, 1 …… First input terminal, 2 …… Second input terminal, 3 …… Output terminal, 4 …… Power supply terminal, 6 …… Mute control terminal, 7,8 …… Control terminal, a …… Non-inverting input terminal, A …… GND reference input type amplifier circuit.

Claims (1)

[Claims] 1. A first and a second resistor connected between a non-inverting input terminal and a first input terminal of a GND reference input type amplifier circuit, said non-inverting input terminal and second input terminal. A third and a fourth resistor connected between the first and second resistors, a fifth and a sixth resistor connected between the non-inverting input terminal and GND, and a connection between the first resistor and the second resistor. A first transistor having a collector terminal connected to the point, a second transistor having a collector terminal connected to the connection point of the third resistor and the fourth resistor, the fifth resistor and the sixth resistor A third transistor having a collector terminal connected to a connection point of the resistor, a first current mirror circuit for supplying a current of the first constant current source to a base terminal of the first transistor, The current is supplied to the constant current source No. 1 by the first control signal, and the mute control signal A circuit for cutting off the current supply by the second constant current source, a second current mirror circuit for supplying the current of the second constant current source to the base terminal of the second transistor, and a second current mirror circuit for the second constant current source. And a circuit for supplying current by the control signal and cutting off the current supply by the mute control signal, and a third current mirror for supplying the current of the third constant current source to the base terminal of the third transistor. A circuit and a circuit for supplying a current to the third constant current source by the mute control signal, wherein the emitters of the first, second and third transistors are grounded. Muting circuit.