JPH0823573B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a diagnostic circuit of a semiconductor integrated circuit, and particularly to a diagnostic of an LSI in which a large scale integrated circuit (hereinafter abbreviated as LSI) is used as one cell. The present invention relates to a suitable semiconductor integrated circuit diagnostic circuit.

[Conventional technology]

It is well known to incorporate a diagnostic circuit to determine whether the LSI operates normally. For example, JP-A-56
As described in Japanese Laid-Open Patent Publication No.-92652, diagnostic data is scanned into a latch and the data is used to diagnose a logic circuit up to the next latch. However, no consideration has been given to diagnosing a logic circuit that has an internal latch such as an LSI, for example, a microprocessor or a peripheral LSI and is functionally integrated.

[Problems to be solved by the invention]

With the increase in the size of LSIs, it has been proposed to combine the functions of a microprocessor or peripheral LSIs to make one LSI. In this case, the microprocessor and peripheral LS
As for I, there are established technologies in the past, so
In making one LSI, the pattern of each LSI as it is is provided on one chip, and the function of each LSI is created on one chip. It takes a great deal of effort to create a test pattern to collectively test whether or not the integrated LSI operates normally. Therefore, as seen in the above-mentioned prior art, each function of the microprocessor or the like is divided to provide a latch, and if the diagnostic data is scanned into this latch, the latch provided in each function of the microprocessor or the like is scanned. An in-circuit will be added, and a new design effort will be required. LS for each function
Since I will be divided, the test pattern already created for the conventional independent LSI microprocessor or peripheral LSI will not be useful.
In addition, the provision of the scan-in latch between each function of the microprocessor and the peripheral LSI has a problem of destroying the merit that they can be configured as a bus.

An object of the present invention is to combine the functions of a microprocessor or peripheral LSI having already established technology into one LSI to separate the diagnostic circuit at the time of normal operation and at the same time one microprocessor or at the time of diagnosis. The purpose is to enable diagnosis as a peripheral LSI.

[Means for solving problems]

The above object is to provide a transfer MOS transistor on the signal line connecting the microprocessor function or the peripheral LSI function in one LSI, and at the same time, connect the diagnostic circuit via the transfer MOS transistor to the output side of the MOS transistor. It is achieved by

[Action]

During normal operation, the transfer MOS transistor between the microprocessor function and the peripheral LSI function is turned on, and the transfer MOS transistor connected to the diagnostic circuit is turned off. As a result, the microprocessor function or the peripheral LSI function operates by sending and receiving signals between them.

During diagnosis, microprocessor function or peripheral LS
The transfer MOS transistor between the I functions is cut off, and the transfer MOS transistor connected to the diagnostic circuit is turned on. As a result, the microprocessor function or the peripheral LSI function is separated from the surrounding circuits, and the diagnostic circuit can input and output. Therefore, the target microprocessor or peripheral LS from the diagnostic circuit
I can be tested alone.

The above is described with reference to FIG. In one LSI 10, a microprocessor function block 1, a peripheral LSI function block 2 and a diagnostic circuit 3 are built in. During normal operation, the microprocessor function block 1 and the peripheral LSI function block 2 operate as an LSI 10 as shown in FIG. Next, when diagnosing the microprocessor function block 1, the microprocessor function block 1 and the peripheral LSI function block 2 are disconnected as shown in FIG.
The microprocessor function block 1 and the diagnostic circuit 3 are connected. Here, the diagnostic data is supplied from the external input pin of the LSI 10 and the output pin of the diagnostic circuit 3. The operation result of the microprocessor function block 1 based on this diagnostic data is
It is output to the external output pin and the input pin of the diagnostic circuit 3. This result is compared with the expected value, and the next diagnostic data is input in sequence. Also, peripheral LSI function block 2
When diagnosing is shown in FIG. Also in this case, the diagnosis is performed by the external pin and the diagnosis circuit 3 similarly to the above.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. A microprocessor function block 1 having a conventional microprocessor function and a peripheral LSI function block 2 having a conventional peripheral LSI function are formed on one chip,
It is one LSI10. The signals of the microprocessor function block 1 are those directly connected to the outside of the LSI 10 and those of the LSI 10
Some are connected to the peripheral LSI function block 2 inside. Among the signals connected to the peripheral LSI function block 2, the output signal A and the input signal B of the microprocessor function block 1 are connected via the transfer MOS transistor 20.
In addition, the bidirectional signal C is a transfer MOS transistor 2
Connect 0 through two. The signals A and B are connected to the output side of the transfer MOS transistor 20 and the diagnostic circuit 3 via the transfer MOS transistor 30. The bidirectional signal C is transferred between the two transfer MOS transistors 20 via the transfer MOS transistor 30 and the diagnostic circuit 3
Connect to. A signal E that separates the normal operation time from the diagnosis time is input to the gate 10. The output of the gate 10 has a positive polarity and a negative polarity. The positive output of the gate 10 is input to the OR gates 12 and 13. The negative output of the gate 10 is input to the gate of the transfer MOS transistor 30 connected to the diagnostic circuit 3. A signal F for dividing the microprocessor function block 1 and the peripheral LSI function block 2 at the time of diagnosis is input to the gate 11. The output of the gate 11 has a positive polarity and a negative polarity. The positive output of gate 11 is input to OR gate 13, and the negative output of OR gate 12
To enter. The output of the OR gate 12 is the signal A and the bidirectional signal C
Input to the gate of the transfer MOS transistor 20 ₁ 20 ₂ 20 ₅ 20 ₇ on the microprocessor function block 1 side. O
The output of the R gate 13 is input to the gates of the transfer MOS transistors 20 ₃ 20 ₄ 20 ₆ 20 ₈ on the peripheral LSI side of the signal B and the bidirectional signal C. Here, the diagnosis circuit 3 is composed of a flip-flop 70 as shown in FIG. Signal G is a selector
Input to 50 select signals, for data 1 and transfer
The signal H from the MOS transistor 30 is selected. The output of the selector 50 is input to the data of the flip-flop 40,
The clock Q1 is used as the clock of the flip-flop 40. The output of the flip-flop 40 is output as the data 1 of the next stage and is simultaneously input to the data of the flip-flop 41. The clock Q2 is used as the clock. The output of the flip-flop 41 is connected to the signal H via the transfer MOS transistor 60. On the other hand, the data 2 is input to the data of the flip-flop 42, and its clock uses the clock Q3. The output of the flip-flop 42 is output as the data 2 of the next stage and is simultaneously input to the data of the flip-flop 43. The flip-flop 43 inputs the clock Q3 to the clock, and its output is the transfer MOS described above.
Input to the gate of transistor 60. A description of each clock and signal G will be given later.

First, the normal operation will be described with reference to FIG.
The signal E is set to a high potential during normal operation. As a result, the negative polarity power of the gate 10 becomes a low potential, and the transfer MO
The S transistor 30 is cut off and the diagnostic circuit is disconnected.
The positive output of the gate 10 inputs a high potential to the transfer MOS transistor 20 via the OR gates 12 and 13. Therefore, the transfer MOS transistor 20 becomes conductive and the microprocessor function block 1 and the peripheral LSI function block 2 are connected. In this state, the microprocessor function block 1 and the peripheral LSI function block 2 can functionally operate.

When diagnosing the microprocessor function block 1, the signal E is set to low potential and at the same time the signal F is set to low potential. When the signal E is set to a low potential, the negative output of the gate 10 becomes a high potential, the transfer MOS transistor 30 becomes conductive, and the diagnostic circuit is connected. When the signal F is set to low potential, the gate 11
The negative output of becomes high potential, and the output of the OR gate 12 becomes high potential. As a result, the transfer MOS of the signal A and the bidirectional signal C on the side of the microprocessor function block 1 is transferred.
Transistors 20 ₁ 20 ₂ 20 ₅ 20 ₇ conduct. Also, OR gate
Since the output of 13 has a low potential, the transfer MOS transistors 20 ₃ 20 ₄ 20 ₆ 20 ₈ of the signal B and the bidirectional signal C on the peripheral LSI function block 2 side are cut off. As a result, the microprocessor functional block 1 is directly connected to the diagnostic circuit 3. Here, the microprocessor function block 1 can be operated by the diagnostic circuit 3 and external input / output signals. The operation of the diagnostic circuit 3 will be described with reference to FIG. First, before inputting the diagnostic data, there is a signal which becomes an input or an output of the microprocessor functional block 1, and the diagnostic circuit 3 sets each signal H as an output or an input. For this purpose, a high potential when the diagnostic circuit 3 is an output from the data 2 and a low potential when the diagnostic circuit 3 is an input are sequentially input to the flip-flop 42 using the clock Q3. Since the output of the flip-flop 42 is the data 2 of the next stage, the data is set in all the flip-flops 42 by repeating the clock Q3 for the number of stages of the flip-flop 20. After this is done, clock Q4
The data is set in the flip-flop 43 by inputting. If the output of the flip-flop 43 is high potential, the transfer MOS transistor 60 is conductive, and if it is low potential, it is cut off. After that, diagnostic data is input, but at this time, the signal G is set to a high potential. By setting the signal G to a high potential, the input of the selector 50 selects the data 1. The data 1 is sequentially input by inputting the clock Q1 so that predetermined diagnostic data is input to the place where the microprocessor function block 1 is input, and the clock Q1 is input to the flip-flop 40. After the setting of the flip-flop 40 is completed, the clock Q2 is input and set in the flip-flop 41. The diagnostic data set in the flip-flop 41 is input to the microprocessor functional block 1 because the transfer MOS transistor 60 is conductive and the transfer MOS transistor 30 is conductive. At this time, if an external input is also input at the same time as the clock 2, the microprocessor functional block 1 operates according to the diagnostic data and outputs it. This output result is output to the outside, and at the same time, the signal H that is input to the diagnostic circuit 3
Is output to Here, the signal G is set to a low potential and the selector 50
When the signal H is selected and the clock Q1 is input, the result of the operation of the microprocessor 1 is the flip-flop 40.
Is set to This result is sequentially output from the final stage of the diagnostic circuit 3 by inputting the clock Q1. This result is compared with the expected value. It is confirmed whether or not the microprocessor function block 1 is operating normally by successively continuing the input of the diagnostic data to the diagnostic circuit 3 and the operation confirmation from the diagnostic circuit 3.

When the peripheral LSI functional block 2 is diagnosed, the signal E is set to a low potential and the signal F is set to a high potential, so that the peripheral LSI 2 is directly connected to the diagnostic circuit 3 as in the case of the diagnosis of the microprocessor functional block 1. This confirms whether the operation of the peripheral LSI functional block 2 is normal.

〔The invention's effect〕

 The present invention has the following effects.

(1) Since each functional LSI can be directly connected to the diagnostic circuit at the time of diagnosis, if the functional LSI is already completed, the test can be easily performed.

(2) Since the test is easy, even if a defect occurs, it is easy to point out the defective portion and the man-hour for defect analysis is reduced.

(3) The diagnostic circuit is disconnected during normal operation, and there is no need to consider diagnostics during logic design.

[Brief description of drawings]

FIG. 1 is a logic diagram showing an embodiment of the present invention, FIG. 2 is a conceptual explanatory diagram of the present invention, and FIG. 3 is a diagnostic circuit diagram. 1 ... Microprocessor function block, 2 ... Peripheral LSI function block, 3 ... Diagnostic circuit, 20 ... Transfer MOS transistor, 30 ... Transfer MOS transistor.

Claims (1)

[Claims] 1. A semiconductor integrated circuit including a first functional block for realizing a function as a microprocessor and a second functional block for realizing a function as a peripheral LSI, wherein the first and second functional blocks are provided. A diagnostic circuit block for diagnosing the semiconductor integrated circuit, a first signal line for inputting an instruction signal of one of two operation modes of the semiconductor integrated circuit, a normal use mode and a diagnostic mode, and the first signal line. , A second signal line for inputting a command signal for selecting one of the second function blocks, and a command signal for the first and second signal lines, in the normal use mode. Switching for electrically connecting the first and second functional blocks and electrically connecting one functional block instructed by the second signal line to the diagnostic circuit block in the diagnostic mode. A semiconductor integrated circuit comprising means.