JP2978692B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main circuit having a predetermined function and a semiconductor integrated circuit having a plurality of lead pins.

[0002]

2. Description of the Related Art As shown in FIG. 4, a boundary scan is a test for handling a semiconductor integrated circuit having a design structure in which a register cell 41 is arranged between each device and an internal logic 42 (hereinafter referred to as a device). Technology (I
EEE Standard 1149.1). These register cells 4
At 1, the occurrence events of each input and output pin 47, 48 can be controlled and observed. When the register cells 41 are connected in series, a data register chain called a boundary register is formed. There are other registers as well, and the instruction register 45 decodes the instruction bits, so that the device can execute various functions. The bypass register 44
Provide a 1-bit path that minimizes the distance from scan input to scan output. INCODE register 43
Identifies the device and the manufacturer. Further, a test access port (TAP) controller 46 having a plurality of device pins dedicated to input, output and control functions is provided.

[0003] EXTEST, BYPAS are indispensable public instructions described in IEEE Standard 1149.1.
S, and SAMPLE / PRELOAD, but EXTEST will be described here. EXTEST mainly deals with a test of a circuit from a boundary register cell to any point outside the device, and has the following three functions. A stand-alone function to test the connection circuit between the boundary register and the device under test and the circuit board, an interconnect function to test the circuit connecting the boundary register and the boundary scan device, and a test between the boundary register and the boundary scan device Cluster function for testing mounted circuits. Here, the stand-alone function will be particularly described. When testing the boundary register cells, the bonding wires between the register cells, and the solder connections between the terminals and the circuit board, the data bits presented to the input of the device are captured by the input register cells, shifted out and analyzed. Is done. The output is also tested by bit loading the output register cells bit-serial and examining the parallel latch outputs.

Japanese Patent Application Laid-Open No. 3-160377 discloses a main circuit having a predetermined function, a plurality of wirings connected to the main circuit, and connection for every two wirings except for the ground wiring of the plurality of wirings. Logic inversion element, and a logic inversion element power supply circuit for supplying power to the logic inversion element.

FIG. 5 is a schematic plan view showing a state of mounting on a printed circuit board. As shown in the figure, power supply pins 31b and 43b provided on a package 30 of a semiconductor integrated circuit are connected to power supply printed wirings 51 and 63 on a printed circuit board 50, and similarly, a ground pin 32b is connected to a grounded printed wiring 5
2 and the signal pins 33b to 42b
To 62 respectively. The power supply pin 31b is connected to the power supply lead 31, the bonding wire 26, and the power supply wiring 11.
Is connected to the main circuit 24 on the semiconductor integrated circuit chip 10, and the ground pin 32b is connected to the ground lead 32 and the ground wiring 1.
2 and connected to the main circuit 24. Signal pin 33
b to 42b are signal leads 33 to 42 and signal wirings 13 to 2
2 and connected to the main circuit 24. Power supply pin 43
b is the power supply lead 43 for the inversion element and the bonding wire 2
6 through the power lead 23 for the logic inversion element and the main circuit 2
4 is connected. Signal printed wiring 54, 55, 5
Shorting bars 64 are provided between 6, 6 and 57, 58 and 59, and 60 and 61, respectively.

Next, a test method will be described. In FIG. 5, a power supply is connected to a power supply printed wiring 63 for a logical inversion element without connecting a power supply to the power supply printed wiring 51. As a result, the logic inversion element 25 is activated, but the main circuit 24 is not activated. In this state, the signal printed wirings 54 and 55, 56 and 57, 58 and 59, and 60 and 61 are short-circuited by a jig or the like using a shorting bar 64, and the signal printed wiring is not shown. Similarly, the wirings 62 and 53 are temporarily short-circuited by a jig or the like. In such a state, the series connection circuit of logic inversion elements 25 performs a ring oscillation operation. By detecting this, it is possible to confirm that the signal pins 32b to 42b are normally connected to the printed wirings 52 to 62. On the other hand, if any one or more of the connection points are open, a series connection circuit of the logic inversion elements 25 is not formed, and no ring oscillation operation is shown. Therefore, it can be clearly distinguished from a case where all connection points are normally connected.

[0007]

As described above,
When a device is mounted on a printed circuit board, a conventional boundary scan requires a register for the boundary scan. This register requires several tens of transistors, and has the disadvantage of increasing the area.

In Japanese Patent Application Laid-Open No. 3-160377, a jig tool for short-circuiting each terminal is required to connect the logic inversion elements in series. When the number of pins increases, the distance between the pins also decreases, and extra Cost and technical disadvantages.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit which requires fewer elements than a boundary scan and does not require a tool for short-circuiting terminals.

[0010]

SUMMARY OF THE INVENTION The present invention provides a main circuit having a predetermined function and a first lead connected to the main circuit.
Group and a second lead provided independently of the first lead group.
And a lead between adjacent leads in the first lead group.
Opening / closing is controlled by a signal applied to the second lead
Semiconductor integrated circuits connected in series by transfer gates
The signal applied to the second lead is
Transfer gate through an input buffer
This is applied to the sheet. In addition,
Spher gate is the output of input buffer or input buffer
Controlled by the output of the inverter connected to the output of
Things.

[0011]

Since the lead pins are arbitrarily opened and shorted by the transfer gate, the number of elements to be added can be reduced, and a tool for short-circuiting each terminal is not required. further,
Transfer gates are placed only between the lead pins.
Therefore, the effect of the delay time is the capacitance of the transfer gate.
The effect is small due to the load alone.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view of a semiconductor integrated circuit according to one embodiment of the present invention. Main body circuit 12 having predetermined function
Also includes an input / output buffer. The leads 14 to 18 from the main circuit 12 are passed through bonding pads (not shown) to bonding wires (not shown). The leads 14 to 18 are connected by both transfer gates of the NMOS transistor 22 and the PMOS transistor 21. The transfer gate is controlled by the input buffer 11 and the inverter 10 by a signal input from the lead 20, and when the lead 20 is "H", it is turned on, and all the leads 14 to 18 are short-circuited. When the lead 20 is "L", it is turned off and becomes an open state, that is, a body circuit test state.

To mount the semiconductor integrated circuit 13A of this embodiment on a printed circuit board and check whether each of the leads 14 to 18 is connected to the printed circuit board, set the lead 20 to "H" and connect the leads 20 to the transfer gate. The continuity check may be performed through the printed circuit board from the first lead 14 to the last lead 18 of the leads. If all connections to the printed circuit board are OK, the transfer gate short-circuits all the leads 14 to 18 , and conduction is confirmed. If there is any connection failure, conduction cannot be achieved. In the connection by the transfer gate, each lead must not be connected in a ring shape, and one part must be cut.

FIGS. 2 and 3 are plan views of a semiconductor integrated circuit according to another embodiment of the present invention. The semiconductor integrated circuit 1 of FIG.
In 3B, the transfer gate is constituted by the NMOS transistor 22, and the operation is the same as that of the embodiment of FIG. Further, in the semiconductor integrated circuit 13C of FIG. 3, the transfer gate is constituted by the PMOS transistor 21, and the operation is the same as that of the embodiment of FIG.

[0015]

As described above, according to the present invention, the transfer gate of the MOS is connected so as to connect each lead to each other and can be arbitrarily short-circuited and opened. No more than one element is required, and no jigs or tools are required which are short-circuited as compared with JP-A-3-160377. Even if the number of pins is increased, there is no technical difficulty and it can be easily realized.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a schematic plan view of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 shows a first conventional example (Boundary Scan IEEE)
It is a figure which shows Standard 1149.1-1990).

FIG. 5 is a diagram showing a second conventional example (Japanese Patent Application Laid-Open No. 3-160377).

[Explanation of symbols]

10 inverter 11 the input buffer 12 the body circuit 13A, 13B, 13C semiconductor integrated circuit 14-18 lead 20 of the test terminal lead 21 PMOS transistor 22 NMOS transistor

Claims (2)

(57) [Claims] 1. A main circuit having a predetermined function, a first lead group connected to the main circuit, and the first lead group
And a second lead provided independently of the first lead.
Between the leads adjacent to each other in the
Controlled by the signal applied to the transfer
-In semiconductor integrated circuits connected in series by gates,
The signal applied to the second lead is in the main circuit.
Gate of the transfer gate through an input buffer
A semiconductor integrated circuit characterized in that the voltage is applied to a sheet . 2. The transfer gate according to claim 1, wherein :
Connected to the output of the buffer or the output of the input buffer
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is controlled by an output of an inverter .