JPH0823997B2 - Read circuit of semiconductor memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit of a semiconductor memory, and more particularly to a read circuit of a static random access memory (hereinafter referred to as SRAM).

2. Description of the Related Art FIG. 3 is a circuit diagram of a read circuit of a conventional semiconductor memory. In FIG. 3, 22, 24, 26, 28, 30 are P-channel MOSFETs, 32, 34, 36 are N-channel MOSFFTs, 38 is an inverter, D, D * are data bus lines, and Q, Q * are sense amplifiers. Output, D _OUT is output data of the read circuit, and O is a control signal of the sense amplifier.

When the control signal O is "L" level, P-channel MOSFET2
2, 24, 26 become conductive, the data bus lines D, D * have the same potential, and the sense amplifier outputs Q, Q * also have the same potential, but they are precharged to near the power supply voltage by the P-channel MOSFET 24. This precharge causes the inverter 38 to bring D _OUT to the "L" level and Q and Q * to the "H" level, so that the P-channel MOSFETs 28 and 30 are non-conductive.
That is, when the control signal O is at "L" level, the initial state for the read operation is set. However, D _OUT is at the "L" level in the initial state. Next, when the data read operation of the memory cell is started and the control signal O becomes "H" level, the data bus lines D and D * start to generate a potential difference. P
The channel MOSFETs 22, 24 and 26 are turned off, and the N-channel MOSFET 26 is turned on, so that the potentials of Q and Q * change according to the potentials of D and D *. Q and Q * are outputs of a MOS type differential amplifier having D and D * as inputs, and the control signal O controls the differential amplifier to an operating state and an initial state. Then, the potential of the output D _OUT of the read circuit is fixed by the potential change of Q and Q *. [IEEE JOURNAL OF SOLID-STATE CIRCUIT
S) VOL, SC-20, No.5, OCTOBER1985 pp935-940].

Problems to be Solved by the Invention In the conventional example of FIG. 3, by setting the sense amplifier to the initial state by the control signal O, the output data D _OUT falls to the “L” level during the initial state and the address changes. Since initialization is performed every time, the current consumption increases. Further, since the initial state is set, the data holding time becomes short. If the data retention time is short, the margin of the timing specifications becomes small, which makes it difficult to use. For example, when the load capacity of output data is large, the current consumption increases. On the other hand, if the gate width of the inverter is increased in consideration of the delay time for speeding up, the load capacitance of the output of the sense amplifier increases,
It is difficult to significantly reduce the delay time of the sense amplifier.

Thus, in the read circuit of the conventional semiconductor memory,
By setting the sense amplifier to the initial state, the data retention time is shortened, which leads to an increase in current consumption when the output load capacitance is large, and the gate width of the inverter is increased in consideration of the delay time for speedup. Then, the load capacitance of the output of the sense amplifier increases, and it is difficult to significantly reduce the delay time of the sense amplifier.

The present invention has been made in view of the above circumstances, and provides a semiconductor memory read circuit capable of reading at high speed and low power consumption without shortening the data holding time even when the sense amplifier is in the initial state.

Means for Solving the Problems In order to solve the above problems, the present invention provides means for initializing a data bus line with a first control signal and a latch for reading data on the data bus line with a first control signal. Means and first
Delaying means for delaying the control signal of 1 to generate the second control signal, inverting means for inverting the normal output of the latch means, and inverting output of the latch means and output of the inverting means by the second control signal. And an output buffer for inputting the inverted output of the latch means and the output of the inversion means. After initializing the data bus line, when the potential change occurs in the data bus line, the latch means operates. The output buffer is operated at high speed by short-circuiting the inverting output and the inverting output of the latching means before the output of the reading and inverting means changes.

Operation According to the present invention, even if the data bus line is initialized, the data holding time is not shortened because the latch means holds the previous data. Further, since there are two input signals of the output buffer and they are electrically short-circuited before the output of the inverting means changes, output data can be obtained at high speed.

Embodiment 1 FIG. 1 is a circuit diagram showing an embodiment of a read circuit of a semiconductor memory of the present invention. FIG. 2 is an operation waveform diagram for explaining the operation of the circuit of FIG. In FIGS. 1 and 2, 2 is a means for initializing the data bus lines D, D * consisting of N-channel MOSFETs 11, 12 with the first control signal O ₁ , 4 is the data D of the data bus lines, D * is the first control signal O
P-channel MOSFET 13, P-channel M to read in ₁
Latch means composed of the OSFET 14, inverters 15 and 16, 6 is a delay means composed of inverters 17 and 18 for delaying the first control signal O ₁ to generate a _second control signal O ₂ , and 8 is a positive means of the latch means 4. Inverting means (inverter) for inverting the transfer output Q,
Reference numeral 10 is an output Q _i of the inverter 8 and an inverted output Q of the latch means 4.
P-channel MOSFET for electrically connecting * with the second control signal O ₂ ; 12 denotes the output Q _{i of the} inverter 8 to the gate input of the P-channel MOSFET 19 and the inverted output Q * of the latch means 4;
Is an output buffer whose gate input is to the N-channel MOSFET 20.

At time t ₁ , the control signal O ₁ rises and the initialization means 2 starts discharging the data bus lines D and D *.

At the same time, the latch means 4 becomes electrically non-conductive with the data bus lines D, D *, and the latch means 4 holds the previous data. O ₁ is also input to the delay means 6, and the time
O ₂ rises at t ₂ . This allows P-channel MOSFET 10
Becomes non-conductive and Q _i and Q * are electrically separated. At time t ₃ , the control signal O ₁ falls, and the initialization means 2 completes the discharge of the data bus lines D, D *, and both D, D * become "L" level.

At the same time, the latch means 4 is electrically connected to the data bus lines D, D *, and both of the data bus lines D, D * are at "L" level. The potential starts to rise from the L "level. At time t ₄ , the control signal O ₂ falls and the P-channel MOSFET 10 becomes conductive again.

As a result, one of D and D * rises to the “H” level at time t ₅ because Q _i and Q * are short-circuited, and one of Q and Q * rises at time t _6. To go to the “H” level,
Q _i changes at time t ₇ . P channel MO at time t4
Qi and Q *, which are conducting by SFET10, are Q at time t6.
Although * causes a level change, it affects Qi through the P-channel MOSFET 10 and accelerates the level change of Qi at time t7. As a result, the gate inputs of the output buffer 12 have the same phase for both the P channel and the N channel, and high speed operation is possible. Output data until it but not change at time t ₈ holds previous data.

For example, assuming that D changes from "L" level to "H" level, D * holds "L" level. Due to the rise in the potential from time t3 to D, Q * slightly drops the potential until time t4, the potential drop is accelerated at time t5, and reaches the “L” level at time t6. On the other hand, Q raises the potential slightly until time t4, and the potential rise is accelerated at time t5 and reaches the “H” level at time t6. As a result, Qi reaches the “L” level at time t7. At this time, the P-channel MOSFET 10 becomes electrically conductive from the time t, so that the potential change of Q * to the “L” level affects the potential change of Qi, so that the Qi is rapidly brought to the “L” level. The output buffer 12 can be driven at high speed.

In FIG. 1, D, D are used as means for initializing the data bus line.
An example of discharging * has been shown, but as another example of the initialization means, one that equalizes D, D * or D, D
It goes without saying that the same effect can be obtained as long as D and D * are set to the same potential, such as precharging *.

As described above, according to the present invention, even when the data bus line is in the initial state, the output buffer can be driven at high speed without shortening the data holding time of the output data. A circuit is provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a read circuit of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a read of a conventional semiconductor memory. It is a circuit diagram showing a circuit. 2 ... Means for initializing data bus line, 4 ... Latch means, 6 ... Delay means, 8 ... Inverter, 10 ... P-channel MOSFET, 12 ... Output buffer, 22, 24, 26, 28, 30 ...
… P-channel MOSFET, 32,34,36 …… N-channel MOSF
ET, 38 ... Inverter.

Claims (1)

[Claims] 1. A means for initializing a data bus line during a period in which a first control signal that can take a first level and a second level is at a first level, and the first control signal is a first level. Level, the latch means for holding the data on the data bus line immediately before that, the delay means for delaying the first control signal in the same phase to generate the second control signal, and the normal output of the latch means. The inverting means for inverting the force, the output of the inverting means, and the inverting output of the latch means are electrically non-conducting while the second control signal is at the first level, and the second control is performed. Means for electrically conducting the signal during the period when the signal is at the second level, and the inverting output of the latch means is connected to the gate of the N-channel MOSFET, and the output of the inverting means is connected to the gate of the P-channel MOSFET. Then N
The source of the channel MOSFET is connected to the ground line, the source of the P channel MOSFET is connected to the power line, and the N channel MO is connected.
An output buffer for commonly connecting and outputting the drain of the SFET and the drain of the P-channel MOSFET, wherein the delay means delays the delay shorter than the delay time from the change of the first control signal to the output change of the latch means. A read circuit of a semiconductor memory, wherein the read circuit generates the second control signal.