JPH0824142B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0824142B2 JPH0824142B2 JP62324510A JP32451087A JPH0824142B2 JP H0824142 B2 JPH0824142 B2 JP H0824142B2 JP 62324510 A JP62324510 A JP 62324510A JP 32451087 A JP32451087 A JP 32451087A JP H0824142 B2 JPH0824142 B2 JP H0824142B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- layer
- wiring
- opening
- pattern size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims description 71
- 239000011229 interlayer Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000280 densification Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に配線層の段切れを
防止した多層配線型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a multilayer wiring type semiconductor device in which disconnection of wiring layers is prevented.
従来、この種の半導体装置では、第１層目と第２層目
の配線をつなぐ接続用の開口部（以降コンタクトホール
と称す）近傍の部分を製造時における位置等のずれを考
慮した広めのパターンサイズにしており、しかも第１層
及び第２層目の配線が同一のサイズになっている場合が
多い。Conventionally, in this type of semiconductor device, a portion in the vicinity of an opening (hereinafter referred to as a contact hole) for connection that connects the wirings of the first layer and the second layer is widened in consideration of a shift in position during manufacturing. In many cases, the pattern size is used and the wirings of the first and second layers are of the same size.
第３図（ａ）及び（ｂ）はそれぞれ従来の半導体装置
の第１の例の平面図及びＢ−Ｂ′線断面図である。FIGS. 3A and 3B are a plan view and a cross-sectional view taken along the line BB ′ of the first example of the conventional semiconductor device, respectively.
この従来例は、絶縁膜１上に第１層目の配線層２′を
設け、配線層２′上にコンタクトホールを開口した絶縁
膜３を設け、その上にコンタクトホールを通して配線層
２′と接続しかつパターンサイズが同一の第２層目の配
線層４′を設け、更にその上に絶縁膜５を介して第３層
目の配線層６′を設けた構造をしている。In this conventional example, a first wiring layer 2'is provided on an insulating film 1, an insulating film 3 having a contact hole opened is provided on the wiring layer 2 ', and a wiring layer 2'is formed through a contact hole. A second wiring layer 4'which is connected and has the same pattern size is provided, and a third wiring layer 6'is further provided on the second wiring layer 4'through an insulating film 5.
このようにコンタクトホール近傍の互いに接続した第
１及び第２層目の配線層２′及び４′のパターンサイズ
が同じになっていると、２層分の段差が出来てしまい、
その上に第３層目の配線層６′が配置されると段差の部
分のステップカバレージが非常に悪くなる。If the pattern sizes of the first and second wiring layers 2'and 4'connected to each other in the vicinity of the contact hole are the same, a step difference of two layers is generated,
If the third wiring layer 6'is arranged on top of this, the step coverage of the step portion becomes very poor.
第４図（ａ）及び（ｂ）はそれぞれ従来の半導体装置
の第２の例の平面図及びＣ−Ｃ′線断面図である。FIGS. 4A and 4B are a plan view and a sectional view taken along the line CC ′ of the second example of the conventional semiconductor device, respectively.
この例は、絶縁膜１上に第１層目の配線層に2a′を所
定の間隔ｌ′をおいて配置し、配線層2a′上にコンタク
トホールを開口した絶縁膜３を形成した後その上に第１
層目の配線層2a′よりもパターンサイズの小さい第２層
目の配線層4a′を設け、更にその上に絶縁膜５を介して
第３層目の配線層６′を設けた構造をしている。In this example, 2a 'are arranged on the insulating film 1 in the first wiring layer at a predetermined interval l', and after the insulating film 3 having contact holes formed on the wiring layer 2a 'is formed, First on top
The second wiring layer 4a 'having a smaller pattern size than the wiring layer 2a' of the second layer is provided, and the wiring layer 6'of the third layer is further provided on the second wiring layer 4a 'via the insulating film 5. ing.
この第２の例では、コンタクトホールの近傍の第１及
び第２層目の配線層2a′及び4a′のパターンサイズが違
うので、段差の部分の傾斜が緩やかになり第３層目の配
線層６′のステップカバレージは大幅に改善される。し
かし、コンタクトホールの近傍の第１層目の配線層2a′
のパターンサイズを大きくしたうえに互いに所定の間隔
ｌ′をおいて配置されるので、パターンサイズを大きく
した分だけ面積を余分に必要とし半導体装置の高密度化
を阻害することになる。In this second example, since the pattern sizes of the first and second wiring layers 2a 'and 4a' in the vicinity of the contact hole are different, the inclination of the step portion becomes gentle and the third wiring layer is formed. The 6'step coverage is greatly improved. However, the first wiring layer 2a ′ near the contact hole
Since the pattern size is increased and the patterns are arranged at a predetermined interval l ', an additional area is required for the increased pattern size, which hinders the densification of the semiconductor device.
第５図は従来の半導体装置の第３の例の平面図であ
る。FIG. 5 is a plan view of a third example of the conventional semiconductor device.
この第３の例では、行方向に配置した第１層目の配線
層2cの両脇（上下）に所定の間隔ｌ′をおいて配線層2
a′を配置し、コンタクトホールを通して第１層目の配
線層2a′と接続されかつ第１層目の配線層2cを跨いで列
方向に配置した第２層目の配線層4cにより互いに接続さ
れたパターンサイズの小さな配線層4a′を設けている。
これは、第２の例を応用した例である。In the third example, the wiring layer 2 is provided on both sides (upper and lower sides) of the first wiring layer 2c arranged in the row direction with a predetermined interval l '.
a'is arranged, is connected to the first wiring layer 2a 'through a contact hole, and is connected to each other by a second wiring layer 4c arranged in the column direction across the first wiring layer 2c. The wiring layer 4a 'having a small pattern size is provided.
This is an example in which the second example is applied.
上述した従来の半導体装置は、コンタクトホール近傍
の上下の配線パターンサイズが同じか単に上層より下層
の配線パターンサイズを大きくしてあるだけなので、段
差が大きくてステップカバレージが悪くなり半導体装置
の品質・信頼性が低下するという欠点あるいは段差の傾
斜が緩くステップカバレージが改善されたとしても面積
利用効率が悪化して半導体装置の高密度化が阻害される
という欠点がある。In the conventional semiconductor device described above, since the upper and lower wiring pattern sizes near the contact hole are the same or only the wiring pattern size of the lower layer is made larger than the upper layer, the step coverage is large and the step coverage is deteriorated. There is a drawback that the reliability is lowered, or even if the step coverage is improved due to a gradual slope of the step, the area utilization efficiency is deteriorated and the densification of the semiconductor device is hindered.
本発明の半導体装置は、層間絶縁膜を介して積層され
かつ前記層間絶縁膜に形成した接続用の開口部を通して
接続された第１層目の配線層と第２層目の配線層とを有
する多層配線型の半導体装置において、第１の開口部と
第２の開口部とが互いに隣接して形成され、前記第１の
開口部を通して接続される第２層目の配線層の前記第１
の開口部近傍のパターン寸法は第１層目の配線層の前記
第１の開口部近傍のパターン寸法より大きくなるように
設定され、前記第２の開口部を通して接続される第２層
目の配線層の前記第２の開口部近傍のパターン寸法は第
１層目の配線層の前記第２の開口部近傍のパターン寸法
より小さくなるように設定されている。A semiconductor device of the present invention has a first wiring layer and a second wiring layer which are stacked via an interlayer insulating film and are connected through an opening for connection formed in the interlayer insulating film. In a multi-layer wiring type semiconductor device, a first opening and a second opening are formed adjacent to each other, and the first wiring layer of the second wiring layer is connected through the first opening.
Is set to be larger than the pattern dimension in the vicinity of the opening of the first wiring layer of the first wiring layer, and the wiring of the second layer connected through the second opening is connected. The pattern size in the vicinity of the second opening of the layer is set to be smaller than the pattern size in the vicinity of the second opening of the first wiring layer.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実
施例の平面図及びＡ−Ａ′線断面図である。1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention, respectively.
この実施例は、絶縁膜１の上に第２の例と同様に所定
の間隔ｌ′をおいて第１層目をパターンサイズの大きな
配線層2aとパターンサイズの小さな配線層2bとを設け、
配線層2a及び2b上にコンタクトホールを開口した絶縁膜
３を設け、配線層2a及び2b上にそれぞれに接続した第２
層目のパターンサイズの小さな配線層4a及びパターンサ
イズの大きな配線層4bを設け、更にその上に絶縁膜５を
介して第３層目の配線層６を設けた構造をしている。In this embodiment, the first layer is provided with a wiring layer 2a having a large pattern size and a wiring layer 2b having a small pattern size on the insulating film 1 at a predetermined interval l ', as in the second example.
A second insulating film 3 having contact holes is formed on the wiring layers 2a and 2b and connected to the wiring layers 2a and 2b, respectively.
A wiring layer 4a having a small pattern size and a wiring layer 4b having a large pattern size are provided as a layer, and a third wiring layer 6 is further provided thereon with an insulating film 5 interposed therebetween.
この実施例では、コンタクトホール近傍の配線パター
ンサイズが第１層目が大きいものと第２層目の方が大き
いものとを隣に配置しているので、段差部の傾斜が緩く
なってステップカバレージが向上すると共に隣り同士の
間隔がパターンサイズの大きい第１層目の配線層2aと第
２層目の配線層4bとの水平方向の間隔ｌとなり、これは
間隔ｌ′よりも狭いので面積利用効率は低下せず高密度
化の妨げにならない。In this embodiment, since the wiring pattern size in the vicinity of the contact hole is larger next to the first layer and larger in the second layer, the slope of the step portion is gentle and the step coverage is small. And the space between adjacent wirings becomes a horizontal space l between the first wiring layer 2a and the second wiring layer 4b having a large pattern size, which is smaller than the space l ', and therefore the area is used. Efficiency does not decrease and does not hinder high density.
第２図は本発明の第２の実施例の平面図である。 FIG. 2 is a plan view of a second embodiment of the present invention.
この実施例は第１の実施例を応用して、第３の従来例
と同様のパターンを実現したものであり、第１層目のパ
ターンサイズの方が大きくなる部分の配線層2a及び4aの
重層ブロックと第２層目のパターンサイズの方が大きな
部分の配線層2b及び4bの重層ブロックとが間隔ｌで交互
に配置されている。This embodiment realizes a pattern similar to that of the third conventional example by applying the first embodiment, and the wiring layers 2a and 4a of the portions where the pattern size of the first layer is larger The multi-layer blocks and the multi-layer blocks of the wiring layers 2b and 4b in which the pattern size of the second layer is larger are alternately arranged at intervals l.
この実施例では、第３の従来例に比べて、面積が12.5
％程度縮小される。In this embodiment, the area is 12.5 as compared with the third conventional example.
It is reduced by about%.
以上、本発明の実施例では、パターンサイズを変えた
もののみ説明したが、この他に本発明では、その他に上
下の配線パターンの位置をずらしたり、あるいはパター
ンの形状を変えたりして同様の効果を得るものでも良
い。As described above, in the embodiment of the present invention, only the one in which the pattern size is changed has been described, but in addition to this, in the present invention, the position of the upper and lower wiring patterns may be shifted or the shape of the pattern may be changed. You may get an effect.
以上説明した様に本発明は、コンタクトホール近傍の
互いに接続された上下の配線パターンの大きさや形等の
組合せを隣り同士変えることによって、段差の映写を緩
和してステップカバレージを向上すると共に配線の間隔
を狭めて面積利用効率を改善し、より一層高密度化した
品質・信頼性の高い半導体装置を提供できるという効果
がある。As described above, according to the present invention, by changing the combination of the sizes and shapes of the upper and lower wiring patterns connected to each other in the vicinity of the contact hole, the projection of the step is alleviated to improve the step coverage and the wiring can be formed. There is an effect that a space is narrowed to improve the area utilization efficiency, and a semiconductor device with higher quality and higher reliability can be provided.
第１図（ａ）及び（ｂ）はそれぞれ本発明の第１の実施
例の平面図及びＡ−Ａ′線断面図、第２図は本発明の第
２の実施例の平面図、第３図及び第４図（ａ），（ｂ）
はそれぞれ従来の半導体装置の第１及び第２の例の平面
図,B−Ｂ′及びＣ−Ｃ′線断面図、第５図は従来の半導
体装置の第３の例の平面図である。 １……絶縁膜、２′,2a,2a′,2b,2c……配線層、３……
絶縁膜、４′,4a,4a′,4b,4c……配線層、５……絶縁
膜、6,6′……配線層。1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention, and FIG. 2 is a plan view of the second embodiment of the present invention. Figure and Figure 4 (a), (b)
FIGS. 5A and 5B are plan views of the first and second examples of the conventional semiconductor device, a cross-sectional view taken along the line BB ′ and CC ′, and FIG. 5 is a plan view of the third example of the conventional semiconductor device. 1 ... Insulating film, 2 ', 2a, 2a', 2b, 2c ... Wiring layer, 3 ...
Insulation film, 4 ', 4a, 4a', 4b, 4c ... Wiring layer, 5 ... Insulation film, 6,6 '... Wiring layer.
Claims (1)
絶縁膜に形成した接続用の開口部を通して接続された第
１層目の配線層と第２層目の配線層とを有する多層配線
型の半導体装置において、第１の開口部と第２の開口部
とが互いに隣接して形成され、前記第１の開口部を通し
て接続される第２層目の配線層の前記第１の開口部近傍
のパターン寸法は第１層目の配線層の前記第１の開口部
近傍のパターン寸法より大きくなるように設定され、前
記第２の開口部を通して接続される第２層目の配線層の
前記第２の開口部近傍のパターン寸法は第１層目の配線
層の前記第２の開口部近傍のパターン寸法より小さくな
るように設定されていることを特徴とする半導体装置。1. A multi-layer wiring having a first wiring layer and a second wiring layer which are stacked with an interlayer insulating film interposed therebetween and are connected through a connection opening formed in the interlayer insulating film. Type semiconductor device, the first opening and the second opening are formed adjacent to each other, and the first opening of the second wiring layer is connected through the first opening. The pattern size in the vicinity is set to be larger than the pattern size in the vicinity of the first opening of the first wiring layer, and the pattern size of the second wiring layer connected through the second opening is the same. A semiconductor device, wherein a pattern size in the vicinity of the second opening is set to be smaller than a pattern size in the vicinity of the second opening of the first wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62324510A JPH0824142B2 (en) | 1987-12-21 | 1987-12-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62324510A JPH0824142B2 (en) | 1987-12-21 | 1987-12-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01165144A JPH01165144A (en) | 1989-06-29 |
| JPH0824142B2 true JPH0824142B2 (en) | 1996-03-06 |
Family
ID=18166606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62324510A Expired - Lifetime JPH0824142B2 (en) | 1987-12-21 | 1987-12-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0824142B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52149990A (en) * | 1976-06-09 | 1977-12-13 | Hitachi Ltd | Production of multilayer wirings |
| JPS6489468A (en) * | 1987-09-30 | 1989-04-03 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-12-21 JP JP62324510A patent/JPH0824142B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01165144A (en) | 1989-06-29 |
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