JPH0824167B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for achieving high integration of memory elements including transistors and capacitors.

[Prior Art] FIG. 15 is a block diagram showing an example of a configuration of a general RAM. Referring to the figure, a plurality of word lines and a plurality of bit lines are arranged in memory cell array 101 so as to intersect with each other, and memory cells are provided at respective intersections of these word lines and bit lines. Memory cell selection is X
1 selected by the address buffer / decoder 102
This is performed based on the intersection of one word line and one bit line selected by the Y address buffer / decoder 103. The data of the selected memory cell is written,
Alternatively, the data stored in the memory cell may be read, but the instruction to write / read this data is read / write.
This is performed by a read / write control signal (R / W) applied to control circuit 104. When writing data, input data (Di
n) is input to the selected memory cell via the R / W control circuit 104. On the other hand, at the time of reading data, the data stored in the selected memory cell is detected and amplified by the sense amplifier 105, and the data output buffer 106
Is output to the outside as output data (Dout) via.

FIG. 16 is an equivalent circuit diagram of the dynamic memory cell shown for explaining the write / read operation of the memory cell.

Referring to the figure, the dynamic memory cell is composed of a pair of field effect transistor 108 and capacitor 109, the gate electrode of field effect transistor 108 is connected to word line 110 to capacitor 109, and the source / drain electrode is a bit line. Connect to 107 respectively. Word line 1 when writing data
When a predetermined potential is applied to 10, the field effect transistor 108 becomes conductive, so that the charge applied to the bit line 107 is stored in the capacitor 109. On the other hand, at the time of reading data, the electric charge stored in the capacitor 109 is taken out through the bit line 107 because the field effect transistor 108 becomes conductive by applying a predetermined potential to the word line 110.

Figure 17 shows a dynamic MOSRMA with folded bit lines.
It is a figure which shows the plane arrangement of the memory part of (random access memory), and FIG. 18 is a XVIII-XVIII sectional view of FIG.

 The configuration will be described below with reference to both drawings.

The RAM is a groove 1 formed at a predetermined position on the main surface of the semiconductor substrate 3.
It is composed of a pair of MOS transistors and a capacitor formed in the active region 112 including the inner surface of the trench 18 in the bottom of 8 isolated from the adjacent element by the isolation oxide film 20. The MOS transistor includes impurity regions 42 and 44 which are source or drain regions formed on the main surface of the semiconductor substrate 3 and impurity regions 4 and 4.
2 and the impurity region 44, and a word line 9 serving as a gate electrode formed through the oxide film 24. The capacitor includes an impurity region 46a connected to the impurity region 44 and an impurity layer 46b formed on the sidewall of the trench 18,
The cell plate 6 is formed on the impurity layers 46a and 46b and via the capacitor insulating film 7 including the isolation oxide film 20 at the bottom of the trench 18. An interlayer insulating film 48 made of an oxide film is formed so as to cover the transistor and the capacitor, and the bit line 1 formed on the interlayer insulating film 48 has contact holes 12 formed in the interlayer insulating film 48.
Is connected to the impurity region 42 through.

In the RAM configured as described above, when the word line 9 is selected and a predetermined potential is applied, the region between the impurity regions 42 and 44 therebelow is brought into conduction to perform the read / write operation. Of.

19A to 19G are schematic process sectional views showing a method for manufacturing a conventional device.

 This manufacturing method will be described below with reference to the drawings.

First, the conductive type ions opposite to the semiconductor substrate 3 are implanted into the main surface of the semiconductor substrate 3, and a heat treatment is performed to form an impurity layer 46a made of a diffusion layer of the conductive type ions opposite to the semiconductor substrate 3 in a predetermined region. (See Figure 19A).

Next, an oxide film 50 is formed on the entire main surface of the semiconductor substrate 3,
The semiconductor substrate 3 including the oxide film 50 on a part of the impurity layer 46a
Then, the trench 18 is formed to a predetermined depth, and a nitride film 52 is deposited on the entire surface including the inner surface of the trench 18, and then the nitride film 52 is removed only on the bottom surface of the trench 18 (see FIG. 19B).

After implanting the same conductivity type ions as the semiconductor substrate 3 into the bottom surface of the groove 18, the bottom surface is thermally oxidized to form an impurity layer 22 and a thick isolation oxide film 20 made of a diffusion layer of the same conductivity type ions as the semiconductor substrate 3. (See Figure 19C).

After removing the nitride film 52, the conductive type ions opposite to the semiconductor substrate 3 are implanted into the side wall of the groove 18 by oblique ion implantation or the like, and heat treatment is performed to form impurities of the conductive type ion diffusion layer opposite to the semiconductor substrate 3. Form layer 46b (see Figure 19D).

The oxide film 50 is removed, and the capacitor insulating film 7 is formed on the bottom and side walls of the groove 18 and a part of the main surface of the semiconductor substrate 3 by CV.
It is formed by the D method or thermal oxidation method. An electrode material such as polysilicon containing impurities is deposited on the entire surface including the inside of the groove 18, an oxide film is further deposited on the entire surface including the inside of the groove 18, and the oxide film is etched back by anisotropic etching. As a result, the oxide film 54 is buried in the trench 18 on the polysilicon and planarized. At this time, polysilicon is exposed in the flat portion. Next, photolithography and etching are performed to form a cell plate 6 having a flat portion of a predetermined shape from polysilicon (see FIG. 19E).

An oxide film 24 serving as a transfer gate insulating film is formed by thermal oxidation or the like, polysilicon and refractory metal silicide are sequentially laminated on the entire surface, and photoengraving and etching are performed to form the word line 9. Impurity regions made of a diffusion layer of conductive ions opposite to the semiconductor substrate 3 are formed by implanting conductive type ions opposite to the semiconductor substrate 3 into the exposed main surface of the semiconductor substrate 3 and performing heat treatment.
42 and 44 are formed (see FIG. 19F).

CV over the entire main surface of the semiconductor substrate 3 including the word lines 9
An oxide film is deposited by the D method to form the interlayer insulating film 48, and a contact hole 49 reaching the impurity region 42 is formed by etching a predetermined portion of the interlayer insulating film 48 using a photolithography process. Finally, aluminum, refractory metal silicide, refractory metal, or the like is deposited over the entire surface including the inside of the contact hole 49, and patterned to form the bit line 1 that contacts the impurity region 42 and the contact 12. (See Figure 19G).

[Problems to be Solved by the Invention] Since the conventional semiconductor memory device is configured as described above, it has been attempted to achieve high integration by adopting a grooved type capacitor portion. In other parts, the factors that hinder high density and high integration of the device still remained. That is, first, the word line 9 and the contact 12 must be formed with a certain distance. The reason is that when the bit line 1 is connected to the source or drain region of the transistor formed on the main surface of the semiconductor substrate 3 via the contact 12, the connection around the contact 12 is made to be an ohmic low resistance contact. It is necessary to form the impurity region 42 by ion implantation on the main surface of the semiconductor substrate 3. However, it is necessary to secure a distance between the word line 9 and the contact 12 in consideration of the diffusion so that the impurity region 42 does not reach the transfer gate region below the word line 9 by the diffusion of the implanted ions by the heat treatment. When forming a contact hole 49 in the inter-layer insulation film 48 using a photolithography process, the mask displacement that causes the positioning of the contact hole 49, that is, the overlay accuracy of the mask becomes a problem. There is no choice but to set the contact position at a position that allows for accuracy. Therefore, in the structure of the conventional device, the distance between the word line 9 and the contact 12 must be increased more than necessary.

Further, even if the conventional device can shorten the unnecessary distance in the above, since the contact portion is basically on the plane portion of the main surface of the semiconductor substrate, its occupied area must be at least ensured. In other words, the limit of high integration and high density of the device was exhibited.

The present invention has been made to solve the above problems, and provides a semiconductor memory device which can improve the connection between the bit line and the transistor and contribute to high integration and high density of elements. With the goal.

[Means for Solving Problems] A semiconductor memory device according to the present invention is a semiconductor memory device including a bit line, a word line intersecting with the bit line, a transistor, and a capacitor connected to the transistor. A semiconductor substrate having a main surface and having a first groove formed in the main surface, the first groove having a sidewall, and further being formed on the sidewall of the first groove and connected to the transistor. The first impurity region is formed, and the bit line is formed inside the first groove and at a position in contact with the first impurity region.

A semiconductor memory device according to another invention of the present invention is
A semiconductor memory device including a bit line, a word line intersecting with the bit line, a transistor, and a capacitor connected to the transistor, the semiconductor substrate having a main surface,
A first insulating film formed on the main surface of the semiconductor substrate;
A semiconductor layer having a main surface and having a first groove reaching the first insulating film formed on the main surface, the first groove having a sidewall, and A first impurity region formed on a sidewall of the first groove and connected to the transistor is provided, and the bit line is formed inside the first groove and at a position in contact with the first impurity region. is there.

A semiconductor memory device according to still another invention of the present invention is
A semiconductor substrate having a main surface and having a first groove formed in the main surface, the first groove having a side wall, and further including a side wall of the first groove, A first impurity region partially formed and a first trench formed inside the first trench;
And a bit line in contact with the impurity region of.

[Operation] In the present invention, since the groove is formed in the main surface of the semiconductor substrate and the impurity region connected to the transistor and the bit line formed inside the groove are in contact with each other on the side wall of the groove, the contact hole is not necessary, The line portion can be flattened, and the margin of the overlapping region of the word line and the bit line is increased.

Further, according to another invention of the present invention, a semiconductor layer is formed on the main surface of a semiconductor substrate with an insulating film interposed, and an impurity region connected to a transistor is formed on a sidewall of a groove reaching the insulating film provided in the semiconductor layer. Since the bit line formed inside the groove is in contact with the bit line, a contact hole is not required, the bit line can be flattened, and the margin of the overlapping region of the word line and the bit line is increased.

In still another aspect of the present invention, a groove is formed on the main surface of the semiconductor substrate, and the impurity region formed on the semiconductor substrate and the bit line formed inside the groove are in contact with each other on the side wall of the groove, It is possible to form a semiconductor memory device including a bit line that is electrically connected to the impurity region below the main surface of the semiconductor substrate.

[Embodiment] FIG. 1 is a diagram showing a planar layout showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line II-II of FIG. 1, and FIG. 3 is FIG. III-III sectional view of FIG. 4, and FIG. 4 is a IV-IV sectional view of FIG. 1.

This configuration will be described below with reference to FIGS. 1 to 4.

Grooves 26 and grooves are formed on the main surface of the semiconductor substrate 3 made of a silicon substrate
18 is formed. Although the groove 26 is formed in series in the vertical direction in FIG. 1, the groove 18 is different in functional parts formed around the groove, and the structure of the groove 18 is alternately repeated in the series of grooves in the vertical direction. It has been configured. Bit line 1 made of polysilicon or the like is formed on the inner surface of groove 26, and isolation oxide films 14 and 10b are formed on the bottom and side walls of groove 26, respectively.
Impurity layers 16 and 8b are formed in regions of the semiconductor substrate 3 that are in contact with the isolation oxide films 14 and 10b, respectively.
At the same time, the elements are electrically separated. On the other hand, impurity layers 2 and 4 are formed on the other side wall of the groove 26 and a part of the side wall of the left side groove 18 to form the source or drain region of the transistor. A polysilicon layer 5 is formed on both sides of the sidewall of the left trench 18, and the inside of the left trench 18 sandwiched by the polysilicon layer 5 is filled with a cell plate 6 made of polysilicon via a capacitor insulating film 7. It The polysilicon layer 5, the capacitor insulating film 7 and the cell plate 6 on one side constitute one capacitor, and the bottom of the left side groove 18 is separated from the two capacitors formed in the left side groove 18 by An isolation oxide film 20 is formed. An impurity layer 22 is further formed in the region below the isolation oxide film 20 to complete element isolation. The groove 18 on the right side has a structure for separating the groove 18 on the left side adjacent to each other in the vertical direction in FIG. 1, that is, the adjacent capacitor and the transistor portion connected to the capacitor. A thick isolation oxide film 10 is formed inside the groove 18 on the right side so as to sandwich the cell plate 6, and a sidewall of the groove 18 on the right side where the isolation oxide film 10 is formed,
The impurity layer 8a is formed to complete element isolation by the isolation oxide film 10. An isolation oxide film 20 is also formed on the bottom of the right trench 18, and an impurity layer 22 is further formed in the lower region thereof to perform element isolation on the bottom of the right trench 18. Impurity layer 8a and isolation oxide film 10a are connected to impurity layer 8b and isolation oxide film 10b on the side wall of trench 26 in the plane portion of the main surface of semiconductor substrate 3, respectively. Groove 26
A thick oxide film is formed on the bit line 1 formed inside, the cell plate 6 formed inside the left groove 18 and the cell plate 6 formed inside the right groove 18, respectively.
Further, a thin oxide film 24 is formed on the portion where the main surface of the semiconductor substrate 3 is exposed. On these oxide films, a word line 9 made of polysilicon is patterned and formed above each transistor and each capacitor. Here, the semiconductor substrate 3 sandwiched between the impurity layer 2 and the impurity layer 4
Region becomes the channel region, the oxide film 24 on the channel region functions as the gate insulating film of the transistor, and the portion of the word line 9 above it functions as the gate electrode.

The operation of the dynamic MOSRAM configured as above will be briefly described below.

When a predetermined potential is applied to the selected word line 9 during writing, the impurity layers 2, 4 on the main surface of the semiconductor substrate 3 are
The conductivity type of the region sandwiched by is inverted to bring the impurity layers 2 and 4 into conduction. Therefore, the potential applied to the bit line 1 is applied to the impurity layer 2, the inversion region, and the impurity layer 4 via the contact 12.
It is stored in the capacitor formed of the polysilicon layer 5, the capacitor insulating film 7 and the cell plate 6 through the transistor portion formed of.

On the other hand, at the time of reading, a predetermined potential is applied to the similarly selected word line 9, and the potential stored in the capacitor is applied to the bit line 1 through the transistor portion and the contact 12 to detect this potential. It is a thing.

FIG. 5 is a diagram showing a planar layout showing a second embodiment of the present invention, and FIG. 6 is a sectional view taken along line VI-VI of FIG.

This configuration will be described below with reference to FIGS. 5 and 6.

The basic structure is the same as that shown in FIGS. 1 and 2, but the difference lies in the cross-sectional shape of the conductor forming the bit line 1.

In this embodiment, the inside of the groove 26 is completely filled with a conductor, and a large cross-sectional area can be obtained, which contributes to reduction of the wiring resistance of the bit line, which is advantageous in operating characteristics.

In addition, III-III direction and IV- shown in FIG.
The cross section in the IV direction is almost the same as that shown in FIGS. 3 and 4.

7A to 7F are schematic process sectional views showing the manufacturing method of the first embodiment of the present invention.

 This manufacturing method will be described below with reference to the drawings.

An oxide film 28 is formed on the entire main surface of the semiconductor substrate 3 by thermal oxidation or a CVD method. The oxide film 28 is selectively anisotropically etched using a resist (not shown) that has been photoengraved as a mask, and then the resist is removed. By using the oxide film 28 selectively etched as a mask, the semiconductor substrate 3 is anisotropically etched to a predetermined depth to form a groove.
Form 26 (see Figure 7A).

Next, the resist 30 covers a large amount of the entire main surface of the semiconductor substrate 3 including the inside of the groove 26. This is used to selectively remove only a predetermined resist in the groove 26 using a photolithography technique.
Expose a part of.

Semiconductor substrate 3 exposed using this resist 30 as a mask
Is further anisotropically etched to form a deeper groove 18 (see FIG. 7B).

After removing the resist 30, a nitride film 32 is formed on the entire surface of the semiconductor substrate.
Is deposited. The nitride film 32 on the bottoms of the trenches 18 and 26 is removed by etching back by anisotropic etching, and the same conductivity type ions as the semiconductor substrate 3 are formed on the bottoms of the trenches 18 and 26 by a method such as ion implantation. Inject. Photolithography using a three-layer resist is performed to form contact grooves.
Nitride film only on one sidewall of 26 and on the left side trench 18 which will be the capacitor part
With the remaining 32, the other part of the nitride film 32 is removed by isotropic etching. Further, the exposed oxide film 28 is removed, and the same conductive type ions as those of the semiconductor substrate 3 are implanted into the sidewalls and flat portions of the trenches 18 and 26 other than the contact portion and the capacitor portion by a method such as oblique ion implantation (first (See Figure 7C).

Groove the element isolation oxide films 20, 14 and 10 by thermal oxidation.
It is formed on the bottom surface portion of the groove 18 and the groove 26, the side wall portion of the groove portion 18 on the right side, and the side wall portion on one side of the groove 26. At this time, at the same time, the impurity layers 8a, 16 and 22 of the same conductivity type ion as the semiconductor substrate 3 are formed on the semiconductor substrate 1 side of the element isolation oxide films 10, 14 and 20.
Are formed by thermal diffusion. Subsequently, after removing the remaining nitride film 32, conductive type ions opposite to the semiconductor substrate 3 are obliquely implanted by a method such as oblique ion implantation, and a heat treatment is performed to remove one of the upper side wall of the left trench 18 and one of the trenches 26. Impurity layers 2 and 4 of conductive type ions opposite to the semiconductor substrate 3 are formed on the side wall portions, and the remaining oxide film 28 is removed (see FIG. 7D).

A polysilicon material is deposited on the entire surface of the semiconductor substrate 3 including the insides of the grooves 18 and 26, and a resist is applied on the polysilicon material to planarize the material. By anisotropically etching back, the resist and the polysilicon-based material are etched at the same time, the polysilicon-based material in the planar portion is removed, and the polysilicon layer 1 and the capacitor of the bit line are formed from the same polysilicon-based material. At the same time, a polysilicon layer 5 which will be one electrode is formed. When this etch back is completed, the contact between the impurity layer 2 and the polysilicon layer 1 is formed in the side wall of the groove 26 in a self-aligned manner. Further, by performing photolithography and etching with a three-layer resist, the element isolation oxide film 10 on the sidewall of the groove 18 on the right side is formed.
Only the upper polysilicon material is removed, and the polysilicon layer 5 and the inside of the groove 18 on the left side are hollowed out. An oxide film 7 serving as a capacitor gate insulating film is formed on the polysilicon layer 5 by a method such as thermal oxidation or a CVD method. Further, a polysilicon material containing conductive impurities is deposited on the entire surface including the inside of the groove 18, a resist is applied, and the resist is flattened and then etched back by anisotropic etching. As a result, the resist and the polysilicon-based material containing the conductive impurities are simultaneously etched, and the polysilicon-based material on the flat surface is removed, so that the trench
A polysilicon layer 6 to be the cell plate of the capacitor embedded inside 18 is formed (see FIG. 7E).

When the oxide film 24 serving as a transfer gate insulating film is formed on the main surface of the semiconductor substrate 3 sandwiched by the impurity layers 2 and 4 by thermal oxidation, at the same time, the polysilicon layers 1, 5 and 6 are also thermally oxidized. A thick oxide film 36 is also formed. Finally, a single layer of polysilicon, two layers of refractory metal silicide and polysilicon,
Alternatively, a word line 9 is formed by depositing a wiring material composed of a high melting point metal single layer and patterning it by performing photoengraving and etching. Since the bit line 1 is buried in the groove 26 and the word line 9 is formed on the groove 26, it is not necessary to consider a considerable distance between the contact hole and the word line unlike the conventional device. Also, since the contact is not on the plane but on the side wall of the groove, the contact area can be earned in the vertical direction, and the high integration of the semiconductor device,
The structure is suitable for high density (see Fig. 7F).

FIG. 8 is a diagram showing a planar layout showing a first embodiment of another invention of the present invention, and FIG. 9 is a diagram of FIG.
10 is a sectional view taken along line IX, FIG. 10 is a sectional view taken along line XX of FIG. 8, and FIG. 11 is a sectional view taken along line XI-XI of FIG.

This configuration will be described below with reference to FIGS. 8 to 11.

The overall structure is basically the same as that shown in FIGS. 1 to 4, but in the present embodiment, the semiconductor substrate 3 is not directly provided with a groove but a semiconductor is formed on the main surface via an oxide film 38. The layer 40 is formed, and the groove 26a and the groove 18 are formed from the main surface of the semiconductor layer 40. Therefore, an oxide film or an impurity layer for element isolation is not required on the bottom surface of the groove 26a, and the oxide film 38 instead isolates it from an adjacent element.

FIG. 12 is a view showing a planar layout showing a second embodiment of another invention of the present invention, and FIG. 13 is a view of XIII of FIG.
It is a -XIII sectional view.

This configuration will be described below with reference to FIGS. 12 and 13.

The basic structure is the same as that shown in FIGS. 8 and 9, but the difference lies in the cross-sectional shape of the conductor forming the bit line 1.

In this embodiment, the inside of the groove 26a is completely filled with a conductor, and a large cross-sectional area can be obtained, which contributes to reduction of the wiring resistance of the bit line, which is advantageous in operating characteristics. .

Further, the sectional views in the XX direction and the XI-XI direction shown in FIG. 12 are substantially the same as those shown in FIGS. 10 and 11.

Also, the manufacturing methods of the first and second embodiments basically follow the manufacturing steps of FIGS. 7A to 7F. Specifically, before forming the process of FIG. 7A, an oxide film 38 is formed on the main surface of the semiconductor substrate 3, a semiconductor layer 40 is formed on the oxide film 38, and then an oxide film 28 is formed on the semiconductor layer 40. To form. Subsequently, by forming the groove 26 to a depth reaching the oxide film 38, the manufacturing steps in FIGS. 7B to 7F can be similarly applied. At this time, since it is not necessary to form an isolation oxide film or an impurity layer on the bottom surface of the groove 26a, the groove 26a may be appropriately used as a mask with a resist or the like.

In each of the embodiments of the above invention and other inventions, a polysilicon material is used as the bit line material, but other materials such as a two-layer structure of refractory metal silicide and polysilicon or refractory metal are used. It goes without saying that any conductor such as the above may be used.

FIG. 14 is a schematic sectional view showing still another embodiment of the present invention.

 Hereinafter, this configuration will be described with reference to the drawings.

Two grooves are formed on the main surface of the semiconductor substrate 3 made of a silicon substrate.
42a, 42b are formed, one side wall of the grooves 42a, 42b and two grooves
An impurity layer 46 is formed on the main surface of the semiconductor substrate 3 in the region sandwiched by 42a and 42b. The inside of the grooves 42a, 42b are filled with a conductive material such as polysilicon to form wirings 44a, 44b,
Contacts 48a and 48b are formed on the sidewalls of the grooves 42a and 42b to form an impurity layer 46.
Is in contact with. Therefore, the wiring 44a and the wiring 44b are electrically connected via the impurity layer 46 in a state of being embedded in the semiconductor substrate 3,
Since there is no protrusion on the semiconductor substrate 3,
An insulating film such as an oxide film can be formed on top of this and other components can be stacked on top of it, which is particularly useful for a semiconductor memory device aiming at high integration. That is, in this embodiment, the wiring structure can be applied not only to the memory cell portion of the semiconductor memory device but also to the peripheral circuit and the logic circuit, and the wiring structure is less likely to cause disconnection of wiring or contact failure. It becomes possible.

Although the sidewalls of the groove to be the contact portion are perpendicular to the main surface of the semiconductor substrate in the embodiments for all the inventions described above, they may not necessarily be vertical. Or an acute angle, the same effect can be obtained with the same effect.

As described above, according to the present invention, the bit line is formed in the groove provided in the semiconductor substrate and the side wall of the bit line is in contact with the impurity region connected to the transistor. Therefore, the present invention only contributes to the degree of integration of the device. In addition, a highly reliable semiconductor memory device with few contact defects can be formed. Further, since the bit line is buried inside the groove, the bit line portion can be flattened and the margin of the overlapping region of the word line and the bit line is increased.

As described above, according to another invention of the present invention, a groove is formed in a semiconductor layer formed on a semiconductor substrate with an insulating film interposed therebetween, and an impurity that connects to a bit line and a transistor inside the groove is formed via a sidewall of the groove. Since we will make contact with the area,
It is possible to form a highly reliable semiconductor memory device that not only contributes to the degree of integration of the elements but also has few contact failures and ensures reliable insulation separation between the elements. Further, since the bit line is buried inside the groove, the bit line portion is flattened and the margin of the overlapping region of the word line and the bit line is increased.

As described above, still another invention of the present invention forms a bit line in a groove formed in a semiconductor substrate and makes contact with an impurity region on the side wall thereof, so that there is no protrusion on the semiconductor substrate. Since another component can be formed, a semiconductor memory device that can contribute to the degree of integration of elements can be formed.

[Brief description of drawings]

1 is a diagram showing a planar layout showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line II-II of FIG. 1, FIG. 3 is a sectional view taken along line III-III of FIG. FIG. 4 is a sectional view taken along the line IV-IV in FIG. 1, FIG. 5 is a plan layout showing a second embodiment of the present invention, and FIG. 6 is a sectional view taken along the line VI-VI in FIG.
FIG. 7 to FIG. 7F are schematic process sectional views showing the manufacturing method of the first embodiment of the present invention, and FIG. 8 is a plan layout showing the first embodiment of another invention of the present invention. 9 is the eighth
Figure IX-IX cross section, Figure 10 is XX cross section of Figure 8,
FIG. 11 is a sectional view taken along line XI-XI in FIG. 8, and FIG. 12 is a diagram showing a planar layout showing a second embodiment of another invention of the present invention.
FIG. 13 is a sectional view taken along the line XIII-XIII in FIG. 12, FIG. 14 is a schematic sectional view showing an embodiment of yet another invention of the present invention, and FIG. 15 is a block diagram showing an example of the configuration of a general RAM. , FIG. 16 is an equivalent circuit diagram of a dynamic memory cell shown for explaining the writing / reading operation of the memory cell, and FIG. 17 is a diagram showing a plan layout of a memory portion of a dynamic MOS RAM having a folded bit line configuration. 18 is a sectional view taken along the line XVIII-XVIII in FIG. 17,
19A to 19G are schematic process sectional views showing a method for manufacturing a conventional device. In the figure, 1 is a bit line, 2 is an impurity layer, 3 is a semiconductor substrate, 4 is an impurity layer, 5 is a polysilicon layer, 6 is a cell plate, 7 is a capacitor insulating film, 8a and 8b are impurity layers, 9
Is a word line, 10a and 10b are isolation oxide films, 12 is a contact, 1
4 is an isolation oxide film, 16 is an impurity layer, 20 is an isolation oxide film, 22 is an impurity layer, 24 is an oxide film, 26 is a groove, 42a and 42b are grooves, and 44a and 44b.
Is a wiring, 46 is an impurity layer, and 48a and 48b are contacts. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/04 29/41 7735-4M H01L 27/10 681 B 27/04 C 29/44 C

Claims (27)

[Claims] 1. A semiconductor memory device including a bit line, a word line intersecting with the bit line, a transistor, and a capacitor connected to the transistor, the semiconductor memory device having a main surface and having the main surface. A semiconductor substrate having a formed first trench is provided, wherein the first trench has a sidewall, and a first impurity region formed on the sidewall of the first trench and connected to the transistor is formed. The semiconductor memory device according to claim 1, wherein the bit line is formed inside the first groove and at a position in contact with the first impurity region. 2. The transistor has a source region and a drain region, and the source and drain regions are
Formed on the main surface of the semiconductor substrate, and the first impurity region is connected to the source or drain region,
The semiconductor memory device according to claim 1. 3. A second groove having a side wall is further formed on the main surface of the semiconductor substrate, and the capacitor is formed inside the second groove. Semiconductor memory device. 4. The capacitor includes a first conductor formed on the sidewall of the second trench, a first insulating film formed on the first conductor, and the first conductor. And a second conductor formed on the insulating film of claim 3.
The semiconductor memory device according to the item. 5. A second impurity region is formed in a part of a side wall of the second trench on which the first conductor is formed, and the second impurity region constitutes the transistor. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is connected to the source or drain region. 6. The transistor according to claim 5, wherein the transistor has a channel region, and the channel region is a region of the main surface of the semiconductor substrate sandwiched by the source and drain regions. Semiconductor memory device. 7. A second insulating film is further formed on the main surface of the semiconductor substrate including the first and second trenches, and the word line is formed on the second insulating film. The semiconductor memory device according to claim 6, wherein 8. The transistor has a gate electrode and a gate insulating film, the gate electrode is a part of the word line above the channel region, and the gate insulating film is the second region above the channel region. 8. The semiconductor memory device according to claim 7, which is a part of the insulating film of FIG. 9. The semiconductor memory device according to claim 1, wherein the inside of the first groove is filled with the bit line. 10. The first groove has a bottom portion, and the bottom portion and a side wall of the first groove opposite to a side wall of the side wall of the first groove where the first impurity region is formed. 10. The semiconductor memory device according to claim 1, wherein the insulator 3 is formed. 11. A third impurity region is further formed in a region of the semiconductor substrate below the third insulator formed at the bottom of the first groove, according to claim 10.
The semiconductor memory device according to the item. 12. The method according to claim 10, wherein a fourth impurity region is further formed in a region of the semiconductor substrate which is in contact with the third insulator formed on the sidewall of the first groove. 11. The semiconductor memory device according to item 11. 13. A semiconductor memory device including a bit line, a word line intersecting with the bit line, a transistor, and a capacitor connected to the transistor, the semiconductor substrate having a main surface, and the semiconductor substrate. A first insulating film formed on the main surface, and a first insulating film formed on the first insulating film and having a main surface and reaching the first insulating film formed on the main surface. A semiconductor layer having a trench, the first trench has a sidewall, and a first impurity region formed on the sidewall of the first trench and connected to the transistor, the bit The line is formed inside the first groove and at a position in contact with the first impurity region. 14. The transistor has a source region and a drain region, the source and drain regions are formed on the main surface of the semiconductor layer, and the first impurity region is connected to the source or drain region. Will be
The semiconductor memory device according to claim 13. 15. A second groove, which reaches the inside of the semiconductor substrate and has a side wall, is formed on the main surface of the semiconductor layer, and the capacitor is formed inside the second groove. A semiconductor memory device according to claim 14. 16. The capacitor includes a first conductor formed on the sidewall of the second groove, a second insulating film formed on the first conductor, and the second conductor. And a second conductor formed on the insulating film of
15. The semiconductor memory device according to item 15. 17. A second impurity region is formed in a region of the semiconductor layer, which is a part of a sidewall of the second groove on which the first conductor is formed, and a second impurity region is formed. 17. The semiconductor memory device according to claim 16, wherein said impurity region is connected to said source or drain region forming said transistor. 18. The transistor has a channel region, and the channel region is a region of the main surface of the semiconductor layer sandwiched between the source and drain regions.
A semiconductor memory device according to claim 17. 19. A third insulating film is further formed on the main surface of the semiconductor layer including the first and second trenches, and the word line is formed on the third insulating film. 19. A semiconductor memory device according to claim 18. 20. The transistor has a gate electrode and a gate insulating film, the gate electrode is a part of the word line above the channel region, and the gate insulating film is the third region above the channel region. 20. The semiconductor memory device according to claim 19, which is a part of the insulating film of. 21. The semiconductor memory device according to claim 13, wherein the inside of the first groove is filled with the bit line. 22. A fourth insulating film is further formed on the side wall of the first groove, the side wall being opposite to the side wall on which the first impurity region is formed. 22. The semiconductor memory device according to any one of items 13 to 21. 23. A region of the semiconductor layer in contact with the fourth insulating film formed on the sidewall of the first groove, further comprising a third region.
23. The semiconductor memory device according to claim 22, wherein the impurity region is formed. 24. A semiconductor substrate having a main surface and having a first groove formed in the main surface, the first groove having a side wall, and the side wall of the first groove. A first impurity region formed in a part of the main surface of the semiconductor substrate, and a bit line formed inside the first groove and in contact with the first impurity region. Semiconductor memory device. 25. A second groove having a side wall is further formed on the main surface of the semiconductor substrate, and a second impurity connecting to the first impurity region is formed on the side wall of the second groove. 25. The semiconductor memory device according to claim 24, wherein a region is formed, and a conductor in contact with the second impurity region is formed inside the second groove. 26. The semiconductor memory device according to claim 25, wherein said bit line and said conductor fill the inside of said first and second trenches. 27. The semiconductor memory device according to claim 26, wherein the conductor is a wiring.