JPH0824172B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, particularly to simplification of contacts, and further to contacts for forming a sense amplifier of a memory.

(B) Conventional technology With recent miniaturization and high integration of semiconductor integrated circuit elements,
The contact area between the polysilicon gate, wiring, source and drain and the metal wiring is very small.

However, although A1 has a low melting point and polysilicon can withstand high temperatures, it has a problem that the resistance is high even if a large amount of impurities are doped. A two-layer structure of a silicide film, so-called polycide, is used as wiring. This polycide has a resistance lower than that of polysilicon like a refractory metal or silicide and can contribute to prevention of wiring delay, and thus has been adopted in recent years.

This polycide is, for example, WSi _X / polySi, MoSi _X / polyS
i, TaSi _X / polySi, TiSi _X / polySi, etc. are in practical use.

In particular, WSi _X has been applied to memory after 1 Mbit under severe conditions because high-quality films containing few alkali metals and radioactive elements can be obtained by the CVD method when using WF ₆ .

FIG. 2 shows a conventional pattern structure in which the WSi _X / polySi is used as a bit line, and particularly, the transistor pair Q _P1 , Q _p2 and the bit line pair BL ₁ , BL _{2 of} the sense amplifier shown in FIG. Shows the configuration of.

Here, _P of Q _P1 and Q _P2 indicates that it is a P channel type.

In FIG. 2, four lines arranged in parallel in the lateral direction, which are indicated by alternate long and short dashed lines, are the bit line pair BL ₂ and BL ₁ of the first sense amplifier and the bit line of the second sense amplifier in order. B
L ₁ and BL ₂ . The rectangular regions indicated by the broken lines are the device regions (1) and (2), and the regions hatched by the two-dot chain line and hatched are the gates (3) made of polysilicon,
(4). Dotted line crosses (5) and (6) are bit lines BL
Shown are contacts ₁ and BL ₂ and the gates (3) and (4) in the lower layer of the bit line. Also, the laterally long rectangular regions shown by the solid lines are electrodes (7) and (8) made of aluminum,
The crosses (9) and (10) indicated by solid lines make contact between the bit lines and the drain region. Further, the regions shown by solid lines in the vertical direction are signal lines and are Φ _R and Φ _S in FIG.

(C) Problems to be Solved by the Invention In the above configuration, the electrodes (7) and (8) made of aluminum, which contact the bit lines, are formed for the following reasons.

That is, in the bit line made of polycide such as WSix / polySi, the polySi formed in the lower layer has the TR in the memory cell region of the N channel type, and it is necessary to make contact with this N type diffusion region. , N-type impurities are diffused and formed.

However, the P-channel transistors Q _P1 and Q _{P2 in} FIG.
As shown by the connection in Fig. 3, there is a lot of need to connect the P ⁺ type diffusion region and the N ⁺ type polySi formed in the lower layer of the bit line in the memory, and if they are simply contacted, a PN junction will occur at the contact part. There was a characteristic problem.

Therefore disconnect the bit lines BL ₁ as the second view of the arrow, the bit lines BL ₁ to extend from the left, end the bit lines BL ₁
This aluminum electrode (7) is contacted with the aluminum electrode (7) formed in the upper layer through the contact hole (9).
It has a bridge structure in which it is in contact with the bit line BL ₁ provided in the lower layer through the contact hole (9).

However, this configuration has a problem that an extra design space is required to provide the aluminum electrodes (7) and (8) having the bridge structure, and the number of contacts increases.

Further, the contact resistance between the aluminum electrodes (7) and (8) and the upper layer WSi _X of the bit line becomes extremely unstable due to the process, and thus the operation of the memory sense amplifier may become unstable. there were.

(D) Means for Solving the Problems The present invention is directed to solve the above problems by providing a one-conductivity-type element region formed on a semiconductor substrate and a first insulating film formed on the element region. A gate formed on the first insulating film, a second insulating film formed on the semiconductor substrate so as to cover the gate, and a second insulating film extending from the outside of the element region of the element region. Wiring that passes through or reaches the second insulating film and has a lower layer made of polycide having an opposite conductivity type, a third insulating film formed on the semiconductor substrate so as to cover the wiring, and the element region and the wiring. And a first contact hole formed through the exposed first insulating film to the third insulating film from the element region adjacent to the one region. Between the contact hole and the wiring outside the element area Solves by having an electrode for electrically connecting the element region and the wiring through a second contact hole and out.

(E) Operation As described above, the bit line was integrated without being separated, and two contacts were provided on the bit line so that the contact resistance was formed in parallel instead of in series to reduce the contact resistance.

Further, one of the above two is used for the contact between the bit line and the P ⁺ type diffusion region, and a common contact hole exposing one region of the bit line which overlaps with this diffusion region and the diffusion region adjacent to this one region. Was formed and provided.

Therefore, since the bit line is not cut off, no contact is required and unstable operation of the sense amplifier due to contact resistance can be reduced.

(F) Examples Examples of the present invention will be described below.

First, as shown in FIG. 3, there is an N-type semiconductor substrate (21),
A LOCOS oxide film (22) is formed on the semiconductor substrate (21). A gate (24) made of polysilicon is formed on the semiconductor substrate (21) through a gate insulating film (23).
(25) is formed.

However, since FIG. 3 is a sectional view taken along the line AA ′ in FIG. 1, gates (24) and (25) are gates of different sense amplifiers.

Also, the LOCOS oxide film (22) and gates (24), (25)
Self-aligned by the P-type diffusion region (26),
(27), here, the source and drain (26) and (27), which are the element regions of the P-channel transistor, are formed by ion implantation. Of course, the N-channel transistor is similarly formed.

As mentioned in the section of the problem to be solved by the invention,
In the memory, the transistors in the cells are N-channel and the peripheral circuits are CMOS. Therefore, the wiring has more contacts with the N-type diffusion region than with the P-type diffusion region. FIG. 1 is a plan view of the sense amplifier circuit of FIG. 5 on the P-channel transistors Q _P1 and Q _P2 side, and the P-type element region including the source and drain is a rectangular broken line. In the area shown, gate (24),
(25) is indicated by a two-dot chain line area hatched by diagonal lines.

Therefore, the gate (24) has the first transistor Q _P1 formed therein, and the gate (25) has the second transistor Q _P2 formed therein.

An SiO ₂ film (28) which is an interlayer insulating film formed by the LPCVD method is formed on the gates (24) and (25).

Then, a pair of polycide bit lines composed of WSi _X / polySi are arranged in a lateral direction substantially parallel to each other by the alternate long and short dash line in FIG.
BL ₂ , BL ₁ , BL ₁ , BL ₂ are arranged in this order. Polysilicon (29) doped with N-type impurities is provided in the lower polycide, and the upper layer of this polysilicon (29) is
A tungsten silicide film (30) made of WSi _X is provided.

Further, an interlayer insulating film (31), here, for example, a BPSG film or a SiO ₂ film formed by a CVD method is formed on the semiconductor substrate including the bit line, and an electrode made of aluminum is further formed on the interlayer insulating film (31) in FIG. A first electrode (32) and a second electrode (33) which contact the signal lines Φ _R and Φ _S and the bit line with the drain region are formed. Here, in addition to aluminum, refractory metal, polysilicon, etc. can be considered.

The signal lines Φ _R and Φ _S are shown by solid lines and are arranged substantially orthogonal to the bit lines, and Φ _R and the transistor Q _{P1 are connected} to the contact regions (34) and (35) indicated by _crosses . Also contacts in contact with the source region of Q _P2 (36)
Is in direct contact with the semiconductor substrate to bias the N-type region outside the device region.

Finally, the first electrode (32) and the second electrode, which are the features of the present invention,
The contact structure of the electrode (33) will be described. The rectangular shape with a cross, indicated by the solid line, is the first contact (3
7) and the second contact (38). The contacts (37) and (38) are opened as one common contact so that a part of the bit line overlapping with the drain region and the drain region adjacent to this part are exposed. Then, through the common contact, the first electrode (3
2), the second electrode (33) is provided. This contact structure is shown in FIG. 3, where the exposed region of the bit line and the diffusion region are in contact with the electrodes (32), (33). Also here, the third contact hole (39)
A fourth contact hole (40) is provided.

Therefore, since the first contact hole (37) and the second contact hole (38) are provided, the bit line made of polycide, especially the lower N type polysilicon (29) and the P ⁺ type diffusion region are formed. Ohmic contact is possible without making direct contact.

Further, the third contact hole (39) and the fourth contact hole (40) are provided with the bit line BL ₂ , the first electrode (32) and the bit line B.
Since L ₁ and the second electrode (33) are connected to each other, the contact resistance and the wiring resistance are connected in parallel, and the contact resistance can be reduced. The first electrode (32) and the second electrode (3
3) has a parallel structure instead of connecting the disconnected bit lines in series as shown in the conventional example, so that the contact region (38), (40) or (37) between this electrode and the bit line is formed. , (39) is unstable, it can be compensated by the remaining contact. Further, since no contact resistance is inserted between the bit lines, it is possible to eliminate a defect in the sense amplifier due to instability of the contact connecting the bit lines.
Moreover, even with this structure, two contact structures can be adopted from the conventional three contact structures. In reality, since a sense amplifier is provided for each pair of bit lines, the contact reduction can be greatly reduced when considering the entire memory.

Next, a second embodiment will be described with reference to FIG. In this embodiment, the third contact hole (39) and the fourth contact hole (40) of the previous embodiment are omitted, and as a result, the first contact hole (39) and the fourth contact hole (40) are omitted.
The electrode (32) and the second electrode (33) are slightly different and are otherwise the same. Therefore, only different points will be described here and the other description will be omitted.

In this embodiment, the bit line and the P ⁺ type diffusion region are in contact with each other through the first contact hole (37) and the second contact hole (38). Therefore, the number of contacts can be reduced by four for each sense amplifier as compared with the conventional case.

(G) Effect of the Invention First, since the bit lines are integrated rather than the structure in which the bit lines are separated and the bit lines are connected to each other by the bridge structure electrode, a contact failure connecting the bit lines to each other occurs. Bit line resistance can be reduced.

Secondly, since the bit line and the P ⁺ type diffusion region adopt a common contact in which the P ⁺ type diffusion region adjacent to the bit line surface is opened at a time, both of them are provided with contacts as in the conventional case. The number of contacts can be reduced by the structure.

Therefore, it is possible to realize stable operation of the sense amplifier without opening due to contact failure between bit lines. Furthermore, the number of contacts can be reduced by 1 or 2 for each sense amplifier. Becomes Therefore, the chip area can be reduced and the pattern can be simplified.

Thirdly, in the first embodiment, in addition to the common contact,
Since the separate contact for connecting the bit line and the first electrode and the bit line and the second electrode is provided, the contact resistances are connected in parallel and the contact resistance can be reduced. Moreover, since the two contacts between the electrode and the bit line are provided, the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device of the present invention, FIG. 2 is a plan view of a conventional semiconductor device, and FIG. 3 is AA ′ of FIG.
4 is a sectional view taken along the line, FIG. 4 is an equivalent circuit diagram of the sense amplifier, and FIG. 5 is a plan view of a semiconductor device of another embodiment.

Claims (6)

[Claims] 1. An element region of one conductivity type formed on a semiconductor substrate, a first insulating film formed on the element region, and a gate formed on the first insulating film. A second insulating film formed on the semiconductor substrate so as to cover the gate, and a second insulating film extending from the outside of the device region to the second insulating film of the device region.
Wiring that passes through or reaches the insulating film and has a lower layer made of polycide having an opposite conductivity type, and a third wiring formed on the semiconductor substrate so as to cover the wiring.
Common insulating layer formed between the first insulating film and the third insulating film exposed from the element region adjacent to the one region and the wiring that overlaps the element region. A semiconductor device comprising: a hole, and an electrode electrically connecting the wiring and the element region through the common contact hole and a contact hole exposing a wiring outside the element region. 2. A contact hole outside the element region is removed,
The semiconductor device according to claim 1, wherein the wiring and the element region are electrically connected by the common contact hole and the electrode. 3. The semiconductor device according to claim 1, wherein the conductive material is a semiconductor of one conductivity type or a metal. 4. The semiconductor device according to claim 1, wherein the wiring is a bit line forming a sense amplifier, and the element region is a P-type diffusion region forming the sense amplifier. 5. A device region of at least one pair of one conductivity type formed on a semiconductor substrate, and a LOCO formed on the semiconductor substrate surrounding the device region.
S oxide film, one gate and the other gate respectively formed on the first insulating film that covers at least the one element region and the other element region, the one gate and the one element region A second transistor formed of the other gate and the other element region, a second insulating film that covers at least the gate, and the LOCOS oxide film from above. One bit line made of polycide that extends over one element region and contacts the one gate and extends over the drain region of the second transistor, and is substantially parallel to the one bit line. And the LOCOS
The other bit line made of polycide that extends from above the oxide film onto the drain region of the first transistor and the other element region and is in contact with the other gate, and the one bit line and the other bit line. A third insulating film that covers at least the one surface of the one wiring that overlaps with the drain region of the second transistor, and a common first surface that exposes the surface of the drain region of the second transistor adjacent to the one surface. A first contact, a surface of the other wiring overlapping the drain region of the first transistor, and a common second surface exposing the surface of the drain region of the first transistor adjacent to the one surface.
And a first electrode electrically connecting the first contact to a third contact exposing one wiring outside the second transistor region, and being outside the first transistor region. A second electrode electrically connecting the second contact and the second contact, which exposes the other wiring, a line substantially perpendicular to the bit line, and a source region of the first transistor and the second electrode. A semiconductor device having at least a signal line electrically connecting to a source region of the transistor. 6. The third contact and the fourth contact are removed, and the bit line and the drain region are electrically connected by the first contact and the first electrode and the second contact and the second electrode. 5. The semiconductor device according to claim 4, wherein the semiconductor device is connected to.