JP2966482B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to simplification of a contact, and further relates to a contact for forming a sense amplifier of a memory.

(B) Conventional technology With the recent miniaturization and high integration of semiconductor integrated circuit devices,
The contact area between the polysilicon gate, wiring, source, drain and metal wiring is extremely small.

However, although Al has a low melting point and polysilicon can withstand high temperatures, it has a problem of high resistance even if it is heavily doped with impurities.To solve both problems, polysilicon film and metal silicide are used. Polycide having a two-layer structure of a film is used as a wiring. This polycide has a lower resistance than polysilicon, like high melting point metal and silicide,
It is adopted because it can contribute to prevention of wiring delay and the like.

This polycide is, for example, WSi _x / polySi, MoSi _x / polyS
i, TaSi _x / polySi, TiSi _x / polySi, etc. are at the practical stage.

In particular, when WF ₆ is used for WSi _{x, a} high-quality film with few alkali metals and radioactive elements can be obtained by the CVD method.

FIG. 2 shows a conventional pattern structure using this WSi _x / polySi as a bit line. In particular, the transistor pair Q _P1 and Q _P2 and the bit line pair BL ₁ and BL _{2 of} the sense amplifier shown in FIG. Is shown.

Here, _P of Q _P1 and Q _P2 indicates a P-channel type.

4 arranged in parallel in the horizontal direction shown by the dashed line
Are sequentially connected to the bit line pair BL of the first sense amplifier.
₂ , BL ₁ and the bit line pair BL ₁ , BL ₂ of the second sense amplifier. Areas on a square shown by broken lines are element areas (1) and (2), and areas hatched by diagonal lines and hatched by polysilicon are gates (3) and polysilicon made of polysilicon.
(4). Dotted crosses (5) and (6) indicate bit lines BL
₁ , BL ₂ and the lower gates (3), (4). The rectangular regions elongated in the horizontal direction shown by solid lines are electrodes (7) and (8) made of aluminum, and the crosses between bit lines and the drain region are contacted by crosses (9) and (10) shown by solid lines. ing. Further, the area indicated by the solid line in the vertical direction is
The signal lines are Φ _R and Φ _S in FIG.

(C) Problems to be Solved by the Invention In the above configuration, the electrodes (7) and (8) made of aluminum for contacting between bit lines are formed for the following reasons.

In other words, in the bit line made of polycide such as WSi _x / polySi, poly-silicon formed in the lower layer has a large ratio of contact with the N ⁺ type diffusion region in the contact of the entire memory, so that N-type impurities are contained. It is formed by diffusion.

However, the P-channel transistors Q _P1 and Q _P2 shown in FIG.
As shown by the connection, there is often a need to connect the P ⁺ type diffusion region and the N ⁺ type polySi formed under the bit line in the memory, and if a simple contact is made, a PN junction will occur at the contact part There was a problem characteristically.

Therefore as Fig. 4 (sectional view along line A-A 'of FIG. 2), and contact with the aluminum electrode (7) formed on the upper end bit lines BL _1, through the aluminum electrode (7) It is put in contact through the bit lines BL ₁ and the contact hole provided in the lower Te (9).

However, this configuration has a problem that an extra design space is required to provide the aluminum electrodes (7) and (8) and that the number of contacts increases.

Further, as can be seen from FIG. 2, it is necessary to cut the bit line, and the operation of the sense amplifier of the memory may become unstable due to an increase in the number of contacts.

(D) Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides an element region of one conductivity type formed on a semiconductor substrate, an insulating film formed in the element region, A wiring extending from the outside of the region, passing or reaching over the insulating film on the element region, and a lower layer formed of polycide formed on the insulating film having the opposite conductivity type; and a wiring of the element region and the wiring This problem is solved by providing a contact hole formed in an insulating film corresponding to the overlapping region, and filling the contact hole with a conductive material that does not form a PN junction with the element region.

(E) Function As described above, by embedding a conductive material that does not form a PN junction with the element region between the contact between the element region and the wiring, the aluminum electrode conventionally used can be omitted, and as a result, the connection between the wiring and the aluminum electrode can be eliminated. Contacts can also be omitted.

Since the bit line is not disconnected, no contact is required, and unstable operation of the sense amplifier due to contact resistance or the like can be reduced.

(F) Examples Examples of the present invention will be described below.

First, as shown in FIG. 3, there is an N-type semiconductor substrate (21).
A LOCOS oxide film (22) is formed on the semiconductor substrate (21). A gate (24) made of polysilicon is provided on the semiconductor substrate (21) via a gate insulating film (23).
(24 ') is formed.

However, since FIG. 3 is a sectional view taken along the line AA 'of FIG. 1, the gate (24) is not shown.

The LOCOS oxide film (22) and the gate (24) are self-aligned to form P-type diffusion regions (25), (25 '),
Here, the element region of the P-channel transistor (25),
(25 ') is formed by ion implantation. Of course N
A channel transistor is also formed.

As mentioned in the section of the problem to be solved by the invention,
The memory has N-channel transistors in the cells and CMOS peripheral circuits. Therefore, although the number of contacts with the N-type diffusion region is larger than the number of contacts with the P-type diffusion region, FIG. 1 is a plan view of the P-channel transistors Q _P1 and Q _P2 of the sense amplifier circuit of FIG. And the P-type element regions (25), (25 ')
Are gates (24), (2)
4 ') is indicated by a two-dot chain line area hatched with oblique lines.

Therefore, a first transistor Q _P1 is formed at the gate (24), and a second transistor Q _P2 is formed at the gate (24).

It said gate (24), are formed SiO ₂ film (26) which is in (24 ') on an interlayer insulating film formed by the LPCVD method. This SiO ₂ film (26) has an upper layer of WSi _x / pol
A second contact hole (27) and a first contact hole for electrically contacting the bit lines BL ₁ and BL ₂ made of a polycide layer of ySi with the P-type diffusion regions (25) and (25 ′). There is (28).

In the contact holes (27) and (28), an electrode material which does not form a PN junction with the diffusion regions (25) and (25 '), for example, tungsten W by selective vapor deposition is buried.

Next, a bit line pair is made substantially parallel in the horizontal direction by a dashed line in FIG. 1 with a polycide having a composition of WSi _x / polySi.
BL ₂ , BL ₁ , BL ₁ , and BL ₂ are arranged in this order. The lower layer of the polycide is provided with polysilicon (29) doped with an N-type impurity, and the upper layer of the polysilicon (29) is provided.
A tungsten silicide film (30) made of WSi _x is provided. Therefore, the bit lines BL ₁ and BL ₂ and the diffusion regions (25) and (25 ′) are electrically connected to each other through the electrode material embedded in the first contact hole (27) and the second contact hole (28). Are combined.

In addition, an interlayer insulating layer (3
1) For example, a BPSG film or a SiO ₂ film formed by a CVD method is formed, and electrodes made of aluminum, here, signal lines Φ _R and Φ _S are vertically arranged by solid lines in FIG. I have.

The signal line Φ _R is connected to the contact region (32),
(33) is commonly connected to the sources of the transistors Q _P1 and Q _P2 .

(G) Effects of the Invention As is clear from the above description, by embedding a conductive material that does not form a PN junction with the element region between the element region and the contact of the wiring, the aluminum electrode that has been conventionally used can be omitted. As a result, the contact between the wiring and the aluminum electrode can be omitted.

Therefore, the capacitance between the aluminum electrode and the wiring, which is conventionally provided, can be eliminated, and the contact resistance can be eliminated by omitting the contact, thereby improving the operation of the sense amplifier. Moreover, since the contacts can be omitted, the design space can be reduced, design flexibility can be achieved, and the design can be simplified, and the yield can be improved.

In addition, the present invention can be implemented in a place other than the sense amplifier, and can be implemented in a contact portion between a polycide wiring and a P-type diffusion region.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to the present invention, FIG. 2 is a plan view of a conventional semiconductor device, and FIGS.
FIG. 5 is a sectional view taken along the line AA ′ in FIG. 2 and FIG. 5 is an equivalent circuit diagram of the sense amplifier.

Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/43 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 27/10 H01L 21/8242 H01L 21 / 3205 H01L 21/768 H01L 29/43

Claims (2)

(57) [Claims] At least one pair of one conductivity type device regions formed on a semiconductor substrate, and a LOCO formed on the semiconductor substrate surrounding the device region.
An S oxide film, a pair of bit lines extending over the LOCOS oxide film, and made of polycide passing or reaching over the insulating film over the element region; and overlapping the one element region with the one bit line A first transistor substantially formed in the region and electrically connected to the bit line; a first transistor including the first gate and sources and drains formed on both sides of the gate; A second gate substantially formed in an overlapping region of the other element region and the other bit line, and electrically connected to the bit line; a second gate formed on both sides of the second gate; A second transistor comprising a source and a drain, and electrically contacting the one bit line and a drain formed in the other element region;
A first contact hole in which a conductive material that does not form a PN junction is embedded, and the other bit line is electrically contacted with a drain formed in the one element region;
A second contact hole in which a conductive material that does not form a PN junction is embedded, and at least a signal line that electrically contacts the source of the one element region and the source of the other element region. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said conductive material is tungsten.