Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0824210B2 - Optical bistable semiconductor laser and manufacturing method thereof - Google Patents
[go: Go Back, main page]

JPH0824210B2 - Optical bistable semiconductor laser and manufacturing method thereof - Google Patents

Optical bistable semiconductor laser and manufacturing method thereof

Info

Publication number
JPH0824210B2
JPH0824210B2 JP17958887A JP17958887A JPH0824210B2 JP H0824210 B2 JPH0824210 B2 JP H0824210B2 JP 17958887 A JP17958887 A JP 17958887A JP 17958887 A JP17958887 A JP 17958887A JP H0824210 B2 JPH0824210 B2 JP H0824210B2
Authority
JP
Japan
Prior art keywords
layer
laser
active layer
inp
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17958887A
Other languages
Japanese (ja)
Other versions
JPS6422089A (en
Inventor
正明 久野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17958887A priority Critical patent/JPH0824210B2/en
Publication of JPS6422089A publication Critical patent/JPS6422089A/en
Publication of JPH0824210B2 publication Critical patent/JPH0824210B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F3/00Optical logic elements; Optical bistable devices
    • G02F3/02Optical bistable devices
    • G02F3/026Optical bistable devices based on laser effects

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 [概要] 光入力に対する光出力が双安定を示す光双安定半導体
レーザの構造とその製造方法に関し、 複数の電極を分離する分離溝の幅を狭くして、且つ、
分離抵抗を高くすることを目的として、 活性層と、該活性層とヘテロ接合をなす上下クラッド
層と、該活性層に電流を注入する電極とを備え、且つ、
ストライプ状に形成されたレーザ層を有する半導体レー
ザにおいて、 該ストライプ方向に直交し、且つ、少なくとも上部ク
ラッド層にまで達する分離溝によつて該電極が複数に分
割され、加えて、該ストライプ状のレーザ層の両側面と
該分離溝が半絶縁性半導体層によつて埋没されてなるよ
うに構成にする。
DETAILED DESCRIPTION OF THE INVENTION [Outline] A structure of an optical bistable semiconductor laser exhibiting a bistable optical output with respect to an optical input and a manufacturing method thereof, in which a width of a separation groove for separating a plurality of electrodes is narrowed, and
An active layer, upper and lower cladding layers forming a heterojunction with the active layer, and electrodes for injecting a current into the active layer for the purpose of increasing the isolation resistance, and
In a semiconductor laser having a laser layer formed in a stripe shape, the electrode is divided into a plurality of pieces by a separation groove that is orthogonal to the stripe direction and reaches at least the upper cladding layer, and in addition, Both side surfaces of the laser layer and the separation groove are buried by a semi-insulating semiconductor layer.

[産業上の利用分野] 本発明は光双安定半導体レーザの構造とその製造方法
に関する。
TECHNICAL FIELD The present invention relates to a structure of an optical bistable semiconductor laser and a manufacturing method thereof.

光双安定半導体レーザとは、分割した電極に流す電流
を独立に制御して光出力が2つの安定状態を取り得るレ
ーザのことで、このような光双安定素子は光信号を利用
した通信・情報処理分野においてスイッチ,メモリ,演
算,増幅を可能にする機能素子であつて、且つ、小型で
操作が簡単、高集積化が可能なために、その開発研究が
強く推進されている。
An optical bistable semiconductor laser is a laser that can independently control the currents flowing through the divided electrodes and have two stable optical outputs. Such an optical bistable element is used for communication using optical signals. In the field of information processing, a functional element that enables a switch, a memory, an operation, and an amplification, and is small in size, easy to operate, and highly integrated, so that the research and development thereof is strongly promoted.

このような光双安定半導体レーザにおいて、分離され
た電極間の分離抵抗を高め、且つ、分離溝の幅を狭くす
ることが特性向上の鍵であり、そのような構造のレーザ
素子が要望されている。
In such an optical bistable semiconductor laser, increasing the isolation resistance between the separated electrodes and narrowing the width of the isolation groove is the key to improving the characteristics, and a laser device having such a structure is desired. There is.

[従来の技術] 光双安定半導体レーザの構造はG.J.Lasher氏によつて
1964年に電極を共振器方向に2つに分割し、一方を光増
幅領域、他方を光吸収領域として用いる直列に分割され
た電極(タンデム(tandem)電極)構造のものが発表さ
れている(Solid state Electronics 7巻(1964).PP.7
07〜716参照)。この構造は以降のダブルヘテロ接合,
埋込み構造の適用によつてほぼ実用レベルに達してき
た。
[Prior Art] The structure of an optical bistable semiconductor laser was written by GJ Lasher.
In 1964, an electrode (tandem electrode) structure was announced in which the electrode was divided into two in the cavity direction, one of which was used as a light amplification region and the other as a light absorption region (tandem electrode). Solid state Electronics Volume 7 (1964) .PP.7
07-716). This structure is the following double heterojunction,
The application of the embedded structure has almost reached the practical level.

以前、発明者は化学気相成長(CVD)法を用いてメサ
ストライプ状レーザ層の両側の閉込め層(埋込み層)を
半絶縁性の高抵抗InPで埋め込んだ光双安定半導体レー
ザを提案した(特願昭61−304518号参照)。この構造に
よれば、分割された電極間の抵抗を容易に1KΩ以上とす
ることができ、また、注入電流の廻り込みも防げるの
で、均一で再現性の良い素子が得られる。
Previously, the inventor proposed an optical bistable semiconductor laser in which the confinement layers (embedded layers) on both sides of the mesa stripe laser layer were embedded with semi-insulating high-resistance InP using the chemical vapor deposition (CVD) method. (See Japanese Patent Application No. 61-304518). With this structure, the resistance between the divided electrodes can be easily set to 1 KΩ or more, and the sneak of the injection current can be prevented, so that a uniform and highly reproducible element can be obtained.

第6図はその提案した従来構造の光双安定半導体レー
ザを示す図で、同図(a)は斜視図,同図(b)はその
XX′断面図である。図中、1はn−InP基板,2はn−InP
クラッド層(バッフア層とも云う),3はInGaAsP活性層
(アンドープ),4はp−InPクラッド層,5はp+−InGaAsP
キャップ層,8はSiO2膜からなる絶縁膜,9A,9Bは分離した
p型電極,10は裏面のn型電極,11は閉込め層の半絶縁性
InP層(SI−InP層),12は分離溝で、ストライプ状レー
ザ層6はn−InPクラッド層2よりInGaAsP活性層3,p−I
nPクラッド層4,p+−InGaAsPキャップ層5に至る部分で
形成されている。また、SI−InP層11の抵抗率は10〜10
Ωcm程度のもので、このレーザ素子の寸法は凡そ次の通
りである。
FIG. 6 is a diagram showing the proposed conventional optical bistable semiconductor laser, in which FIG. 6 (a) is a perspective view and FIG. 6 (b) is its perspective view.
It is a XX 'sectional view. In the figure, 1 is an n-InP substrate, 2 is an n-InP substrate
Cladding layer (also called buffer layer), 3 is InGaAsP active layer (undoped), 4 is p-InP cladding layer, 5 is p + -InGaAsP
Cap layer, 8 is an insulating film made of SiO 2 film, 9A and 9B are separate p-type electrodes, 10 is a backside n-type electrode, and 11 is a semi-insulating layer of the confinement layer.
InP layers (SI-InP layers), 12 are isolation trenches, and the striped laser layer 6 is composed of the InGaAsP active layers 3, p-I from the n-InP cladding layer 2.
It is formed in a portion reaching the nP cladding layer 4 and the p + -InGaAsP cap layer 5. The resistivity of the SI-InP layer 11 is 10 to 10
It is about Ωcm, and the dimensions of this laser device are as follows.

A=B=300μm,C=120μm, 閉込め層の深さd=2.5〜3μm ストライプ幅W=1〜2μm, 分離幅X=15μm(10〜40μm). なお、この従来構造の分離溝12はInGaAsPキャップ層
まで除去した深さの溝となつている。
A = B = 300 μm, C = 120 μm, confinement layer depth d = 2.5-3 μm, stripe width W = 1-2 μm, separation width X = 15 μm (10-40 μm). The isolation groove 12 of this conventional structure is a groove having a depth removed up to the InGaAsP cap layer.

[発明が解決しようとする問題点] ところで、上記の光双安定半導体レーザにおいて、分
離溝12の幅を変化させて電極間の抵抗値を測定した分離
溝幅と電極間の抵抗値との関係図表を第7図に示し、且
つ、分離溝幅を変化させて発振しきい値を測定した分離
溝幅と発振しきい値との関係図表を第8図に示す。
[Problems to be Solved by the Invention] In the above-mentioned optical bistable semiconductor laser, the relationship between the separation groove width and the resistance value between the electrodes, in which the resistance value between the electrodes is measured by changing the width of the separation groove 12 FIG. 7 shows a chart, and FIG. 8 shows a relational chart between the separation groove width and the oscillation threshold value which are obtained by measuring the oscillation threshold value by changing the separation groove width.

第7図に示す図表より、分離抵抗を高くするためには
分離溝幅を広くすれば良いことが明白である。一方、第
8図より分離溝幅を広くすると発振しきい値が急激に高
くなることが判かり、溝幅が50μmを越えれば発振しき
い値が数百mA以上と非常に大きくなる。これは分離溝に
は電極がなく、分離溝直下の活性層へ電流が注入されな
いため、共振器内で大きな損失となつて発振しきい値が
高くなるものである。しかし、このしきい値の上昇は特
性劣化の基本的事項で、出来るだけ低いしきい値に維持
することが望ましい。
It is clear from the chart shown in FIG. 7 that the separation groove width can be widened in order to increase the separation resistance. On the other hand, it can be seen from FIG. 8 that the oscillation threshold value sharply rises when the separation groove width is widened, and when the groove width exceeds 50 μm, the oscillation threshold value becomes extremely large at several hundred mA or more. This is because there is no electrode in the separation groove and no current is injected into the active layer directly below the separation groove, which causes a large loss in the resonator and raises the oscillation threshold. However, this rise of the threshold value is a basic matter of characteristic deterioration, and it is desirable to maintain the threshold value as low as possible.

ところで、上記第7図に示す分離溝幅と電極間の抵抗
値との関係図表において、○印は実測値で、実線はキャ
リア移動濃度より求めたInPクラッド層の抵抗値であ
り、非常に良く一致しているが、これよりInPクラッド
層を除去すれば大幅に分離抵抗を上昇することが推考さ
れ、そうすれば、分離幅を広くせずに、更に分離抵抗を
高めることが可能になる。また、活性層3を含む両InP
クラッド層2,4(活性層の下部)まで除去して、抵抗率1
0ΩcmのSI−InP層11を埋め込めば、分離溝幅2μmのと
きに10Ω以上の分離抵抗が期待できる。
By the way, in the relationship diagram between the separation groove width and the electrode-to-electrode resistance value shown in FIG. 7 above, the ○ mark is the measured value, and the solid line is the resistance value of the InP clad layer obtained from the carrier transfer concentration. It is in agreement, but it is considered that the removal of the InP clad layer will significantly increase the isolation resistance, and by doing so, it becomes possible to further increase the isolation resistance without widening the isolation width. In addition, both InPs including the active layer 3
The clad layers 2 and 4 (lower part of the active layer) are removed, and the resistivity is 1
If the SI-InP layer 11 of 0 Ωcm is embedded, a separation resistance of 10 Ω or more can be expected when the separation groove width is 2 μm.

本発明はこのような観点より、分離溝の幅を狭くし
て、且つ、分離抵抗を高くすることを目的として、光双
安定半導体レーザの新規な構造を提案するものである。
From this point of view, the present invention proposes a novel structure of an optical bistable semiconductor laser for the purpose of narrowing the width of the separation groove and increasing the separation resistance.

[問題点を解決するための手段] その目的は、ストライプ方向に直交し、且つ、少なく
とも上部クラッド層にまで達する分離溝によつて該電極
が複数に分割され、加えて、該ストライプ状のレーザ層
の両側面と該分離溝が半絶縁性半導体層によつて埋没さ
れた光双安定半導体レーザの構造によつて達成される。
[Means for Solving the Problems] The purpose is to divide the electrode into a plurality of parts by a separation groove which is orthogonal to the stripe direction and reaches at least the upper cladding layer, and in addition, the stripe-shaped laser This is achieved by the structure of an optical bistable semiconductor laser in which both sides of the layer and the separating groove are buried by a semi-insulating semiconductor layer.

且つ、それを形成するためには、半導体基板上に活性
層と、該活性層とヘテロ接合をなす上下クラッド層を備
えるストライプ状のレーザ層を形成する工程と、該スト
ライプ状のレーザ層の両側面を埋没する半絶縁性半導体
層を形成する工程と、該ストライプ方向に直交し、且
つ、上部クラッド層にまで達する分離溝を形成する工程
と、該分離溝部分に半絶縁性半導体層を埋没する工程と
が含まれる製造方法を用いる。
In addition, in order to form it, a step of forming a stripe-shaped laser layer including an active layer and upper and lower clad layers forming a heterojunction with the active layer on a semiconductor substrate, and both sides of the stripe-shaped laser layer. A step of forming a semi-insulating semiconductor layer for burying the surface, a step of forming an isolation groove orthogonal to the stripe direction and reaching the upper clad layer, and a step of burying the semi-insulating semiconductor layer in the isolation groove portion. The manufacturing method including the step of

また、半導体基板上に活性層と、該活性層とヘテロ接
合をなす上下クラッド層を形成する工程と、該活性層お
よび上下クラッド層を選択的にエッチングし、ストライ
プ状で且つ該ストライプ方向に直交する分離溝によつて
複数に分割されてなるレーザ層を形成する工程と、該レ
ーザ層の両側面及び該分離溝を半絶縁性半導体層によつ
て埋没する工程が含まれる製造方法を用いる。
Further, a step of forming an active layer and upper and lower clad layers forming a heterojunction with the active layer on a semiconductor substrate, and selectively etching the active layer and the upper and lower clad layers to form a stripe shape and orthogonal to the stripe direction. The manufacturing method includes a step of forming a laser layer divided into a plurality of parts by the separation groove, and a step of burying both side surfaces of the laser layer and the separation groove with a semi-insulating semiconductor layer.

[作用] 即ち、本発明は、分離溝を活性層の少なくとも上部ク
ラッド層まで達する深さに形成し、その分離溝を半絶縁
性半導体層で埋没させた構造にする。そうすれば、分離
抵抗が高くなつて、且つ、発振しきい値が低くできる。
[Operation] That is, according to the present invention, the isolation trench is formed to a depth reaching at least the upper cladding layer of the active layer, and the isolation trench is buried with the semi-insulating semiconductor layer. Then, the isolation resistance can be increased and the oscillation threshold can be lowered.

[実施例] 以下、図面を参照して実施例により詳細に説明する。[Examples] Hereinafter, examples will be described in detail with reference to the drawings.

第1図は本発明にかかるレーザの構造(I)を示す図
で、同図(a)は斜視図、同図(b)はそのYY′断面を
示しており、第6図に示す従来構造と同じく、1はn−
InP基板,2はn−InPクラッド層(バッフア層),3はInGa
AsP活性層,4はp−InPクラッド層,5はp+−InGaAsPキャ
ップ層,6はレーザ層,8はSiO2膜(絶縁膜),9A,9Bは分離
したp型電極,10はn型電極,11はSI−InP層で、21は分
離溝を埋没させたSI−InP層である。本例は分離溝をp
−InPクラッド層4(活性層の上部)まで形成し、その
部分にSI−InP層21を埋没させた実施例で、このような
レーザ構造をもち、分離溝幅X=2μm,ストライプ幅W
=1.5μmの寸法を有するレーザ素子からは56KΩの分離
抵抗値が得られる。且つ、単一のp型電極を有する通常
の半導体レーザと比べて発振しきい値の上昇は僅かに数
%に止まる。これは分離溝幅が狭くてInGaAsP活性層3
の非電流注入幅が減少し、共振器内の損失が減少するた
めと考えられる。
FIG. 1 is a diagram showing a structure (I) of a laser according to the present invention, in which FIG. 1 (a) is a perspective view and FIG. 1 (b) is a YY 'cross section thereof, showing the conventional structure shown in FIG. 1 is n-
InP substrate, 2 n-InP clad layer (buffer layer), 3 InGa
AsP active layer, 4 is p-InP clad layer, 5 is p + -InGaAsP cap layer, 6 is laser layer, 8 is SiO 2 film (insulating film), 9A and 9B are separate p-type electrodes, 10 is n-type The electrode, 11 is an SI-InP layer, and 21 is an SI-InP layer in which the separation groove is buried. In this example, the separation groove is p
In the embodiment in which the -InP clad layer 4 (upper part of the active layer) is formed and the SI-InP layer 21 is buried in that portion, the laser structure is provided, the separation groove width X = 2 μm, and the stripe width W.
A separation resistance value of 56 KΩ can be obtained from a laser device having a dimension of = 1.5 μm. In addition, the rise in the oscillation threshold is only a few percent as compared with the usual semiconductor laser having a single p-type electrode. This is because the separation groove width is narrow and the InGaAsP active layer 3
It is considered that this is because the non-current injection width of is reduced and the loss in the resonator is reduced.

また、第2図は本発明にかかる構造(II)を示す図
で、同図(a)は斜視図、同図(b)はそのZZ′断面を
示しており、第1図に示す構造と同一部位には同一記号
が付けてあるが、22が分離溝を埋没させたSI−InP層で
あり、本例では分離溝がp−InPクラッド層4,InGaAsP活
性層3を越えてn−InPクラッド層2(活性層の下部)
まで達しており、その溝部分にSI−InP層22を埋没させ
た実施例である。このように活性層3を共振方向に一部
を除去し、その活性層部分にSI−InP層22を埋没させて
も、SI−InP層22の幅が2μm程度と非常に狭いため、
また、InGaAsP活性層3と鉄ドープしたSI−InP層22との
光屈折率の差は余り大きくないために大きな伝播損失に
はならない。
2 is a diagram showing a structure (II) according to the present invention. FIG. 2 (a) is a perspective view and FIG. 2 (b) is a ZZ 'cross section thereof, showing the structure shown in FIG. Although the same symbols are given to the same portions, 22 is an SI-InP layer in which the isolation groove is buried. Clad layer 2 (lower part of active layer)
In this embodiment, the SI-InP layer 22 is buried in the groove. Even if the active layer 3 is partially removed in the resonance direction and the SI-InP layer 22 is buried in the active layer portion in this way, the width of the SI-InP layer 22 is very narrow, about 2 μm.
Further, since the difference in optical refractive index between the InGaAsP active layer 3 and the iron-doped SI-InP layer 22 is not so large, a large propagation loss does not occur.

このInGaAsP活性層3を越えてn−InPクラッド層2
(活性層の下部)までSI−InP層22を埋没させる本発明
にかかる構造(II)は前記した構造(I)よりも一層高
抵抗な分離層を設けた構造である。実施結果によれば、
分離溝幅X=2μm,ストライプ幅W=1.5μmの寸法の
レーザ素子から10Ω以上の分離抵抗値が得られ、タンデ
ム電極間の注入電流の相互拡散が無視できるようになつ
た。
Beyond this InGaAsP active layer 3, n-InP clad layer 2
The structure (II) according to the present invention in which the SI-InP layer 22 is buried up to (the lower part of the active layer) is a structure in which the isolation layer having a higher resistance than that of the structure (I) is provided. According to the implementation results,
A separation resistance value of 10 Ω or more was obtained from a laser element having a separation groove width X = 2 μm and a stripe width W = 1.5 μm, and the mutual diffusion of injection current between tandem electrodes became negligible.

一方、InGaAsP活性層3をカットせずに上側のp−InP
クラッド層4(活性層の上部)までSI−InP層21を埋没
させる前記の本発明にかかる構造(I)は比較的に活性
層の光伝播損失の小さい構造であり、この2つの構造
(I),(IIは分離抵抗と発振しきい値とのいずれを優
先するかによつて使い分けするものである。
On the other hand, the p-InP on the upper side without cutting the InGaAsP active layer 3
The above-mentioned structure (I) according to the present invention in which the SI-InP layer 21 is buried up to the clad layer 4 (upper part of the active layer) is a structure in which the light propagation loss of the active layer is relatively small. ), (II is used depending on whether the isolation resistance or the oscillation threshold is prioritized.

上記例は1つの分離溝を設けた光双安定半導体レーザ
の構造例であるが、2つ以上の分離溝を形成して3つ以
上のタンデム電極を設けた構造にしても、同様に分離溝
にSI−InP層を埋没させると、同様に分離抵抗を高くし
て発振しきい値を小さくできる。第3図(a),(b)
は2つの分離溝を形成して3つのタンデム電極を設けた
他の構造例で、同図(a)は第1図に示す実施例と同様
に分離溝をp−InPクラッド層4まで形成して、そこにS
I−InP層21A,21Bを埋没させた例で、9A,9B,9Cがp電極
である。第3図(b)は第2図に示す実施例と同様に分
離溝を活性層3を越えてn−InPクラッド層2まで形成
し、そこにSI−InP層22A,22Bを埋没させ、p電極9A,9B,
9Cを設けた例である。
The above example is an example of the structure of an optical bistable semiconductor laser having one separation groove. However, even if a structure in which two or more separation grooves are formed and three or more tandem electrodes are provided, the separation groove is similarly formed. When the SI-InP layer is buried in, the isolation resistance can be similarly increased and the oscillation threshold can be reduced. Fig. 3 (a), (b)
Shows another structural example in which two tandem electrodes are provided by forming two isolation trenches. In the figure (a), the isolation trenches are formed up to the p-InP cladding layer 4 as in the embodiment shown in FIG. And there S
In the example in which the I-InP layers 21A and 21B are buried, 9A, 9B and 9C are p electrodes. In FIG. 3 (b), similar to the embodiment shown in FIG. 2, isolation trenches are formed beyond the active layer 3 up to the n-InP cladding layer 2, and SI-InP layers 22A and 22B are buried therein, and p Electrodes 9A, 9B,
This is an example in which 9C is provided.

次に、本発明にかかる上記の構造の形成方法を説明す
る。第4図(a)〜(e)は本発明にかかる構造(I)
の形成工程順斜視図であり、同図により順を追って説明
すると、 第4図(a)参照;まず、公知の液相エピタキシャル成
長(LPE)法によつてn−InP基板1上にn−InPクラッ
ド層2,InGaAsP活性層3,p−InPクラッド層4,p+−InGaAsP
キャップ層5を成長してダブルヘテロ接合構造にする。
Next, a method of forming the above structure according to the present invention will be described. 4 (a) to 4 (e) are structures (I) according to the present invention.
FIG. 4A is a perspective view showing the order of forming steps of the n-InP substrate 1 by a known liquid phase epitaxial growth (LPE) method. Cladding layer 2, InGaAsP active layer 3, p-InP cladding layer 4, p + -InGaAsP
The cap layer 5 is grown to have a double heterojunction structure.

第4図(b)参照;次いで、ストライプ状のSiO2膜マス
ク31(膜厚3000Å程度)を形成し、これを保護膜にして
n−InPクラッド層2までエッチングして幅1〜1.5μm,
高さ2.5μm程度の活性層3を含むストライプ状のレー
ザ層6を形成する。エッチング法は硝酸あるいは希塩酸
を用いるウエットエッチングによる。
4 (b); Next, a stripe-shaped SiO 2 film mask 31 (thickness of about 3000Å) is formed, and this is used as a protective film to etch the n-InP clad layer 2 to a width of 1 to 1.5 μm.
A stripe-shaped laser layer 6 including an active layer 3 having a height of about 2.5 μm is formed. The etching method is wet etching using nitric acid or dilute hydrochloric acid.

第4図(c)参照;次いで、ストライプ状のSiO2膜マス
ク31をそのまま残存させて、それをマスクにしてエッチ
ング除去部分に、有機金属熱分解気相成長(MOCDV)法
で鉄をドープしたSI−InP層11を表面が平坦になるまで
成長して埋没させる。その際、SiO2膜上に成長層が形成
されずに、所謂、選択的なエピタキシャル成長が行われ
る。
See FIG. 4 (c); then, the striped SiO 2 film mask 31 is left as it is, and the portion removed by etching is used as a mask to dope iron with metal organic thermal decomposition vapor deposition (MOCDV) method. The SI-InP layer 11 is grown and buried until the surface becomes flat. At that time, so-called selective epitaxial growth is performed without forming a growth layer on the SiO 2 film.

第4図(d)参照;次いで、SiO2膜マスク31を除去して
新たなSiO2膜マスク32を直角方向に形成し、それを保護
膜にしてp−InPクラッド層4までエッチングして幅2
μm,高さ1.7μmのストライプ状の分離溝13を形成す
る。
See FIG. 4 (d); next, the SiO 2 film mask 31 is removed to form a new SiO 2 film mask 32 in the direction perpendicular to the mask, and the p-InP clad layer 4 is etched to a width by using it as a protective film. Two
A stripe-shaped separation groove 13 having a size of μm and a height of 1.7 μm is formed.

第4図(e)参照;次いで、SiO2膜マスク32をそのまま
残存させ、これをマスクにして分離溝13部分に、気相エ
ピタキシャル成長(VPE)法で鉄をドープしたSI−InP層
21を表面が平坦になるまで成長して埋没させる。その
際、SiO2膜上には成長せずに、選択的なエピタキシャル
成長が行われる。ここに、VPE法を用いるのは狭い溝部
分への成長層の形成にはVPE法が適しているからであ
る。
See FIG. 4 (e); then, the SiO 2 film mask 32 is left as it is, and the SI-InP layer doped with iron by the vapor phase epitaxial growth (VPE) method is used in the separation groove 13 portion using this as a mask.
21 is grown and buried until the surface becomes flat. At that time, selective epitaxial growth is performed without growing on the SiO 2 film. The VPE method is used here because the VPE method is suitable for forming the growth layer in the narrow groove portion.

以下はSiO2膜マスク31を除去し、p電極9A,9Bおよび
n電極10を形成して、第1図のように完成する。
In the following, the SiO 2 film mask 31 is removed, the p electrodes 9A and 9B and the n electrode 10 are formed, and the process is completed as shown in FIG.

次に、第5図(a)〜(c)は本発明にかかる構造
(II)の形成工程順斜視図であり、同図により順を追っ
て説明すると、 第5図(a)参照;まず、前記方法と同様に、LPE法に
よつてn−InP基板1上にn−InPクラッド層2,InGaAsP
活性層3,p−InPクラッド層4,p+−InGaAsPキャップ層5
を成長する。
Next, FIGS. 5 (a) to 5 (c) are perspective views in order of the forming process of the structure (II) according to the present invention, which will be sequentially described with reference to FIG. 5 (a); Similar to the above method, the n-InP clad layer 2 and InGaAsP are formed on the n-InP substrate 1 by the LPE method.
Active layer 3, p-InP clad layer 4, p + -InGaAsP cap layer 5
To grow.

第5図(b)参照;次いで、閉込め層および分離溝を同
時にエッチングするためのSiO2膜マスク33(膜厚3000Å
程度)を形成し、これを保護膜にしてn−InPクラッド
層2までエッチングして幅1〜1.5μm,高さ2.5μm程度
の活性層3を含むストライプ状の2分割したレーザ層6
を形成する。エッチング法は硝酸あるいは希塩酸を用い
るウエットエッチングである。
See FIG. 5 (b); then, the SiO 2 film mask 33 (film thickness 3000Å) for simultaneously etching the confinement layer and the separation groove.
Is formed and is used as a protective film to etch to the n-InP clad layer 2 to form a striped laser layer 6 including an active layer 3 having a width of 1 to 1.5 μm and a height of 2.5 μm.
To form. The etching method is wet etching using nitric acid or dilute hydrochloric acid.

第5図(c)参照;次いで、SiO2膜マスク33をそのまま
残存させ、これをマスクにしてエッチング除去部分に、
MOCDV法で鉄をドープしたSI−InP層11,22を表面が平坦
になるまで成長して埋没させる。その際、SiO2膜上には
成長層が形成されず、選択エピタキシャル成長が行われ
る。
See FIG. 5 (c); next, the SiO 2 film mask 33 is left as it is, and this is used as a mask in the etching removed portion,
The SI-InP layers 11 and 22 doped with iron are grown and buried by the MOCDV method until the surface becomes flat. At that time, a growth layer is not formed on the SiO 2 film, and selective epitaxial growth is performed.

以下はSiO2膜マスク33を除去し、p電極9A,9Bおよび
n電極10を形成して、第2図のように完成する。
After that, the SiO 2 film mask 33 is removed and the p-electrodes 9A and 9B and the n-electrode 10 are formed to complete the process as shown in FIG.

この構造(II)の形成方法はSI−InP層11,22を同時に
成長して1回の埋没工程で済むために、作製が容易であ
る。
This structure (II) is easy to manufacture because the SI-InP layers 11 and 22 are grown at the same time and only one burying step is required.

[発明の効果] 以上の説明から明らかなように、本発明によれば分離
抵抗が高く、発振しきい値の低い双安定半導体レーザが
得られ、OEICなど光通信の発展に顕著に貢献するもので
ある。
[Effects of the Invention] As is clear from the above description, according to the present invention, a bistable semiconductor laser having a high separation resistance and a low oscillation threshold value can be obtained, which significantly contributes to the development of optical communication such as OEIC. Is.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明にかかる構造(I)を示す図、 第2図は本発明にかかる構造(II)を示す図、 第3図(a),(b)は本発明にかかる他の構造例を示
す図、 第4図(a)〜(e)は本発明にかかる構造(I)の形
成工程順斜視図、 第5図(a)〜(c)は本発明にかかる構造(II)の形
成工程順斜視図、 第6図は従来構造を示す図、 第7図は従来の分離溝幅と分離抵抗との関係図表、 第8図は従来の分離溝幅と発振しきい値との関係図表で
ある。 図において、 1はn−InP基板、2はn−InPクラッド層(バッフア
層)、3はInGaAsP活性層、4はp−InPクラッド層、5
はp+−InGaAsPキャップ層、6はレーザ層、8はSiO2
(絶縁膜)、9A,9B,9Cは分離したp型電極、10はn型電
極、11,21,22,21A,21B,22A,22Bは半絶縁性InP層(SI−I
nP層)、12,13は分離溝、31,32,33はSiO2膜マスク を示している。
FIG. 1 is a diagram showing a structure (I) according to the present invention, FIG. 2 is a diagram showing a structure (II) according to the present invention, and FIGS. 3 (a) and 3 (b) are other structures according to the present invention. The figure which shows an example, FIGS. 4 (a)-(e) are perspective views in order of the formation process of the structure (I) concerning this invention, FIG. 5 (a)-(c) are the structures (II) concerning this invention. FIG. 6 is a diagram showing a conventional structure, FIG. 7 is a diagram showing a relationship between a conventional isolation groove width and an isolation resistance, and FIG. 8 is a conventional isolation groove width and an oscillation threshold value. It is a relationship chart. In the figure, 1 is an n-InP substrate, 2 is an n-InP clad layer (buffer layer), 3 is an InGaAsP active layer, 4 is a p-InP clad layer, 5
Is a p + -InGaAsP cap layer, 6 is a laser layer, 8 is a SiO 2 film (insulating film), 9A, 9B, 9C are separate p-type electrodes, 10 is an n-type electrode, 11, 21, 22, 21A, 21B , 22A and 22B are semi-insulating InP layers (SI-I
nP layer), 12, 13 are isolation trenches, and 31, 32, 33 are SiO 2 film masks.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】活性層と、該活性層とヘテロ接合をなす上
下クラッド層と、該活性層に電流を注入する電極とを備
え、且つ、ストライプ状に形成されたレーザ層を有する
半導体レーザにおいて、 該ストライプ方向に直交し、且つ、少なくとも上部クラ
ッド層にまで達する分離溝によつて該電極が複数に分割
され、加えて、該ストライプ状のレーザ層の両側面と該
分離溝が半絶縁性半導体層によつて埋没されてなること
を特徴とする光双安定半導体レーザ。
1. A semiconductor laser comprising an active layer, upper and lower clad layers forming a heterojunction with the active layer, electrodes for injecting current into the active layer, and a laser layer formed in a stripe shape. , The electrode is divided into a plurality of parts by a separation groove which is orthogonal to the stripe direction and reaches at least the upper cladding layer, and in addition, both side surfaces of the stripe-shaped laser layer and the separation groove are semi-insulating. An optical bistable semiconductor laser characterized by being buried by a semiconductor layer.
【請求項2】半導体基板上に活性層と、該活性層とヘテ
ロ接合をなす上下クラッド層を備えるストライプ状のレ
ーザ層を形成する工程と、 該ストライプ状のレーザ層の両側面を埋没する半絶縁性
半導体層を形成する工程と、 該ストライプ方向に直交し、且つ、上部クラッド層にま
で達する分離溝を形成する工程と、 該分離溝部分に半絶縁性半導体層を埋没する工程とが含
まれてなることを特徴とする光双安定半導体レーザの製
造方法。
2. A step of forming a stripe-shaped laser layer comprising an active layer and upper and lower cladding layers forming a heterojunction with the active layer on a semiconductor substrate, and a semi-burying method for burying both side surfaces of the stripe-shaped laser layer. The method includes a step of forming an insulating semiconductor layer, a step of forming an isolation groove orthogonal to the stripe direction and reaching the upper cladding layer, and a step of burying a semi-insulating semiconductor layer in the isolation groove portion. A method for manufacturing an optical bistable semiconductor laser, characterized by comprising:
【請求項3】半導体基板上に活性層と、該活性層とヘテ
ロ接合をなす上下クラッド層を形成する工程と、 該活性層および上下クラッド層を選択的にエッチング
し、ストライプ状で且つ該ストライプ方向に直交する分
離溝によつて複数に分割されてなるレーザ層を形成する
工程と、 該レーザ層の両側面及び該分離溝を半絶縁性半導体層に
よつて埋没する工程が含まれてなることを特徴とする光
双安定半導体レーザの製造方法。
3. A step of forming an active layer and upper and lower clad layers forming a heterojunction with the active layer on a semiconductor substrate, and the active layer and the upper and lower clad layers are selectively etched to form stripes and the stripes. The method includes a step of forming a laser layer divided into a plurality of pieces by a separation groove orthogonal to the direction, and a step of burying both side surfaces of the laser layer and the separation groove with a semi-insulating semiconductor layer. A method for manufacturing an optical bistable semiconductor laser, comprising:
JP17958887A 1987-07-17 1987-07-17 Optical bistable semiconductor laser and manufacturing method thereof Expired - Fee Related JPH0824210B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17958887A JPH0824210B2 (en) 1987-07-17 1987-07-17 Optical bistable semiconductor laser and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17958887A JPH0824210B2 (en) 1987-07-17 1987-07-17 Optical bistable semiconductor laser and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6422089A JPS6422089A (en) 1989-01-25
JPH0824210B2 true JPH0824210B2 (en) 1996-03-06

Family

ID=16068355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17958887A Expired - Fee Related JPH0824210B2 (en) 1987-07-17 1987-07-17 Optical bistable semiconductor laser and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0824210B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2890644B2 (en) * 1990-04-03 1999-05-17 日本電気株式会社 Manufacturing method of integrated optical modulator
CN111504523B (en) * 2020-04-15 2021-07-20 深圳第三代半导体研究院 A kind of self-luminous piezoelectric device and preparation method thereof

Also Published As

Publication number Publication date
JPS6422089A (en) 1989-01-25

Similar Documents

Publication Publication Date Title
US4870468A (en) Semiconductor light-emitting device and method of manufacturing the same
JPH0824210B2 (en) Optical bistable semiconductor laser and manufacturing method thereof
JP3108183B2 (en) Semiconductor laser device and method of manufacturing the same
JP2710248B2 (en) Manufacturing method of semiconductor laser
JPH0437598B2 (en)
JPS6258692A (en) Manufacture of semiconductor light emitting device
JPH0567849A (en) Semiconductor light emitting element
JPS6255990A (en) Semiconductor laser
JPH0983077A (en) Semiconductor optical device
JP2566985B2 (en) Semiconductor device and manufacturing method thereof
JPS6241437B2 (en)
JPH0697085A (en) Method for manufacturing semiconductor device
JPH08222809A (en) Semiconductor light emitting device
JPH0521891A (en) Method of manufacturing buried structure semiconductor laser
JPH01309393A (en) Semiconductor laser device and its manufacture
JPH05175599A (en) Semiconductor laser and manufacturing method thereof
JPH0697707B2 (en) Semiconductor light emitting device
JPH06350188A (en) Semiconductor laser device
JPS6354234B2 (en)
JPS59168687A (en) Semiconductor laser and manufacture thereof
JPS622718B2 (en)
JPH0632324B2 (en) Optical bistable semiconductor laser
JPH0697603A (en) Semiconductor laser and its manufacture
JPH0680863B2 (en) Semiconductor laser
JPS61280695A (en) Semiconductor laser

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees