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JPH0824256B2 - Driving circuit for pnpn semiconductor device with gate - Google Patents
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JPH0824256B2 - Driving circuit for pnpn semiconductor device with gate - Google Patents

Driving circuit for pnpn semiconductor device with gate

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Publication number
JPH0824256B2
JPH0824256B2 JP31117888A JP31117888A JPH0824256B2 JP H0824256 B2 JPH0824256 B2 JP H0824256B2 JP 31117888 A JP31117888 A JP 31117888A JP 31117888 A JP31117888 A JP 31117888A JP H0824256 B2 JPH0824256 B2 JP H0824256B2
Authority
JP
Japan
Prior art keywords
pnpn
gate
pnpn semiconductor
semiconductor element
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP31117888A
Other languages
Japanese (ja)
Other versions
JPH02156231A (en
Inventor
義春 田代
健一 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31117888A priority Critical patent/JPH0824256B2/en
Publication of JPH02156231A publication Critical patent/JPH02156231A/en
Publication of JPH0824256B2 publication Critical patent/JPH0824256B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はゲート付pnpn素子を駆動するための回路に関
する。
The present invention relates to a circuit for driving a gated pnpn element.

(従来の技術) 光コンピュータ、光交換あるいは光・電気集積回路の
分野に用いることができ光スイッチや光メモリー、ある
いは波長変換の機能を有するpnpn半導体素子が注目され
ている。pnpn半導体素子は2つのトランジスタが互いに
コレクターとベースを接合し合った素子と考えることが
できる。そのために、この素子は印加電圧が大きくなる
とトリガ(光あるいは電気)により発生した電流が基に
なりトランジスタの正帰還効果で、ON状態に移行する。
ON状態では内部にある3個のpn接合全てが順バイアス状
態となる。pnpn半導体素子をON状態からOFF状態へ戻す
ためには順バイアスとなっている3個のpn接合から、過
剰キャリアをす早く追い出すか、再結合させる必要があ
る。pnpn半導体素子から高速に過剰キャリアを追い出す
方法として、pnpn半導体素子にゲートを設け、そのゲー
トから過剰キャリアを追い出す方式が考えられており、
本発明の発明者らにより特開昭63−244929号公報により
解決されている。第2図にその従来知られているゲート
付pnpn半導体素子の駆動回路を示す。この駆動回路は、
pnpn半導体素子1のアノード電極4とカソード電極5の
間に負荷抵抗2と電源3とが直列に接続されたpnpn素子
1自体を動かす電源回路と、pnpn半導体素子1のアノー
ド電極4とゲート電極6との間に、金属−n−GaAs接触
型のショットキーダイオード7のn−GaAs側をpnpn半導
体素子1のアノード電極4に、ショットキーダイオード
7の金属側をpnpn半導体素子1のゲート電極6に接続さ
れたゲート回路部とで構成されている。電源3によりpn
pn半導体素子1のアノード電極に正の電圧を印加し、増
加していくとpnpn半導体素子はON状態となる。そのとき
には、pnpn半導体素子1のゲート電極6とアノード電極
4との間に接続されたショットキーダイオード7には、
アノード電極4に接続されたn−GaAs側に正の電圧が印
加され、ショットキーダイオード7は逆バイアス状態と
なり、電流は流れない。これによりpnpn半導体素子1の
動作に影響を及ぼさない。次にpnpn半導体素子1をON状
態からOFF状態へ戻すために、電源3によりpnpn半導体
素子のアノード電極に負の電圧を印加する。そのときに
は、pnpn半導体素子1のゲート電極6とアノード電極4
との間に接続されたショットキーダイオードには、アノ
ード電極4に接続されたn−GaAs側に負の電圧が印加さ
れ、ショットキーダイオード7は順バイアス状態とな
り、pnpn半導体素子のゲート電極4は同素子のアノード
電極と短絡されることになる。それによってpnpn半導体
素子のp2領域に蓄積されていた正孔がpnpn半導体素子の
p1−n1−p2領域における内部電界によりゲート電極4を
通じて外部に流れ出す。それに伴い、pnpn半導体素子の
n1領域に蓄積されていた電子もpnpn半導体素子内部にお
ける電荷の中性条件を満足するために消滅して行く。そ
のためにpnpn半導体素子は、この回路により、ON状態か
らOFF状態への戻りがす早く行なわれることになる。
(Prior Art) Attention has been paid to a pnpn semiconductor element that can be used in the fields of optical computers, optical switching or optical / electrical integrated circuits, and has an optical switch, an optical memory, or a wavelength conversion function. A pnpn semiconductor device can be considered as a device in which two transistors have their collectors and bases joined to each other. Therefore, when the applied voltage increases, this element shifts to the ON state by the positive feedback effect of the transistor based on the current generated by the trigger (light or electricity).
In the ON state, all three pn junctions inside are in a forward bias state. In order to return the pnpn semiconductor device from the ON state to the OFF state, it is necessary to expel excess carriers from the three forward-biased pn junctions as quickly as possible or to rejoin them. As a method of expelling excess carriers from a pnpn semiconductor element at high speed, a method of providing a gate on the pnpn semiconductor element and expelling excess carriers from the gate is considered.
This has been solved by the inventors of the present invention by Japanese Patent Laid-Open No. 63-244929. FIG. 2 shows a conventionally known driving circuit of a pnpn semiconductor device with a gate. This drive circuit
A power supply circuit for driving a pnpn element 1 itself, in which a load resistor 2 and a power supply 3 are connected in series between an anode electrode 4 and a cathode electrode 5 of the pnpn semiconductor element 1, and an anode electrode 4 and a gate electrode 6 of the pnpn semiconductor element 1. Between the n-GaAs side of the metal-n-GaAs contact type Schottky diode 7 is the anode electrode 4 of the pnpn semiconductor element 1, and the metal side of the Schottky diode 7 is the gate electrode 6 of the pnpn semiconductor element 1. And a connected gate circuit section. Pn by power supply 3
When a positive voltage is applied to the anode electrode of the pn semiconductor element 1 and increases, the pnpn semiconductor element turns on. At that time, in the Schottky diode 7 connected between the gate electrode 6 and the anode electrode 4 of the pnpn semiconductor element 1,
A positive voltage is applied to the n-GaAs side connected to the anode electrode 4, the Schottky diode 7 is in a reverse bias state, and no current flows. This does not affect the operation of the pnpn semiconductor device 1. Next, in order to return the pnpn semiconductor element 1 from the ON state to the OFF state, a negative voltage is applied from the power supply 3 to the anode electrode of the pnpn semiconductor element. At that time, the gate electrode 6 and the anode electrode 4 of the pnpn semiconductor element 1 are
A negative voltage is applied to the n-GaAs side connected to the anode electrode 4 of the Schottky diode connected between the Schottky diode and the Schottky diode 7, the Schottky diode 7 is in a forward bias state, and the gate electrode 4 of the pnpn semiconductor element is It will be short-circuited with the anode electrode of the same element. As a result, holes accumulated in the p 2 region of the pnpn semiconductor device are
It flows out through the gate electrode 4 due to the internal electric field in the p 1 -n 1 -p 2 region. Along with that, the pnpn semiconductor device
The electrons accumulated in the n 1 region also disappear to satisfy the neutral condition of the charge inside the pnpn semiconductor device. For this reason, the pnpn semiconductor element is quickly returned from the ON state to the OFF state by this circuit.

(発明が解決しようとする問題点) 光コンピュータ、光交換あるいは光・電気集積回路の
分野に用いることができ光スイッチや光メモリー、ある
いは波長変換の機能を有するpnpn半導体素子は、例えば
ジー・ダブル・テーラら(G.W.Tayloretal.)によりア
プライド・フィジックス・レターズ(Apple.Phys.Let
t.)誌、第50(2)巻、1987年、第338頁〜第340頁に記
載されている。
(Problems to be solved by the invention) An optical switch, an optical memory, or a pnpn semiconductor element having a wavelength conversion function, which can be used in the fields of optical computers, optical switching or optical / electrical integrated circuits, is, for example,・ Applied Physics Letters (Apple.Phys.Let) by Thera et al. (GWTaylor et al.)
t.), Vol. 50 (2), 1987, pp. 338-340.

この素子は印加電圧が大きくなるとトリガ光により発
生した電流が基になりトランジスタの正帰還効果で、ON
状態に移行する。ON状態では内部にある3個のpn接合全
てが順バイアス状態となる。そのときのpnpn素子のバン
ド構造は、半導体レーザ(LD)、発光ダイオード(LE
D)と同様となるために、ON状態でのpnpn半導体素子は
発光を生じる。
This element is turned on by the positive feedback effect of the transistor based on the current generated by the trigger light when the applied voltage increases.
Transition to the state. In the ON state, all three pn junctions inside are in a forward bias state. At that time, the band structure of the pnpn element is a semiconductor laser (LD), a light emitting diode (LE
Since it is the same as in D), the pnpn semiconductor element in the ON state emits light.

このpnpn半導体素子はp1領域はp型Al0.4Ga0.6Asでn1
領域はn−GaAsで、p2領域はp−GaAs、n2領域はn−Al
0.4Ga0.6Asにより形成されている。この素子の光吸収と
発光はn1とp2領域で行なわれる。受光機能はこの層の禁
制帯波超よりも短い波長でなされ、発光は禁制帯波長程
度で生じるので、光アンプや波長変換素子として働かせ
ると常に入力光9よりも出力光10の波長が長波長側にシ
フトしていくことになる。また発光をLD光で発生される
場合には活性層は薄くする必要があり同一層を利用した
受光では受光効率(感度)が悪くなる様な発光・受光で
の特性のトレードオフを生じる問題がある。しかしこの
様な様子な問題に対して従来知られた駆動回路は、ON状
態からOFF状態へ戻すときには内部に蓄積されたキャリ
アを引き抜く効果により高速化する効果があるがOFF状
態からON状態へ移る場合には素子特性をカバーする効果
はなく特性改善効果は得られなかった。
In this pnpn semiconductor device, the p 1 region is p type Al 0.4 Ga 0.6 As and n 1
The region is n-GaAs, the p 2 region is p-GaAs, and the n 2 region is n-Al.
It is formed of 0.4 Ga 0.6 As. Light absorption and emission of this device are performed in the n 1 and p 2 regions. The light receiving function is performed at a wavelength shorter than the forbidden band in this layer, and the light emission occurs at about the forbidden band wavelength. Therefore, when operating as an optical amplifier or wavelength conversion element, the wavelength of the output light 10 is always longer than that of the input light 9. It will shift to the side. In addition, when the emitted light is generated by LD light, the active layer needs to be thin, and there is a problem in that there is a trade-off in the characteristics of light emission and light reception, such that the light reception efficiency (sensitivity) deteriorates with light reception using the same layer. is there. However, to solve this kind of problem, the conventionally known drive circuit has the effect of speeding up by the effect of extracting the carriers accumulated inside when returning from the ON state to the OFF state, but it shifts from the OFF state to the ON state. In this case, there was no effect of covering the device characteristics and no effect of improving the characteristics was obtained.

本発明の目的は従来のかかる問題点を解決し、ON状態
からOFF状態に高速に戻す効果を損なうことなく、pnpn
半導体のもつ発光と受光の間のトレードオフをカバーす
ることが可能な駆動回路を提供することにある。
The object of the present invention is to solve the above-mentioned problems of the prior art, and to keep the effect of returning from the ON state to the OFF state at high speed with pnpn
An object of the present invention is to provide a drive circuit capable of covering the trade-off between light emission and light reception of a semiconductor.

(問題点を解決するための手段) 本発明は、pnpn接合を有し、n型ベース領域、p型ベ
ース領域いずれか、または両方にゲート電極が設けられ
たpnpn半導体素子を駆動するための回路において、整流
特性を有し光を受けると電力を発生する受光素子が該pn
pn素子のp型ゲート−アノード間にp型ゲートからアノ
ードに向かう電流のみが流れる整流極性方向に接続され
ているか、または、n型ゲート−カソード間にカソード
からn型ゲートに向う電流のみが流れる整流極性方向に
接続され、かつ、該pnpn半導体素子のアノード−カソー
ド間に電源及び負荷抵抗が直列に接続されていることを
特徴とするゲート付pnpn半導体素子の駆動回路である。
(Means for Solving the Problems) The present invention relates to a circuit for driving a pnpn semiconductor device having a pnpn junction and having a gate electrode provided in either or both of an n-type base region and a p-type base region. At pn, the light receiving element that has rectifying characteristics and generates power when receiving light is
Only the current flowing from the p-type gate to the anode of the pn element flows in the rectifying polarity direction, or only the current flows from the cathode to the n-type gate between the n-type gate and the cathode. A driving circuit for a pnpn semiconductor device with a gate, characterized in that the power supply and the load resistance are connected in series between the anode and the cathode of the pnpn semiconductor device in the rectifying polarity direction.

(作用) 上記の手段によれば、p型ゲート−アノード間、ある
いはn型ゲート−カソード間に接続された受光素子をpn
pn半導体素子がOFF状態からON状態となるときには入力
する光を受光することに利用し、キャリアをpnpn半導体
素子に注入することでpnpn半導体素子をON状態とするこ
とができる。従ってpnpn半導体素子の持っている発光特
性と受光特性のトレードオフをカバーすることが可能と
なる。
(Operation) According to the above means, the light receiving element connected between the p-type gate and the anode or between the n-type gate and the cathode is connected to the pn
When the pn semiconductor element is changed from the OFF state to the ON state, it is used for receiving the input light, and the pnpn semiconductor element can be turned on by injecting carriers into the pnpn semiconductor element. Therefore, it becomes possible to cover the trade-off between the light emitting characteristic and the light receiving characteristic of the pnpn semiconductor element.

(実施例) 以下、本発明の実施例について図面を参照して詳細に
説明する。第1図は本発明の駆動回路を示す。この駆動
回路は、第2図でpnpn半導体素子1のアノード電極4と
ゲート電極6との間に接続されている金属−n−GaAs接
触型のショットキーダイオード7の代わりに、p−n接
合を有するInGaAsフォトダイオード(吸収端1.62μm)
8をフォトダイオード8のp型タイプをpnpn半導体素子
1のゲート電極6側に、フォトダイオード8のn型タイ
プをpnpn半導体素子1のアノード側に接続し、それ以外
は第2図と同じ構成となっている。この駆動回路におい
てpnpn半導体素子1をON状態からOFF状態へ戻すときに
はpn接合フォトダイオードも整流特性を有するためにア
ノード側に負の電圧を印加するとフォトダイオードは順
バイアス状態となり内部のキャリアをpnpn半導体素子1
の外に引き出し、従来の駆動回路と同様な効果を有する
ことになる。更に、電源3によりpnpn半導体素子1のア
ノード電極に正の電圧を印加すると、フォトダイオード
8には逆バイアスが印加される。フォトダイオード8に
光が入射されない状態では電流が流れないために従来技
術と同様にpnpn半導体素子1にはなにも影響を及ぼさな
い。しかしフォトダイオードに入力光11が入射される
と、フォトダイオードから光吸収に伴う電流が流れる。
その結果ゲート電極6を通してp2領域にキャリアが注入
され、pnpn半導体素子1がON状態となり出力光10が発生
する。このときフォトダイオード8は吸収端が1.62μm
であり、吸収端よりも短波長の光を受光可能であり、pn
pn半導体素子の発光は0.87μmで生ずることから入力光
11よりも出力光10の波長が常に長波長側となる問題は解
決でき、波長変換も可能となる。更に、受光はフォトダ
イオード8で行なっているためにpnpn半導体素子1は受
光特性は考慮せず発光特性のみを最適化が可能となり、
発光と受光のトレードオフの問題の問題も解決すること
が可能となる。尚本実施例ではInGaAsフォトダイオード
を用いたが特に限定するものではない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a driving circuit of the present invention. This drive circuit has a pn junction instead of the metal-n-GaAs contact type Schottky diode 7 connected between the anode electrode 4 and the gate electrode 6 of the pnpn semiconductor element 1 in FIG. InGaAs photodiode (absorption edge 1.62 μm)
8 is connected to the gate electrode 6 side of the pnpn semiconductor element 1 for the p-type of the photodiode 8 and the anode side of the pnpn semiconductor element 1 for the n-type of the photodiode 8, and otherwise the same configuration as in FIG. Has become. In this drive circuit, when the pnpn semiconductor element 1 is returned from the ON state to the OFF state, the pn junction photodiode also has a rectifying characteristic. Therefore, if a negative voltage is applied to the anode side, the photodiode becomes a forward bias state and internal carriers are pnpn semiconductor. Element 1
And has the same effect as a conventional drive circuit. Further, when a positive voltage is applied to the anode electrode of the pnpn semiconductor element 1 by the power supply 3, a reverse bias is applied to the photodiode 8. Since no current flows in the state where no light is incident on the photodiode 8, it does not affect the pnpn semiconductor element 1 as in the prior art. However, when the input light 11 is incident on the photodiode, a current due to light absorption flows from the photodiode.
As a result, carriers are injected into the p 2 region through the gate electrode 6, the pnpn semiconductor element 1 is turned on, and output light 10 is generated. At this time, the photodiode 8 has an absorption edge of 1.62 μm.
And can receive light with a shorter wavelength than the absorption edge.
Since the pn semiconductor device emits light at 0.87 μm, the input light
The problem that the wavelength of the output light 10 is always longer than that of 11 can be solved, and wavelength conversion can be performed. Further, since light is received by the photodiode 8, the pnpn semiconductor element 1 can optimize only the light emitting characteristics without considering the light receiving characteristics.
It is also possible to solve the problem of the trade-off between light emission and light reception. Although the InGaAs photodiode is used in this embodiment, it is not particularly limited.

更に、p型ゲート−アノード間にフォトダイオード接
続した例を用いて説明したがn型ゲート−カソード間に
接続した場合も有効であり、上記を同時に接続しても有
効であり、更に各々の波長を変えることにより複数の波
長変換効果も有することが可能となる。
Furthermore, although an example in which a photodiode is connected between the p-type gate and the anode has been described, the case where the photodiode is connected between the n-type gate and the cathode is also effective, and it is effective to connect the above at the same time. It becomes possible to have a plurality of wavelength conversion effects by changing

(発明の効果) 以上詳細に述べた通り、本発明によれば、従来の回路
の効果を損なうことなく更にpnpn半導体素子の発光と受
光のトレードオフの問題を解決できる効果を有する。
(Effects of the Invention) As described in detail above, according to the present invention, it is possible to further solve the problem of trade-off between light emission and light reception of a pnpn semiconductor element without impairing the effects of the conventional circuit.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す駆動回路を示す図、第
2図は従来知られている駆動回路を示す図である。 1……pnpn半導体素子、2……負荷抵抗、3……電源、
4……アノード電極、5……カソード電極、6……ゲー
ト電極、7……ショットキーダイオード、8……フォト
ダイオード。
FIG. 1 is a diagram showing a driving circuit showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventionally known driving circuit. 1 ... pnpn semiconductor element, 2 ... load resistance, 3 ... power supply,
4 ... Anode electrode, 5 ... Cathode electrode, 6 ... Gate electrode, 7 ... Schottky diode, 8 ... Photodiode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】pnpn接合を有し、n型ベース領域、p型ベ
ース領域のいずれか、または両方にゲート電極が設けら
れたpnpn半導体素子を駆動するための回路において、整
流特性を有し光を受けると電力を発生する受光素子が該
pnpn素子のp型ゲート・アノード間にp型ゲートからア
ノードに向かう電流のみが流れる整流極性方向に接続さ
れているか、または、n型ゲート・カソード間にカソー
ドからn型ゲートに向かう電流のみが流れる整流極性方
向に接続され、かつ、該pnpn半導体素子のアノード・カ
ソード間に電源及び負荷抵抗が直列に接続されているこ
とを特徴とするゲート付pnpn半導体素子の駆動回路。
1. A circuit for driving a pnpn semiconductor element having a pnpn junction and having a gate electrode provided in either or both of an n-type base region and a p-type base region, and having a rectifying characteristic The light receiving element that generates power when receiving
Only the current flowing from the p-type gate to the anode flows in the rectifying polarity direction between the p-type gate and the anode of the pnpn element, or only the current flowing from the cathode to the n-type gate flows between the n-type gate and the cathode. A driving circuit for a pnpn semiconductor device with a gate, which is connected in the direction of rectification polarity and in which a power supply and a load resistor are connected in series between the anode and the cathode of the pnpn semiconductor device.
JP31117888A 1988-12-08 1988-12-08 Driving circuit for pnpn semiconductor device with gate Expired - Lifetime JPH0824256B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31117888A JPH0824256B2 (en) 1988-12-08 1988-12-08 Driving circuit for pnpn semiconductor device with gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31117888A JPH0824256B2 (en) 1988-12-08 1988-12-08 Driving circuit for pnpn semiconductor device with gate

Publications (2)

Publication Number Publication Date
JPH02156231A JPH02156231A (en) 1990-06-15
JPH0824256B2 true JPH0824256B2 (en) 1996-03-06

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JP31117888A Expired - Lifetime JPH0824256B2 (en) 1988-12-08 1988-12-08 Driving circuit for pnpn semiconductor device with gate

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JP7741539B2 (en) * 2021-08-10 2025-09-18 国立研究開発法人産業技術総合研究所 Semiconductor device and method for manufacturing the same

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