JPH0828491B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0828491B2 JPH0828491B2 JP62117780A JP11778087A JPH0828491B2 JP H0828491 B2 JPH0828491 B2 JP H0828491B2 JP 62117780 A JP62117780 A JP 62117780A JP 11778087 A JP11778087 A JP 11778087A JP H0828491 B2 JPH0828491 B2 JP H0828491B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- cdte
- well region
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 〔概要〕 CdTeの基板に所定パターンの水銀・カドミウム・テル
ル(Hg1-XCdXTe)よりなる島状のウェル領域を形成し、
該ウェル領域内にP−N接合を形成してホトダイオード
を形成し、該ホトダイオードとSi基板に形成した電荷転
送素子のようなマルチプレクサの入力部とをインジウム
金属柱で接続して一体化したハイブリッド型赤外検知器
のCdTe基板のうちの島状のウェル領域を残留させた状態
でCdTe結晶のみを選択的にエッチング除去して半導体装
置を製造することで、光電変換素子に於けるクロストー
クの発生を無くし、この半導体装置を77°Kの動作時の
低温状態より室温の間の温度サイクルで動作させた場合
に、CdTe基板とSi基板との熱膨張係数の相違によって前
記In金属柱に塑性変形が生じないようにする。DETAILED DESCRIPTION OF THE INVENTION [Outline] An island-shaped well region made of a predetermined pattern of mercury, cadmium, and tellurium (Hg 1-X Cd X Te) is formed on a CdTe substrate,
A hybrid type in which a P-N junction is formed in the well region to form a photodiode, and the photodiode and an input portion of a multiplexer such as a charge transfer device formed on a Si substrate are connected by an indium metal pillar to be integrated. Crosstalk occurs in the photoelectric conversion element by selectively removing the CdTe crystal by etching while leaving the island-shaped well region of the CdTe substrate of the infrared detector to manufacture a semiconductor device. When this semiconductor device is operated in a temperature cycle between a low temperature state at 77 ° K and a room temperature, the In metal column is plastically deformed due to the difference in thermal expansion coefficient between the CdTe substrate and the Si substrate. So that it does not occur.
本発明は半導体装置の製造方法に係り、特にCdTe基板
にホトダイオードをアレイ状に形成した赤外線検知素子
と該検知素子の検知信号の信号処理回路を設けたSi基板
を金属柱で接続したハイブリッド型赤外検知器の製造方
法に関する。The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a hybrid type red connecting a metal substrate to an infrared detection element in which photodiodes are formed in an array on a CdTe substrate and a Si substrate provided with a signal processing circuit for a detection signal of the detection element. The present invention relates to a method for manufacturing an outer detector.
水銀・カドミウム・テルルよりなる化合物半導体基板
にホトダイオードをアレイ状に配設した赤外線検知素子
の出力部と、Si基板に設けられ該検知素子で検知された
検知信号を信号処理する電荷転送素子の入力部とをIn金
属柱で接続し、前記赤外線検知素子と電荷転送素子とを
一体化したハイブリッド型赤外検知器の一種であるIRCC
D(赤外検知用電荷転送装置)は周知である。An output part of an infrared detection element in which photodiodes are arranged in an array on a compound semiconductor substrate made of mercury, cadmium and tellurium, and an input of a charge transfer element which is provided on a Si substrate and which processes a detection signal detected by the detection element. IRCC which is a kind of hybrid type infrared detector in which the infrared detection element and the charge transfer element are integrated with each other by an In metal column.
D (infrared detection charge transfer device) is well known.
このようなIRCCDに於いてクロストークの発生を無く
し、77°Kの低温の動作時と室温の非動作時の間の温度
サイクルの間に化合物半導体基板とSi基板との熱膨張係
数の相違によって両者の基板を接続しているIn金属柱に
塑性変形を生じない装置が要望されている。In such an IRCCD, the occurrence of crosstalk is eliminated, and due to the difference in the thermal expansion coefficient between the compound semiconductor substrate and the Si substrate during the temperature cycle between the low temperature operation at 77 ° K and the non-operation at room temperature There is a demand for a device that does not cause plastic deformation in the In metal columns connecting the substrates.
従来、このような赤外線検知素子アレイを形成する場
合、第2図に示すようにCdTe基板1に所定パターンのホ
トレジスト膜2を形成し、該ホトレジスト膜2をマスク
としてブロム(Br2)とメチルアルコール(CH3OH)より
なるエッチング液を用いて溝3を形成する。Conventionally, when forming such an infrared detecting element array, a photoresist film 2 having a predetermined pattern is formed on a CdTe substrate 1 as shown in FIG. 2, and the photoresist film 2 is used as a mask for bromine (Br 2 ) and methyl alcohol. The groove 3 is formed using an etching solution composed of (CH 3 OH).
次いで第3図に示すように該溝3を含む基板1上に液
相エピタキシャル成長方法等を用いてP型のHg1-XCdXTe
よりなる結晶4を形成する。Then, as shown in FIG. 3, P-type Hg 1-X Cd X Te is formed on the substrate 1 including the groove 3 by a liquid phase epitaxial growth method or the like.
To form a crystal 4.
次いで第4図に示すように該基板表面を研磨し、該基
板1に島状のウェル領域5を形成する。Next, as shown in FIG. 4, the surface of the substrate is polished to form island-shaped well regions 5 on the substrate 1.
次いで第5図に示すように該基板上に所定パターンの
ホトレジスト膜6を形成し、このホトレジスト膜6をマ
スクとして用いてイオン注入法により該ウェル領域5に
N型の不純物となるボロン(B)原子をイオン注入して
N型層7を形成し、P−N接合を形成してホトダイオー
ド8を形成する。Next, as shown in FIG. 5, a photoresist film 6 having a predetermined pattern is formed on the substrate, and boron (B) which becomes an N-type impurity in the well region 5 is formed by ion implantation using the photoresist film 6 as a mask. Atoms are ion-implanted to form an N-type layer 7, and a P-N junction is formed to form a photodiode 8.
次いで第6図に示すように、前記したホトレジスト膜
6を除去した後、前記したホトダイオード8のN型層7
よりなる出力部とSi基板9に形成された電荷転送装置の
入力ダイオード10の間と、ホトダイオード8が形成され
ているウェル領域5と、電荷転送装置が形成されている
Si基板9に設けられたアース接続用のバスライン11とを
それぞれIn金属柱12,13を用いて接続している。Next, as shown in FIG. 6, after the photoresist film 6 is removed, the N-type layer 7 of the photodiode 8 is removed.
Between the output section and the input diode 10 of the charge transfer device formed on the Si substrate 9, the well region 5 in which the photodiode 8 is formed, and the charge transfer device are formed.
The bus line 11 for earth connection provided on the Si substrate 9 is connected using In metal columns 12 and 13, respectively.
然し、このような方法で形成したIRCCDは隣接するホ
トダイオード8の間に入射したホトンは光電変換されて
キャリアとなり、そのキャリアは隣接するホトダイオー
ドに流れこんで、両方のホトダイオードの各々で検知さ
れる検知信号にクロストークを発生させる問題がある。However, in the IRCCD formed by such a method, the photons incident between the adjacent photodiodes 8 are photoelectrically converted into carriers, and the carriers flow into the adjacent photodiodes, and are detected by both photodiodes. There is a problem of causing crosstalk in the signal.
またホトダイオード8よりなる赤外線検知素子を形成
したCdTeの基板の熱膨張率(線膨張係数)は、該装置の
動作温度の77゜Kに於いては+0.9×10-6/Kで、電荷転送
装置を形成しているSi基板8は−0.5×10-6/Kで、また
非動作時の297゜KではCdTe基板の熱膨張率は5.0×10-6/K
で、Si基板の熱膨張率は2.5×10-6/Kで両方の基板に於
いて熱膨張率がそれぞれ異なる。The thermal expansion coefficient (coefficient of linear expansion) of the CdTe substrate on which the infrared detection element composed of the photodiode 8 is formed is + 0.9 × 10 -6 / K at 77 ° K, which is the operating temperature of the device. The Si substrate 8 forming the transfer device is -0.5 × 10 -6 / K, and the thermal expansion coefficient of the CdTe substrate is 5.0 × 10 -6 / K at 297 ° K when not operating.
Thus, the coefficient of thermal expansion of the Si substrate is 2.5 × 10 -6 / K, and the coefficient of thermal expansion is different for both substrates.
そのため、このIRCCDの動作時の77゜Kの低温より室温
の297゜Kの間の温度サイクルで動作させた時、両者の基
板の熱膨張係数が異なるために、基板間を接続している
In金属柱に塑性変形が発生する問題がある。Therefore, when the IRCCD is operated at a temperature cycle between 297 ° K at room temperature and 77 ° K at room temperature, the thermal expansion coefficients of both substrates are different, so the substrates are connected.
In There is a problem that plastic deformation occurs in metal columns.
本発明は上記した問題点を除去し、クロストークが発
生せず、In金属柱で接続される両方の基板の熱膨張率の
差によるIn金属柱の塑性変形が生じないようにした半導
体装置の製造方法の提供を目的とする。The present invention eliminates the above-mentioned problems, does not cause crosstalk, and prevents plastic deformation of the In metal columns due to the difference in the thermal expansion coefficient of both substrates connected by the In metal columns. The purpose is to provide a manufacturing method.
上記目的を達成するための本発明の半導体装置の製造
方法は、カドミウムテルル基板に所定パターンの水銀・
カドミウム・テルル結晶層よりなり、P−N接合を形成
したウェル領域を形成して光電変換素子を形成後、該光
電変換素子の出力部と他方の半導体基板に形成したマル
チプレクサの入力部とを金属柱にて接続した後、前記光
電変換素子を形成している基板のカドミウムテルル結晶
のみを選択的に除去する。A method for manufacturing a semiconductor device of the present invention to achieve the above object is to provide a cadmium tellurium substrate with a predetermined pattern of mercury.
After forming a photoelectric conversion element by forming a well region formed of a cadmium tellurium crystal layer and having a P-N junction formed therein, the output section of the photoelectric conversion element and the input section of the multiplexer formed on the other semiconductor substrate are made of metal. After connecting by pillars, only the cadmium tellurium crystal of the substrate forming the photoelectric conversion element is selectively removed.
CdTe基板に形成されているホトダイオードの出力部と
電荷転送装置の入力部とをIn金属柱で接続した後、ホト
ダイオードが形成されているCdTe基板をCdTe結晶は選択
的にエッチングしHg1-XCdXTe結晶はエッチングしないよ
うなエッチング選択比を有するエッチング液、即ち特願
昭57-191058号に於いて本出願人が出願したエッチング
液にてP−N接合を形成したHg1-XCdXTeのウェル領域を
有するCdTe基板をエッチングする。するとCdTe結晶のみ
が選択的にエッチングされるので、ウェル領域のみ基板
より分離される形となり、クロストークの発生が無い半
導体装置が得られる。更に上記の方法によりCdTeの基板
の容積が少なくなるので、CdTeの基板の熱膨張率とSi基
板の熱膨張率の差によってIn金属柱が塑性変形を起こす
事故がなくなる。After connecting the output part of the photodiode formed on the CdTe substrate and the input part of the charge transfer device with an In metal column, the CdTe substrate on which the photodiode is formed is selectively etched by the CdTe crystal and Hg 1-X Cd The X Te crystal is an Hg 1-X Cd X which forms a PN junction with an etching solution having an etching selection ratio such that it does not etch, that is, the etching solution filed by the applicant in Japanese Patent Application No. 57-191058. Etch CdTe substrate with Te well region. Then, only the CdTe crystal is selectively etched, so that only the well region is separated from the substrate, and a semiconductor device without crosstalk is obtained. Further, since the volume of the CdTe substrate is reduced by the above method, the In metal column is not plastically deformed due to the difference in the coefficient of thermal expansion between the CdTe substrate and the Si substrate.
以下、図面を用いながら本発明の一実施例につき詳細
に説明する。Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
本発明の半導体装置の製造方法の工程は前記した第2
図より第6図迄は同様にする。The process of the method for manufacturing a semiconductor device according to the present invention is the same as the above-described second step.
From FIG. 6 to FIG. 6, the same applies.
次いで第1図に示すようにIn金属柱12、およびIn金属
柱13でSi基板9と接続されたCdTeの基板1を弗化水素酸
(HF)と硝酸(HNO3)と酢酸(CH3COOH)と水(H2O)と
が、重量比で(2〜5):(3〜5):6:6の混合比にな
るように混合したエッチング液、即ち本出願人が、特願
昭57-191058号に於いて出願したエッチング液に浸漬さ
せてエッチングする。Then, as shown in FIG. 1, the CdTe substrate 1 connected to the Si substrate 9 by the In metal column 12 and the In metal column 13 was treated with hydrofluoric acid (HF), nitric acid (HNO 3 ) and acetic acid (CH 3 COOH). ) And water (H 2 O) are mixed in a weight ratio of (2 to 5) :( 3 to 5): 6: 6, that is, the applicant of the present invention, Etching is performed by immersing in the etching solution applied for in No. 57-191058.
するとこのエッチング液は、ウェル領域5を形成する
Hg1-XCdXTeの結晶はエッチングしない状態で、CdTe結晶
のみを選択的にエッチングし、Hg1-XCdXTeのウェル領域
5が残った状態で、ウェル領域5以外のCdTe基板が選択
的にエッチングされる。Then, this etching solution forms the well region 5.
With the Hg 1-X Cd X Te crystal not etched, only the CdTe crystal was selectively etched, leaving the well region 5 of Hg 1-X Cd X Te, and the CdTe substrate other than the well region 5 was removed. It is selectively etched.
このようにすれば、CdTe基板の部分は無くなるため、
ホトダイオード8を形成したウェル領域5が完全に絶縁
分離されるため、クロストークの現象が発生しない。ま
たこの半導体装置を77°Kの動作時と297°Kの非動作
時の温度サイクル内で使用した場合、CdTe基板結晶が除
去されているのでSi基板とCdTe基板の熱膨張率の相違で
In金属柱が塑性変形を起こす事故がなくなり、高信頼度
の半導体装置が得られる効果がある。By doing this, the part of the CdTe substrate disappears,
Since the well region 5 in which the photodiode 8 is formed is completely insulated and separated, the phenomenon of crosstalk does not occur. Also, when this semiconductor device is used in a temperature cycle of 77 ° K operation and 297 ° K non-operation, the CdTe substrate crystal is removed, so that the difference in the thermal expansion coefficient between the Si substrate and the CdTe substrate is caused.
In It is possible to obtain a highly reliable semiconductor device by eliminating the accident that plastic deformation of the metal pillar occurs.
以上述べたように本発明の半導体装置の製造方法によ
れば、金属バンプの塑性変形が生じなく、クロストーク
の発生しない半導体装置が得られる効果がある。As described above, according to the method for manufacturing a semiconductor device of the present invention, there is an effect that a plastic deformation of the metal bump does not occur and a semiconductor device in which crosstalk does not occur can be obtained.
第1図は本発明の半導体装置の製造方法を示す断面図、 第2図より第6図までは従来の半導体装置の製造方法を
示す断面図である。 図に於いて、 5はウェル領域、7はN型層、8はホトダイオード、9
はSi基板、10は入力ダイオード、11はバスライン、12,1
3は金属柱を示す。FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 6 are sectional views showing a conventional method for manufacturing a semiconductor device. In the figure, 5 is a well region, 7 is an N-type layer, 8 is a photodiode, and 9 is
Is Si substrate, 10 is input diode, 11 is bus line, 12,1
3 indicates a metal column.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−42175(JP,A) 特開 昭61−214462(JP,A) 特開 昭62−232958(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-57-42175 (JP, A) JP-A-61-214462 (JP, A) JP-A-62-232958 (JP, A)
Claims (1)
を設けた水銀・カドミウム・テルルよりなるウェル領域
(5)を形成して光電変換素子を形成後、該光電変換素
子の出力部と他方の半導体基板(9)に形成したマルチ
プレクサの入力部とを金属柱(12)にて接続し、その後
前記光電変換素子を形成している基板(1)のカドミウ
ムテルル結晶のみを選択的に除去することを特徴とする
半導体装置の製造方法。1. A cadmium tellurium substrate (1) is formed with a well region (5) of mercury-cadmium-tellurium having a P-N junction formed thereon to form a photoelectric conversion element, and then an output portion of the photoelectric conversion element is formed. The input part of the multiplexer formed on the other semiconductor substrate (9) is connected by a metal column (12), and then only the cadmium tellurium crystal of the substrate (1) on which the photoelectric conversion element is formed is selectively removed. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62117780A JPH0828491B2 (en) | 1987-05-13 | 1987-05-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62117780A JPH0828491B2 (en) | 1987-05-13 | 1987-05-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63281460A JPS63281460A (en) | 1988-11-17 |
| JPH0828491B2 true JPH0828491B2 (en) | 1996-03-21 |
Family
ID=14720135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62117780A Expired - Lifetime JPH0828491B2 (en) | 1987-05-13 | 1987-05-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828491B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5385632A (en) | 1993-06-25 | 1995-01-31 | At&T Laboratories | Method for manufacturing integrated semiconductor devices |
| FR2838561B1 (en) * | 2002-04-12 | 2004-09-17 | Commissariat Energie Atomique | PHOTODECTOR MATRIX, PIXEL ISOLATED BY WALLS, HYBRIDED ON A READING CIRCUIT |
-
1987
- 1987-05-13 JP JP62117780A patent/JPH0828491B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63281460A (en) | 1988-11-17 |
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