JPH0828492B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0828492B2 JPH0828492B2 JP62132955A JP13295587A JPH0828492B2 JP H0828492 B2 JPH0828492 B2 JP H0828492B2 JP 62132955 A JP62132955 A JP 62132955A JP 13295587 A JP13295587 A JP 13295587A JP H0828492 B2 JPH0828492 B2 JP H0828492B2
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- semiconductor device
- well region
- cdte
- metal
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Description
【発明の詳細な説明】 〔概要〕 CdTeの基板に所定パターンの水銀・カドミウム・テル
ル(Hg1-XCdXTe)よりなる島状のウェル領域を形成し、
該ウェル領域内にP−N接合を形成してホトダイオード
を形成し、該ホトダイオードとSi基板に形成したマルチ
プレクサの一種である電荷転送素子の入力部とをインジ
ウム金属柱で接続して一体化した半導体装置の製造方法
であって、前記島状のウェル領域間を接続する金属膜を
CdTe基板およびHg1-XCdXTe基板表面に形成した後、金属
柱の間に樹脂を充填し、更に島状のウェル領域を残留さ
せた状態でCdTe基板のみを選択的にエッチング除去して
半導体装置を製造することで、クロストークの発生を無
くし、この半導体装置を77°Kの動作時の低温状態より
室温の間の温度サイクルで動作させた場合に、CdTe基板
とSi基板との熱膨張係数の相違によって前記In金属柱に
塑性変形が生じなく、かつ高密度に集積化された半導体
装置を得るようにする。DETAILED DESCRIPTION OF THE INVENTION [Outline] An island-shaped well region made of a predetermined pattern of mercury, cadmium, and tellurium (Hg 1-X Cd X Te) is formed on a CdTe substrate,
A semiconductor in which a P-N junction is formed in the well region to form a photodiode, and the photodiode and an input portion of a charge transfer device, which is a kind of multiplexer formed on a Si substrate, are connected by an indium metal pillar to be integrated. A method of manufacturing a device, comprising forming a metal film for connecting between the island-shaped well regions.
After forming on the surface of CdTe substrate and Hg 1-X Cd X Te substrate, resin was filled between the metal pillars, and only the CdTe substrate was selectively removed by etching while leaving the island-shaped well region. By manufacturing a semiconductor device, the occurrence of crosstalk is eliminated, and when this semiconductor device is operated at a temperature cycle between room temperature and the low temperature state when operating at 77 ° K, the heat generated between the CdTe substrate and the Si substrate is reduced. A semiconductor device in which plastic deformation does not occur in the In metal column due to the difference in expansion coefficient and which is integrated at high density is obtained.
〔産業上の利用分野〕 本発明は半導体装置の製造方法に係り、特にCdTe基板
にホトダイオードをアレイ状に形成した赤外線検知素子
と該検知素子の検知信号の信号処理回路を設けたSi基板
を金属柱で接続した半導体装置の製造方法に関する。[Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a Si substrate provided with a CdTe substrate on which an infrared detection element having photodiodes formed in an array and a signal processing circuit for a detection signal of the detection element is provided. The present invention relates to a method of manufacturing a semiconductor device connected by a pillar.
水銀・カドミウム・テルルよりなる化合物半導体基板
にホトダイオードをアレイ状に配設した赤外線検知素子
の出力部と、Si基板に設けられ該検知素子で検知された
検知信号を信号処理する電荷転送素子の入力部とをIn金
属柱で接続し、前記赤外線検知素子と電荷転送素子とを
一体化した半導体装置は周知である。An output part of an infrared detection element in which photodiodes are arranged in an array on a compound semiconductor substrate made of mercury, cadmium and tellurium, and an input of a charge transfer element which is provided on a Si substrate and which processes a detection signal detected by the detection element. A semiconductor device in which the infrared detecting element and the charge transfer element are connected to each other by an In metal column is well known.
このような半導体装置に於いてクロストークの発生を
無くし、77°Kの低温の動作時と室温の非動作時の間の
温度サイクルの間に化合物半導体基板とSi基板との熱膨
張係数の相違によって両者の基板を接続しているIn金属
柱に塑性変形を生じない装置が要望されている。In such a semiconductor device, the occurrence of crosstalk is eliminated, and due to the difference in the thermal expansion coefficient between the compound semiconductor substrate and the Si substrate during the temperature cycle between the operation at the low temperature of 77 ° K and the non-operation at the room temperature, both There is a demand for a device that does not cause plastic deformation in the In metal columns connecting the substrates.
従来、このような赤外線検知素子アレイを形成する場
合、第5図に示すようにCdTe基板1に所定パターンのホ
トレジスト膜2を形成し、該ホトレジスト膜2をマスク
としてブロム(Br2)とメチルアルコール(CH3OH)より
なるエッチング液を用いて溝3を形成する。Conventionally, when forming such an infrared detection element array, a photoresist film 2 having a predetermined pattern is formed on a CdTe substrate 1 as shown in FIG. 5, and the photoresist film 2 is used as a mask for bromine (Br 2 ) and methyl alcohol. The groove 3 is formed using an etching solution composed of (CH 3 OH).
次いで第6図に示すように該溝3を含む基板1上に液
相エピタキシャル成長方法等を用いてP型のHg1-XCdXTe
よりなる結晶4を形成する。Then, as shown in FIG. 6, P-type Hg 1-X Cd X Te is formed on the substrate 1 including the groove 3 by a liquid phase epitaxial growth method or the like.
To form a crystal 4.
次いで第7図に示すように該基板表面を研磨し、該基
板1に島状のウェル領域5を形成する。Next, as shown in FIG. 7, the substrate surface is polished to form island-shaped well regions 5 on the substrate 1.
次いで第8図に示すように該基板上に所定パターンの
ホトレジスト膜6を形成し、このホトレジスト膜6をマ
スクとして用いてイオン注入法により該ウェル領域5に
N型の不純物となるボロン(B)原子をイオン注入して
N型層7を形成し、P−N接合を形成してホトダイオー
ド8を形成する。Next, as shown in FIG. 8, a photoresist film 6 having a predetermined pattern is formed on the substrate, and boron (B) which becomes an N-type impurity in the well region 5 is formed in the well region 5 by an ion implantation method using the photoresist film 6 as a mask. Atoms are ion-implanted to form an N-type layer 7, and a P-N junction is formed to form a photodiode 8.
次いで第9図に示すように、前記したホトレジスト膜
6を除去した後、前記したホトダイオード8のN型層7
よりなる出力部とSi基板9に形成された電荷転送装置の
入力ダイオード10の間と、ホトダイオード8が形成され
ているウェル領域5と、電荷転送装置が形成されている
Si基板9に設けられたアース接続用のバスライン11とを
それぞれIn金属柱12,13を用いて接続している。Then, as shown in FIG. 9, after the photoresist film 6 is removed, the N-type layer 7 of the photodiode 8 is removed.
Between the output section and the input diode 10 of the charge transfer device formed on the Si substrate 9, the well region 5 in which the photodiode 8 is formed, and the charge transfer device are formed.
The bus line 11 for earth connection provided on the Si substrate 9 is connected using In metal columns 12 and 13, respectively.
なお、Si基板上の電荷結合素子は図面が複雑となるた
め入力部10とバスライン11のみを示した。The charge-coupled device on the Si substrate has a complicated drawing, so only the input section 10 and the bus line 11 are shown.
然し、このような方法で形成した半導体装置は隣接す
るホトダイオード8の間に入射したホトンは光電変換さ
れてキャリアとなり、そのキャリアは隣接するホトダイ
オードに流れこんで、両方のホトダイオードの各々で検
知される検知信号にクロストークを発生させる問題があ
る。However, in the semiconductor device formed by such a method, the photons incident between the adjacent photodiodes 8 are photoelectrically converted into carriers, and the carriers flow into the adjacent photodiodes, and are detected by both photodiodes. There is a problem of causing crosstalk in the detection signal.
またホトダイオード8よりなる赤外線検知素子を形成
したCdTeの基板の熱膨張率(線膨張係数)は、該装置の
動作温度の77°Kに於いては+0.9×10-6/Kで、電荷転
送装置を形成しているSi基板8は−0.5×10-6/Kで、ま
た非動作時の297°KではCdTe基板の熱膨張率は5.0×10
-6/Kで、Si基板の熱膨張率は2.5×10-6/Kで両方の基板
に於いて熱膨張率がそれぞれ異なる。The thermal expansion coefficient (coefficient of linear expansion) of the CdTe substrate on which the infrared detecting element consisting of the photodiode 8 is formed is + 0.9 × 10 -6 / K at 77 ° K of the operating temperature of the device, The Si substrate 8 forming the transfer device is −0.5 × 10 −6 / K, and the thermal expansion coefficient of the CdTe substrate is 5.0 × 10 5 at 297 ° K when not operating.
At -6 / K, the coefficient of thermal expansion of the Si substrate is 2.5 × 10 -6 / K, and the coefficient of thermal expansion is different for both substrates.
そのため、この半導体装置を動作時の77°Kの低温よ
り室温の297°Kの間の温度サイクルで動作させた時、
両者の基板の熱膨張係数が異なるために、基板間を接続
しているIn金属柱に塑性変形が発生する問題がある。Therefore, when this semiconductor device is operated in a temperature cycle between a low temperature of 77 ° K during operation and 297 ° K at room temperature,
Since the thermal expansion coefficients of the two substrates are different, there is a problem that plastic deformation occurs in the In metal column connecting the substrates.
そのため、このホトダイオード8が形成されているウ
ェル領域5の間をイオンミリング法を用いて溝を形成し
て素子間を分離することで、クロストークの現象の発生
を防止するとともに、この溝を形成することでCdTe基板
自体の容積を減少させて、両者の基板間の熱膨張係数の
差の影響がIn金属柱に及ぼす影響を低減させようとした
が、このような方法でもホトダイオードの出力部と電荷
転送装置の入力部、およびホトダイオードのアース部分
とSi基板に形成されたアース接続との間を接続するため
のInの金属柱が各赤外線検知素子に2本づつ必要とな
り、形成される半導体装置が高密度に形成されない問題
を生じる。Therefore, by forming a groove between the well regions 5 in which the photodiodes 8 are formed by using an ion milling method to separate the elements from each other, the phenomenon of crosstalk is prevented and the groove is formed. By doing so, the volume of the CdTe substrate itself was reduced, and the effect of the difference in thermal expansion coefficient between the two substrates on the In metal column was attempted to be reduced. Each infrared detection element requires two metal pillars of In for connecting between the input part of the charge transfer device and the ground part of the photodiode and the ground connection formed on the Si substrate. Results in the problem that they are not formed in high density.
本発明は上記した問題点を除去し、クロストークが発
生せず、In金属柱で接続される両方の基板の熱膨張率の
差による障害を防いだ半導体装置の製造方法の提供を目
的とする。SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems and to provide a method for manufacturing a semiconductor device in which crosstalk does not occur and an obstacle due to a difference in thermal expansion coefficient between both substrates connected by an In metal pillar is prevented. .
上記目的を達成するための本発明の半導体装置の製造
方法は、カドミウルテルル基板に所定パターンの水銀・
カドミウム・テルル結晶層よりなり、P−N接合を形成
したウェル領域を設け、該ウェル領域間を導電性被膜で
接続した後、該ウェル領域に形成した赤外線検知素子の
出力部と他方の半導体基板に形成したマルチプレクサの
入力部とを金属柱にて接続し、その後、カドミウムテル
ル基板と半導体基板間に樹脂を充填した後、基板1を形
成するカドミウムテルル結晶のみを選択的に除去する。A method for manufacturing a semiconductor device of the present invention to achieve the above object is to provide a predetermined pattern of mercury.
After providing a well region formed of a cadmium tellurium crystal layer and having a P-N junction and connecting the well regions with a conductive film, an output portion of the infrared detection element formed in the well region and the other semiconductor substrate The input part of the multiplexer formed in 1 is connected by a metal column, and then a resin is filled between the cadmium tellurium substrate and the semiconductor substrate, and then only the cadmium tellurium crystal forming the substrate 1 is selectively removed.
ホトダイオードが形成されているウェル領域間を導電
性金属膜で接続した後、In金属柱で両者の基板間を接続
した後、In金属柱の間に樹脂を充填する。更にCdTe結晶
のみ選択的にエッチングし、Hg1-XCdXTe結晶はエッチン
グしないようなエッチング選択比を有するエッチング
液、即ち特願昭57-191058号に於いて本出願人が出願し
たエッチング液にてP−N接合を形成したHg1-XCdXTeの
ウェル領域を有するCdTe基板をエッチングする。すると
CdTe結晶のみが選択的にエッチングされるので、ウェル
領域のみ基板より分離される形となり、クロストークの
発生が無い半導体装置が得られ、更に上記の方法でCdTe
の結晶の容積が少なくなるので、CdTeの基板の熱膨張率
とSi基板の熱膨張率の差によってIn金属柱が塑性変形を
起こす事故がなくなる。After connecting the well regions in which the photodiodes are formed with a conductive metal film, the two substrates are connected with an In metal pillar, and then a resin is filled between the In metal pillars. Further, only the CdTe crystal is selectively etched, the Hg 1-X Cd X Te crystal is not etched etching solution having an etching selection ratio, that is, the etching solution filed by the applicant in Japanese Patent Application No. 57-191058. The CdTe substrate having the well region of Hg 1-X Cd X Te in which the P-N junction is formed is etched at. Then
Since only the CdTe crystal is selectively etched, only the well region is separated from the substrate, and a semiconductor device with no crosstalk can be obtained.
Since the volume of the crystal of is reduced, there is no risk of plastic deformation of the In metal column due to the difference in the coefficient of thermal expansion between the CdTe substrate and the Si substrate.
以下、図面を用いながら本発明の一実施例につき詳細
に説明する。Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
本発明の半導体装置の製造方法の工程は前記した第8
図迄は同様にする。即ち前記した第8図迄の工程を終了
したCdTe基板1にP型のHg1-XCdXTe結晶をウェル領域5
として形成し、これにN型の不純物原子を導入してN型
層7を形成した状態のCdTe基板1を用意する。The process of the method for manufacturing a semiconductor device according to the present invention is the same as the above-mentioned eighth process.
The same is true up to the figure. That is, a P-type Hg 1-X Cd X Te crystal is formed in the well region 5 on the CdTe substrate 1 after the steps up to FIG.
Then, the CdTe substrate 1 in which N-type impurity atoms are introduced thereinto to form the N-type layer 7 is prepared.
次いで第1図に示すように、CdTe基板1上のウェル領
域5間を接続するための金よりなる導電性被膜21を蒸着
法により形成した後、ホトリソグラフィ法を用いて所定
のパターンに形成する。Then, as shown in FIG. 1, a conductive coating film 21 made of gold for connecting between the well regions 5 on the CdTe substrate 1 is formed by a vapor deposition method and then formed into a predetermined pattern by a photolithography method. .
次いで第2図に示すように、該ホトダイオード8の出
力部となるN型層7とSi基板9に形成した入力ダイオー
ド10間をIn金属柱12を用いて接続する。Next, as shown in FIG. 2, the N-type layer 7 serving as the output portion of the photodiode 8 and the input diode 10 formed on the Si substrate 9 are connected using the In metal pillar 12.
更に第3図に示すようにIn金属柱12間にエポキシ樹脂
22を充填する。このようにすることで後の工程がウェル
領域のみ残した状態でCdTe基板のみ選択的にエッチング
した際に、ウェル領域は薄いのでこれを補強する役目を
する。Further, as shown in FIG. 3, epoxy resin is used between the In metal columns 12.
Fill 22. By doing so, when only the CdTe substrate is selectively etched in a state where only the well region remains in the subsequent step, the well region is thin, and therefore, it serves to reinforce this.
次いで第4図に示すように、In金属柱12で接続された
CdTeの基板1を弗化水素酸(HF)と硝酸(HNO3)と酢酸
(CH3COOH)と水(H2O)とが、重量比で(2〜5):
(3〜5):6:6の混合比になるように混合したエッチン
グ液、即ち本出願人が、特願昭57-191058号に於いて出
願したエッチング液に浸漬させてエッチングする。する
とこのエッチング液はウェル領域5を形成するHg1-XCdX
Teの結晶はエッチングしない状態で、CdTe結晶のみを選
択的にエッチングし、Hg1-XCdXTeのウェル領域5が残っ
た状態で、ウェル領域5以外のCdTe基板が選択的にエッ
チングされる。Then, as shown in FIG. 4, it was connected with In metal columns 12.
The substrate 1 of CdTe is hydrofluoric acid (HF), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and water (H 2 O) in a weight ratio (2-5):
(3 to 5): Etching is performed by immersing in an etching solution mixed so as to have a mixing ratio of 6: 6, that is, the etching solution filed by the applicant of the present application in Japanese Patent Application No. 57-191058. Then, this etching solution forms Hg 1-X Cd X which forms the well region 5.
Only the CdTe crystal is selectively etched without etching the Te crystal, and the CdTe substrate other than the well region 5 is selectively etched with the Hg 1-X Cd X Te well region 5 remaining. .
このようにすれば、CdTe基板の部分は無くなるため、
ホトダイオード8を形成したウェル領域5が完全に絶縁
分離されるためクロストークの現象が発生しない。また
この半導体装置を77°Kの動作時と297°Kの非動作時
の温度サイクル内で使用した場合、CdTe基板結晶が除去
されているのでSi基板とCdTe基板の熱膨張率の相違でIn
金属柱が塑性変形を起こす事故がなくなり、高信頼度の
半導体装置が得られる効果がある。By doing this, the part of the CdTe substrate disappears,
Since the well region 5 in which the photodiode 8 is formed is completely insulated and separated, the phenomenon of crosstalk does not occur. When this semiconductor device was used in the temperature cycle of 77 ° K operation and 297 ° K non-operation, the CdTe substrate crystal was removed, and the difference in the coefficient of thermal expansion between the Si substrate and the CdTe substrate caused In.
There is an effect that an accident that causes plastic deformation of the metal column is eliminated and a highly reliable semiconductor device can be obtained.
また赤外線検知素子1個当たりに1個の出力用In金属
柱12のみを形成すれば良いので形成される半導体層の高
密度化が図れる。Further, since it is sufficient to form only one output In metal column 12 for each infrared detection element, the density of the semiconductor layer formed can be increased.
以上述べたように本発明の半導体装置の製造方法によ
れば、金属バンプの塑性変形が生じなく、クロストーク
の発生しない高密度に集積化された半導体装置が得られ
る効果がある。As described above, according to the method for manufacturing a semiconductor device of the present invention, there is an effect that a semiconductor device integrated with high density in which plastic deformation of metal bumps does not occur and crosstalk does not occur can be obtained.
第1図より第4図迄は本発明の半導体装置の製造方法の
工程を示す断面図、 第5図より第9図迄は従来の半導体装置の製造方法の工
程を示す断面図である。 図に於いて、 1はCdTe基板、5はウェル領域、7はN型層、8はホト
ダイオード、9はSi基板、10は入力ダイオード、12はIn
金属柱、21は導電性被膜、22は樹脂を示す。1 to 4 are sectional views showing the steps of the method for manufacturing a semiconductor device of the present invention, and FIGS. 5 to 9 are sectional views showing the steps of the conventional method for manufacturing a semiconductor device. In the figure, 1 is a CdTe substrate, 5 is a well region, 7 is an N-type layer, 8 is a photodiode, 9 is a Si substrate, 10 is an input diode, and 12 is In.
A metal column, 21 is a conductive coating, and 22 is a resin.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−42175(JP,A) 特開 昭61−214462(JP,A) 特開 昭62−232958(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-57-42175 (JP, A) JP-A-61-214462 (JP, A) JP-A-62-232958 (JP, A)
Claims (1)
ンの水銀・カドミウム・テルル結晶層よりなり、P−N
接合を形成したウェル領域(5)を形成し、該ウェル領
域(5)に形成した赤外線検知素子の出力部と他方の半
導体基板(9)に形成したマルチプレクサの入力部とを
金属柱(12)にて接続し、その後カドミウムテルル基板
(1)と半導体基板(9)間に、樹脂(22)を充填した
後、基板(1)を形成するカドミウムテルル結晶のみを
選択的に除去することを特徴とする半導体装置の製造方
法。1. A cadmium tellurium substrate (1) comprising a mercury-cadmium-tellurium crystal layer of a predetermined pattern, comprising a P-N
A well region (5) having a junction is formed, and an output portion of the infrared detecting element formed in the well region (5) and an input portion of the multiplexer formed on the other semiconductor substrate (9) are connected to a metal column (12). And then the resin (22) is filled between the cadmium tellurium substrate (1) and the semiconductor substrate (9), and then only the cadmium tellurium crystal forming the substrate (1) is selectively removed. And a method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62132955A JPH0828492B2 (en) | 1987-05-27 | 1987-05-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62132955A JPH0828492B2 (en) | 1987-05-27 | 1987-05-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63296272A JPS63296272A (en) | 1988-12-02 |
| JPH0828492B2 true JPH0828492B2 (en) | 1996-03-21 |
Family
ID=15093404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62132955A Expired - Lifetime JPH0828492B2 (en) | 1987-05-27 | 1987-05-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828492B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5385632A (en) | 1993-06-25 | 1995-01-31 | At&T Laboratories | Method for manufacturing integrated semiconductor devices |
-
1987
- 1987-05-27 JP JP62132955A patent/JPH0828492B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63296272A (en) | 1988-12-02 |
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