JPH0830824B2 - Method of manufacturing thin film transistor array - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array that constitutes an image display device by combining with a liquid crystal or the like.

2. Description of the Related Art In recent years, expectations for planarization of image display devices have increased, and research and development in this field have been very actively conducted.
Among them, flat displays using liquid crystals have been promising because they are being commercialized.

One of the flat displays using liquid crystal is a method of arranging unit pixels composed of semiconductor switching elements and liquid crystal optical elements in a two-dimensional matrix. Figure 5 shows the equivalent circuit, 17 is MIS (Metal-Insulator-Semicon).
ductor transistor, 18 is a liquid crystal cell, 2 is a scanning signal line, and 5 is a video signal line. A gate signal is sequentially applied to the scanning signal line 2 so that the MIS transistor is turned on, and a video signal corresponding to the gate 1 line is written from the video signal line 5 to the liquid crystal cell 18 by line sequential scanning, thereby providing a function equivalent to that of a CRT. To be done.

The MIS transistor 17 is manufactured by using single crystal silicon, polycrystalline silicon, amorphous silicon, a compound semiconductor, or the like as a semiconductor layer. Here, a method of manufacturing a liquid crystal display when amorphous silicon, which is said to be relatively easy to reduce in cost and increase in area, is used as a semiconductor layer is disclosed in JP-A-59-9962. Will be described as an example. FIG. 3 shows a plan view of this conventional example, and FIG.
The drawing shows a cross-sectional view taken along the line AA 'of the plan view shown in FIG.

First, the first transparent conductive layer 1 is selectively deposited on the glass plate 7, and then, for example, a silicon oxide layer is deposited as the first transparent insulating layer 8 on the entire surface. Next, the first metal layer 2 which also serves as the gate electrode and the scanning signal line is selectively deposited by using, for example, Mo. After that, for example, a silicon nitride layer as the second transparent insulating layer 9, an island-shaped amorphous silicon semiconductor layer 3B containing almost no impurities serving as donors or acceptors, and a semiconductor protective layer 10 made of, for example, a silicon nitride layer are formed by plasma CVD. By the method, it is selectively deposited. afterwards,
A resist pattern for the opening 4 is formed by a normal photolithography method, and the opening 4 is formed by selectively removing the silicon nitride layer 9 and the silicon oxide layer 8 using, for example, a hydrofluoric acid-based etching solution. A part of one transparent conductive layer 1 is exposed. At this time, although not shown, an opening is also formed in the silicon nitride layer 9 on the scanning signal line 2 at the end of this thin film transistor array. Then, the transparent conductive layer 1 is formed through the second metal layer 5 that also serves as the video signal line and the source of the MIS transistor and the drain of the MIS transistor and the opening 4.
A thin film transistor array is obtained by selectively depositing and forming a second metal layer 6 connecting with and with Al, for example.

After the polyimide resin is applied and cured on both the above-mentioned thin film transistor array and the glass substrate 13 on which the second transparent conductive layer 14 is deposited on one main surface, alignment treatment is performed, and the liquid crystal 15 is, for example, a twisted nematic liquid crystal. It is only necessary to seal between the two substrates, and further to arrange the polarizing plates 16 above and below.

Problems to be Solved by the Invention However, in the above-described structure, first, in order to form an island-shaped amorphous silicon semiconductor layer, the amorphous silicon semiconductor layer is usually deposited on the entire surface and then the island-shaped amorphous silicon semiconductor layer is formed by photolithography. Since the resist pattern is formed and the semiconductor layer is selectively removed by etching using the resist pattern as a mask, the number of masks is increased by one. Therefore, there are problems that the manufacturing process becomes complicated, defects increase, and the manufacturing cost increases.

Further, in order to form the opening 4, the silicon nitride layer as the second transparent insulating layer 9 and the silicon oxide layer as the first transparent insulating layer 8 are treated with a hydrofluoric acid-based etching solution such as NH ₄ F: HF.
When wet etching is performed at = 6: 1, the etching rate of silicon oxide is 4 to 5 times faster than that of silicon nitride, depending on the deposition conditions, but the lower silicon oxide layer is overhanged. Due to this overhang, the step coverage of the second metal layers 5 and 6 is deteriorated, and the chemical solution remains in the overhang portion to cause corrosion, which is transparent to the second metal layer 6 also serving as the drain of the MIS transistor. The electrical connection with the conductive layer 1 and the electrical connection between the scanning signal line 2 and the second metal layer (not shown) that also serves as the extraction electrode of the scanning signal line 2 are defective, resulting in pixel defects (point defects). ) And a pixel defect (line defect) over the entire line of one scanning signal line occurs. These defects are fatal for an image display device.

In view of such a point, the present invention provides a method for manufacturing a thin film transistor array which has a simple manufacturing process by reducing the number of masks by one, obtains a good opening, has few electrical connection defects, and has a high yield. The purpose is to do.

Means for Solving the Problems In order to solve the above problems, the present invention comprises a step of selectively forming a transparent conductive layer on an insulating substrate, a first transparent insulating layer on the entire surface of the transparent conductive layer side. A step of forming a first metal layer is selectively formed on the first transparent insulating layer either at a position separated from the transparent conductive layer or at a position covering a part of the transparent conductive layer. Step, depositing a semiconductor layer on the entire surface of the first metal layer and the first transparent insulating layer via a second transparent insulating layer, via the second transparent insulating layer and the semiconductor layer Selectively forming a third insulating layer on a portion of the first metal layer, the first and second transparent insulating layer and the semiconductor layer formed on the transparent conductive layer A first resist pattern for selectively forming openings is formed on the transparent conductive layer, At least a portion of the transparent conductive layer is exposed by reactive ion etching using a reactive gas containing at least carbon fluoride or a gas having a structure in which a part of fluorine of carbon fluoride is replaced by hydrogen. First, a step of forming an opening in the second transparent insulating layer and the semiconductor layer, partially overlapping the first metal layer on the semiconductor layer, electrically through the opening and the transparent conductive layer A step of selectively forming a second metal layer so as to make contact, a second resist pattern is formed on a part of the third insulating layer, the opening and a part of the transparent conductive layer. Selectively removing the second metal layer by etching using the second resist pattern as a mask, and the semiconductor layer on the transparent conductive layer using the second metal layer and the third insulating layer as a mask. Remove.

When the present invention is manufactured with the above-described structure, the number of masks can be reduced by one, and since the etching rate of silicon oxide is smaller than that of silicon nitride, overhang does not occur in the opening and good contact can be obtained. And the second metal layer 6 also serving as the drain of the MIS transistor is electrically connected to the first transparent conductive layer 1 and the second metal layer not shown is also used as the extraction electrode of the scanning signal line 2. Since the defective electrical connection between the scanning signal line 2 and the scanning signal line 2 is reduced, a thin film transistor array having a simple manufacturing process, low cost, and high yield can be manufactured.

Embodiment FIG. 1 is a sectional view of a thin film transistor array according to an embodiment of the present invention, and FIG. 2 is a sectional view of each process of a process after formation of an opening. These two drawings are used. Explain.

First, a transparent conductive layer 1 such as ITO is formed on the glass plate 7.
(Indium-Tin-Oxide) is selectively deposited, and then, for example, silicon oxide is deposited as the first transparent insulating layer 8 on the entire surface. Next, the first metal layer 2 which also serves as the gate electrode and the scanning signal line is selectively formed by depositing, for example, Cr. After that, for example, a silicon nitride layer as a second transparent insulating layer 9 and an amorphous silicon semiconductor layer 3A containing almost no impurities serving as donors or acceptors are deposited on the entire surface by, for example, plasma CVD method, and then the semiconductor is continuously formed. As the protective layer 10, for example, a silicon nitride layer is selectively deposited.
Then, the amorphous silicon semiconductor layer 3A and the silicon nitride layer 9
And the resist pattern 12A of the opening 4 is formed on the silicon oxide layer 8 by a normal photolithography method, and, for example, by a parallel plate type reactive ion etching apparatus,
For example, CF ₄ is maintained at a flow rate of 27 SCCM and O 2 is maintained at 400 mTorr at a flow rate of ₃ SCCM, and etching is performed at a power of 350 W to partially expose the first transparent conductive layer 1. Under this etching condition, since the etching rate of amorphous silicon is 4 to 5 times slower than that of silicon nitride, the lower silicon nitride layer is overhanged as shown in FIG. 2B. When immersed in acid: nitric acid = 1: 100 for about 30 seconds, a part of the overhanging amorphous silicon 3A is etched by hydrofluoric nitric acid, so no overhang occurs and the result becomes as shown in FIG. 2C. . And resist pattern
If 12A is removed, a good opening 4 without overhang is formed as shown in FIG. 2D. At this time, although not shown, an opening is also formed in the silicon nitride layer 9 on the scanning signal line 2 at the end of this thin film transistor array. Then, as a material of the second metal layer 5 that also serves as the video signal line and the source of the MIS transistor, and the second metal layer 6 that connects the drain of the MIS transistor and the first transparent conductive layer 1 through the opening 4. For example, after depositing Al on the entire surface,
A drain resist pattern 12B is formed to obtain FIG. 2E. Then, after selectively removing Al by etching using the source / drain resist pattern as a mask,
If the amorphous silicon layer 3A is selectively removed using, for example, a fluorinated nitric acid-based etching solution by using the resist pattern 12B (that is, the second metal layers 5 and 6) and the semiconductor protective layer 10 as a mask, FIG. Is obtained. Finally, by removing the resist, a thin film transistor array as shown in FIG. 2G is completed. At this time, at the same time, an extraction electrode for the scanning signal line 2 is also formed through the opening at the end of the thin film transistor array described above.

After this, a liquid crystal display is constructed using the thin film transistor array according to the present invention.

As described above, when forming the opening 4, for example, by using a parallel plate type reactive ion etching apparatus, for example, CF4 is kept at 27 SCCM, O2 is kept at 400 mTorr at a flow rate of 3 SCCM, and reactive ions are generated at a power of 350 W. The first transparent conductive layer 1 is partially exposed by etching. Then, after immersing in an etching solution of amorphous silicon, for example, hydrofluoric acid: nitric acid = 1: 100 for about 30 seconds and removing the resist, no overhang occurs and a good contact is formed. After the second metal layers 5 and 6 are formed, the amorphous silicon layer 3A is selected by, for example, a fluorinated nitric acid-based etching solution using the resist pattern 12B (that is, the second metal layers 5 and 6) and the semiconductor protective layer 10 as a mask. If it is removed selectively, the number of masks can be reduced by one, a simple manufacturing process can be achieved, and a thin film transistor array having a high yield and a low manufacturing cost can be manufactured.

Although the source / drain resist pattern 12B is finally removed in the above-described embodiment, the source / drain resist pattern 12B is removed immediately after etching Al, and the second metal layers 5 and 6 and the semiconductor are directly removed. Protective layer 10
Using the as a mask, the amorphous silicon layer 3A may be selectively removed with, for example, a hydrofluoric nitric acid-based etching solution. Further, although the auxiliary capacitance is not provided in the above-mentioned embodiment, one of the electrodes to be the auxiliary capacitance is provided, for example, at the same level as the first metal layer in order to improve the image quality, and the first transparent insulating layer is used to interpose the first transparent insulating layer. An auxiliary capacitance can be added by using one transparent conductive layer as the other auxiliary capacitance electrode. Further, in order to improve the ohmic property of the electrical connection between the semiconductor layer and the second metal layer, an impurity such as P or As is added between the amorphous silicon semiconductor layer 3 and the second metal layers 5 and 6. An amorphous silicon semiconductor layer containing a high concentration may be interposed.

Effects of the Invention As described above, according to the present invention, the number of masks can be reduced by one, and since a good opening is obtained and there are few electrical connection defects, the manufacturing process is simple and the cost is low. A thin film transistor array with high yield can be manufactured, and its practical effect is great.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an embodiment of a thin film transistor array according to the present invention, FIG. 2 is a cross-sectional view of each process after forming an opening, and FIG. 3 is a conventional thin film transistor array. FIG. 4 is a schematic plan view of the liquid crystal display constructed in FIG. 4, FIG. 4 is a schematic sectional view of the device, and FIG. 5 is an equivalent circuit diagram of the device. 1 ... First transparent conductive layer, 2 ... First metal layer (scanning signal line), 3A ... Semiconductor layer containing amorphous silicon as a main component, 3B ... Amorphous silicon as main component Island-shaped semiconductor layer, 4 ... opening, 5 ... second metal layer (video signal line), 6 ... second metal layer (drain electrode), 7 ... glass substrate, 8 ... One transparent insulating layer, 9 ... second transparent insulating layer, 10 ... semiconductor protective layer, 11 ... second metal layer, 12
A: Opening resist pattern, 12B: Source / drain resist pattern, 13 ... Glass substrate, 14 ... Second transparent conductive layer, 15 ... Liquid crystal layer, 16 ... Polarizing plate, 17 ...
MIS transistor, 18 ... Liquid crystal cell.

Claims (4)

[Claims] 1. A step of selectively forming a transparent conductive layer on an insulating substrate, a step of forming a first transparent insulating layer on the entire surface of the transparent conductive layer, and a step of forming a first transparent insulating layer on the first transparent insulating layer. A step of selectively forming one metal layer at a position separated from the transparent conductive layer or at a position covering a part of the transparent conductive layer, on the first metal layer and the first transparent insulation A step of depositing a semiconductor layer on the entire surface of the layer via a second transparent insulating layer, a third insulating layer on a part of the first metal layer via the second transparent insulating layer and the semiconductor layer. A step of selectively forming a layer, for selectively forming an opening on the transparent conductive layer through the first and second transparent insulating layers and a semiconductor layer formed on the transparent conductive layer A first resist pattern is formed, and at least carbon fluoride or a part of fluorine of carbon fluoride is placed in hydrogen. A part of the transparent conductive layer is exposed by reactive ion etching using a reactive gas containing any of the gases of the above structure to form an opening in the first and second transparent insulating layers and the semiconductor layer. A step of partially overlapping the first metal layer on the semiconductor layer, and selectively forming a second metal layer so as to make electrical contact with the transparent conductive layer through the opening, A second resist pattern is formed on a portion of the third insulating layer, the opening and a portion of the transparent conductive layer, and the second metal layer is etched using the second resist pattern as a mask. And a step of removing the semiconductor layer on the transparent conductive layer using the second metal layer and the third insulating layer as a mask. 2. The method of manufacturing a thin film transistor array according to claim 1, further comprising a step of immersing the semiconductor layer in an etching solution after forming the opening and before removing the first resist. . 3. The first transparent insulating layer is silicon oxide, the second transparent insulating layer is silicon nitride, and the semiconductor layer is an amorphous semiconductor containing silicon as a main component. Item 1. A method of manufacturing a thin film transistor array according to item 1. 4. The method of manufacturing a thin film transistor array according to claim 1, wherein the reactive gas contains at least CF ₄ and O ₂ .