JPH0833551B2 - Method of manufacturing thin film transistor array - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array that constitutes an image display device by combining with a liquid crystal or the like.

2. Description of the Related Art In recent years, expectations for planarization of image display devices have increased, and research and development in this field have been very actively conducted.
Among them, flat displays using liquid crystals have been promising because they are being commercialized.

One of the flat displays using liquid crystal is a method of arranging unit pixels composed of semiconductor switching elements and liquid crystal optical elements in a two-dimensional matrix. Fig. 5 shows the equivalent circuit, 16 is MIS (Metal-Insulator- Semico).
n transistor, 17 is a liquid crystal cell, 2 is a scanning signal line, and 5 is a video signal line. A gate signal is sequentially applied to the scanning signal line 2 so that the MIS transistor is turned on, and a video signal corresponding to the gate 1 line is written from the video signal line 5 to the liquid crystal cell 17 by line-sequential scanning to provide a function equivalent to that of a CRT. To be done.

The MIS transistor 16 is manufactured using single crystal silicon, polycrystalline silicon, amorphous silicon, a compound semiconductor, or the like as a semiconductor layer. Here, a method of manufacturing a liquid crystal display when amorphous silicon, which is said to be relatively easy to reduce in cost and increase in area, is used as a semiconductor layer is disclosed in JP-A-59-9962. Will be described as an example. FIG. 3 shows a plan view of a thin film transistor array substrate in this conventional display, FIG. 4 (a) shows a cross section of a liquid crystal display using the array substrate of FIG. 3, and the plan view shown in FIG. The figure in the cross-sectional part on the AA 'line of FIG.

First, the first transparent conductive layer 1 is selectively deposited on the glass plate 7, and then, for example, a silicon oxide layer is deposited as the first transparent insulating layer 8 on the entire surface. Next, the first metal layer 2 which also serves as the gate electrode and the scanning signal line is selectively deposited by using, for example, Mo. After that, for example, a silicon nitride layer as the second transparent insulating layer 9, an island-shaped amorphous silicon semiconductor layer 3B containing almost no impurities serving as donors or acceptors, and a silicon nitride layer as the semiconductor protective layer 10 are formed by the plasma CVD method. To selectively deposit and form. After that, a resist pattern for the opening 4 is formed by a normal photolithography method, and the opening 4 is formed by selectively removing the silicon nitride layer 9 and the silicon oxide layer 8 using, for example, a hydrofluoric acid-based etching solution. , A part of the first transparent conductive layer 1 is exposed. At this time, although not shown, the silicon nitride layer 9 on the scanning signal line 2 is formed at the end of the thin film transistor array.
An opening is also formed in this area. Then, the second metal layer 5 which also serves as the video signal line and the source of the MIS transistor and the second metal layer 6 which connects the drain of the MIS transistor and the transparent conductive layer 1 through the opening 4 are selectively formed by, for example, A1. Deposition is performed to obtain a thin film transistor array.

After the polyimide resin is applied and cured on both the thin film transistor array and the glass plate 12 on which the second transparent conductive layer 13 is deposited on one main surface, alignment treatment is performed, and the liquid crystal 14 is, for example, a twist nematic liquid crystal. It is only necessary to enclose between the two substrates and to dispose the polarizing plates 15 above and below.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the method as described above, first, in order to form the island-shaped amorphous silicon semiconductor layer 3B, the amorphous silicon semiconductor layer is usually deposited on the entire surface and then the island is formed by photolithography. The number of masks is increased by one because the resist pattern is formed in a uniform shape and the amorphous silicon is selectively removed by etching using the resist pattern as a mask. Therefore, the manufacturing process is complicated, defects are increased, and the manufacturing cost is increased.

In addition, the second transparent insulating layer 9 for forming the opening 4 is formed.
Of the silicon nitride layer as the first transparent insulating layer 8 and a silicon oxide layer as the first transparent insulating layer 8 with a hydrofluoric acid-based etching solution such as NH ₄ F: H
When wet etching is performed at F = 6: 1, the etching rate of silicon oxide is 4 to 5 times faster than that of silicon nitride, depending on the deposition conditions, but the lower silicon oxide layer is over-etched, resulting in As shown in (b), the opening 4 having an overhang is formed. Due to this overhang, the step coverage of the second metal layer 6 formed in the opening 4 is deteriorated, and the chemical solution remains in the overhang portion to cause corrosion, which causes the second metal layer to also serve as the drain of the MIS transistor. The electrical connection between the metal layer 6 and the transparent conductive layer and the second metal layer (not shown) also serving as the extraction electrode of the scanning signal line 2 and the scanning signal line 2
There is a problem in that a defective electrical connection to the pixel occurs and a pixel defect (point defect) or a pixel defect (line defect) across all lines of one scanning signal line occurs. These defects are fatal for an image display device.

In view of such a point, the present invention provides a method for manufacturing a thin film transistor array which has a simple manufacturing process by reducing the number of masks by one, obtains a good opening, has few electrical connection defects, and has a high yield. The purpose is to do.

Means for Solving the Problems In order to solve the above problems, the present invention selectively covers a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer on an insulating substrate. In the production of a thin film transistor array formed by deposition, at least the semiconductor layer is selectively removed by wet etching using a resist pattern having an opening on the insulating layer and the semiconductor layer as a mask, and then by reactive ion etching. A method of removing the resist pattern after selectively removing the semiconductor layer and the insulating layer in the opening portion by etching for selectively removing the insulating layer is used.

When the present invention is manufactured with the above-described structure, the number of masks can be reduced by one, and since the etching rate of silicon oxide is smaller than that of silicon nitride, overhang does not occur in the opening and good contact can be obtained. Is formed, the electrical connection between the second metal layer also serving as the drain of the MIS transistor and the first transparent conductive layer, and the electrical connection between the second metal layer also serving as the extraction electrode of the scanning signal line and the scanning signal line. Since the number of defects is reduced, the manufacturing process is simple, the cost is low, and the thin film transistor array with high yield can be manufactured.

Embodiment FIG. 1 is a sectional view of a thin film transistor array in an embodiment of the present invention, and FIG. 2 is a sectional view of an opening forming portion for each process of forming an opening. Will be explained.

First, a transparent conductive layer 1 such as ITO is formed on the glass plate 7.
(Indium-Tin-Oxide) is selectively deposited, and then, for example, silicon oxide is deposited as the first transparent insulating layer 8 on the entire surface. Next, the first metal layer 2 which also serves as the gate electrode and the scanning signal line is selectively formed by depositing, for example, Cr. After that, for example, a silicon nitride layer as a second transparent insulating layer 9 and an amorphous silicon semiconductor layer 3A containing almost no impurities serving as donors or acceptors are formed on the entire surface by plasma CVD, for example, and 1000A is deposited on the entire surface. As the semiconductor protective layer 10, for example, a silicon nitride layer is selectively deposited. This protective layer 10 is shown in FIG.
Indicates the contact portion and layer 10 is not shown.
Then, the amorphous silicon semiconductor layer 3A and the silicon nitride layer 9
And a resist pattern for forming an opening on the silicon oxide layer 8 by an ordinary photolithography method as shown in FIG. 2A.
11 is formed, and the amorphous silicon semiconductor layer 3A is selectively removed by immersing in an etching solution of hydrofluoric acid: nitric acid = 1: 30 for about 60 seconds. The etching rate at this time depends on the method of depositing the amorphous silicon, but since it is about 10,000 A / min, the amorphous silicon 3A is side-etched by about 1 μm with respect to the resist 11. Therefore, as shown in FIG. Like This side etch prevents the overhang from occurring during the subsequent reactive ion etching of the silicon nitride layer and the silicon oxide layer. Then, after washing with water and drying, it is baked at about 160 ° C. for about 20 minutes to improve the adhesion between the resist and the substrate, particularly the adhesion at the side-etched portion, as shown in FIG. 2C. Then, for example, in a parallel plate type reactive ion etching device, for example, CF ₄ is kept at 27 SCCM and O ₂ is kept at 400 mTorr at a flow rate of 3 SCCM, and etching is performed at a power of 350 W to etch silicon nitride 9 and silicon oxide 8. . In this way, the first transparent conductive layer 1 is partially exposed. Under these etching conditions, the etching rate of silicon nitride is several times higher than that of silicon oxide, so overhang does not occur even though it is a two-layer etching. Also, since amorphous silicon penetrates about 1 μm from the resist edge, this also exceeds. Since no hang is generated, the result is as shown in FIG. 2D. Then, if the resist pattern 11 is removed, the second
A good opening 4 having no overhang as shown in FIG. E can be obtained. At this time, although not shown, the silicon nitride layer 9 on the scanning signal line 2 is formed at the end portion of the thin film transistor array.
An opening is also formed in this area. The second metal layer 5 serving also as the video signal line and the source of the MIS transistor and the MIS
A second metal layer 6 for connecting the drain of the transistor and the first transparent conductive layer 1 through the opening 4 is selectively deposited, for example, at A1, and at the same time, the opening at the end of the thin film transistor array described above is formed. The extraction electrode of the scanning signal line 2 is also formed via the. Finally, by using the second metal layers 5 and 6 and the semiconductor protective layer 10 as a mask, the unnecessary amorphous silicon layer other than the transistor portion is selectively removed by, for example, a fluorinated nitric acid-based etching solution to form a thin film transistor array. Will be completed.

After this, a liquid crystal display is constructed using the thin film transistor array according to the present invention.

As described above, when the opening 4 is formed, the resist pattern 11 of the opening 4 is formed by a normal photolithography method, and, for example, an etching solution of hydrofluoric acid: nitric acid = 1: 30 is used for about 60 seconds. The amorphous silicon semiconductor layer is selectively removed by immersion, washed with water and dried, and then baked at about 160 ° C. for about 20 minutes to improve the adhesion between the resist and the substrate. After that, for example, in a parallel plate type reactive ion etching apparatus, for example, CF ₄ is kept at 27 SCCM, O ₂ is kept at 400 mTorr at a flow rate of 3 SCCM, silicon nitride and silicon oxide are etched at a power of 350 W, and the first When the opening 4 is formed by partially exposing the transparent conductive layer 1 and the resist is removed, an overhang does not occur at all, a good contact is formed, and the second metal layers 5 and 6 and the semiconductor protective layer 10 are formed. If the amorphous silicon layer is selectively removed by using, for example, a fluorinated nitric acid-based etching solution as a mask, the number of masks is reduced by one, and a simple manufacturing process is provided, and the yield is high and the manufacturing cost is low. A thin film transistor array can be manufactured.

Although the auxiliary capacitance is not provided in the above-described embodiment, one of the electrodes serving as the auxiliary capacitance is provided at the same level as, for example, the first metal layer in order to improve the image quality, and the first transparent insulating layer is interposed therebetween. A storage capacitor can be added by using the first transparent conductive layer as the other storage capacitor electrode. Also,
Impurities such as P or As are highly concentrated between the amorphous silicon semiconductor layer 3 and the second metal layers 5 and 6 in order to improve the ohmic property of electrical connection between the semiconductor layer and the second metal layer. An amorphous silicon semiconductor layer containing it may be interposed.

EFFECTS OF THE INVENTION As described above, according to the present invention, since a good opening is obtained and there are few electrical connection defects, it is possible to reduce the number of masks by one, the manufacturing process is simple and the cost is low. A thin film transistor array with high yield can be manufactured, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a thin film transistor array formed by the method of the present invention, FIGS. 2A to 2E are cross-sectional views of each process for forming an opening, and FIG. 3 is a schematic view of a conventional thin film transistor array. 4A is a schematic sectional view of a conventional liquid crystal display, FIG. 4B is a partial sectional view of FIG. 4A, and FIG. 5 is an equivalent circuit diagram of the liquid crystal display device. 1 ... First transparent conductive layer, 2 ... First metal layer (scanning signal line), 3A ... Semiconductor layer containing amorphous silicon as a main component, 3B ... Amorphous silicon as main component Island-shaped semiconductor layer, 4 ... opening, 5 ... second metal layer (video signal line), 6 ... second metal layer (drain electrode), 7 ... glass substrate, 8 ... One transparent insulating layer, 9 ...... second transparent insulating layer, 10 ... semiconductor protective layer, 11 ... resist, 12 ...
Glass substrate, 13 ... second transparent conductive layer, 14 ... liquid crystal layer,
15 …… deflector, 16 …… MIS transistor, 17 …… liquid crystal cell.

Claims (5)

[Claims] 1. A first metal layer, an insulating layer, and
In manufacturing a thin film transistor array formed by selectively depositing a semiconductor layer and a second metal layer, at least the semiconductor layer is wet-etched using a resist pattern having an opening on the insulating layer and the semiconductor layer as a mask. Selectively removing the insulating layer by reactive ion etching, and then selectively removing the semiconductor layer and the insulating layer in the opening by etching, and then removing the resist pattern. A method of manufacturing a thin film transistor array, comprising: 2. A step of selectively forming a transparent conductive layer on an insulating substrate, a step of forming a first transparent insulating layer on the entire surface of the transparent conductive layer, and a transistor on the first transparent insulating layer. Selectively forming the first metal layer to be the gate of the transparent conductive layer at a position spaced apart from the transparent conductive layer or a position covering a part of the transparent conductive layer, on the first metal layer Forming a semiconductor layer on the entire surface via a second transparent insulating layer, selecting a third insulating layer as a part on the first metal layer via the second transparent insulating layer and the semiconductor layer Forming step, the step of forming an opening in the first and second transparent insulating layers and the semiconductor layer formed on the transparent conductive layer to expose a part or all of the transparent conductive layer, the semiconductor layer The first metal layer and the first metal layer, which partially overlap each other, and one of which is in front of the opening. A step of selectively forming a pair of second metal layers so as to make electrical contact with the transparent conductive layer, and selectively etching the semiconductor layer by etching using the third insulating layer and the second metal layer as a mask In the method of manufacturing a thin film transistor array including a step of removing the opening, the opening is wet with the resist pattern of the opening formed on the first and second transparent insulating layers and the semiconductor layer as a mask. After selective removal by etching, reactive ion etching using a reactive gas containing at least carbon fluoride or a gas in which at least a part of fluorine of carbon fluoride is replaced with hydrogen, and then the resist A method for manufacturing a thin film transistor array, which is obtained by removing a pattern. 3. The first transparent insulating layer is silicon oxide, the second transparent insulating layer is silicon nitride, and the semiconductor layer is an amorphous semiconductor containing silicon as a main component. Item 3. A method of manufacturing a thin film transistor array according to item 2. 4. The method of manufacturing a thin film transistor array according to claim ₂ , wherein the reactive gas contains at least CF ₄ and O ₂ . 5. The method of manufacturing a thin film transistor array according to claim 2, wherein the semiconductor layer is etched with an etching solution containing hydrofluoric acid and nitric acid.