JPH0830949B2 - Video signal memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal memory device, and is particularly suitable for use in a high-definition video system and used in a special effect device for such a video system. A preferred video signal memory device.

[Outline of Invention]

The present invention relates to a video signal memory device for storing a video data word corresponding to a sample value of the video signal at each sample position on a horizontal scanning line of the video signal forming a raster display screen image. Each of n × n video data words continuous in the horizontal scanning direction and n continuous in the vertical scanning direction included in each square of m squares obtained by dividing in the scanning direction and the vertical scanning direction. Memory means having n × n memory modules provided corresponding to the video data words, each memory module of the n × n memory modules having memory capacity for storing m video data words; When storing the video data word in the memory means, the video data word is stored in a memory module. Is a rectangle indicating a maximum of n memory modules among the n × n memory modules and including the stored video data word as an address in the memory module storing the video data word. The address corresponding to the position on the screen screen of the memory means, and the video data word is stored in the specified address of the maximum n memory modules specified during one write cycle of the memory means. In order to provide a video signal memory device having a control means for controlling
The data can be written at high speed in one or more areas at the same time.

[Conventional technology and its problems]

Standard television signals transmitted in the UK are PAL signals with 625 lines per frame and 50 fields per second.
PAL, NTSC and SECAM signals transmitted in other countries use similar or slightly lower line frequencies (eg 525 lines per frame) and also or slightly higher field frequencies (eg 60 fields per second). . However, there is no immediate prospect that these transmission signals will be changed significantly, and thus there is an increasing demand for high-definition video systems. Such a system can be used, for example, in movie production, closed circuit television systems, satellite communication systems and general studios. One high-definition video system thus proposed uses 1125 lines per frame and 60 fields per second. Also, this proposed system is used in regular television receivers 4:
Use 5: 3 aspect ratio instead of 3 aspect ratio.

Special effects that are applicable to video signals are well known. Thus, for example, the image of the cathode ray tube can be offset (moved in any direction), scaled (stretched or compressed in size), rolled (rotating in two or three dimensions), etc.

One way to achieve such special effects, which will be described in more detail below, is to convert the input analog video signal into a digital signal and modify the individual input digital signals to obtain the desired special effect, resulting in a modified digital signal. Is stored in a field memory and is read out from the field memory to obtain a desired output digital signal.

In the above proposed high definition video system, the input analog video signal is sampled 2048 times per horizontal scanning line, the sampling frequency is 69.12 MHz, and the sampling interval is about 14.7 nanoseconds. Therefore, the time available to write each digital signal to the field memory is a little less than 14.7 nanoseconds due to the special effect correction step, and there is a memory cooperating means to write the data into the memory very fast. The problem that must be raised arises.

It is an object of the present invention to provide a video signal memory device in which data can be written at high speed.

Another object of the present invention is to provide a video signal memory device capable of simultaneously writing data in one or more areas.

[Means for solving problems]

In order to solve the above-mentioned problems, according to the present invention, a video data word corresponding to the sample value of the video signal at each sample position on the horizontal scan line of the video signal forming the screen image of the raster display is stored. In a video signal memory device, n pieces in the horizontal scanning direction and n pieces in the vertical scanning direction are included in each of the squares of m pieces obtained by dividing the screen screen in the horizontal scanning direction and the vertical scanning direction. The memory module comprises n × n memory modules provided corresponding to each video data word of continuous n × n video data words, wherein n
Each memory module of the × n memory modules is a memory module having a capacity for storing m video data words, and a memory module for storing the video data word when the video data word is stored in the memory module. , Indicating a maximum of n memory modules among the n × n memory modules, and
As an address in the memory module for storing the video data word, an address corresponding to the position on the screen screen of the rectangle containing the stored video data word is designated, and during one writing cycle of the memory means. , A control means for controlling to store the video data word at the indicated address of the indicated maximum n memory modules.

[Action]

In the present invention, the time available to write to the memory module is increased by a function of n, as n data words are written at the same time than if they were written demultiplexed and sequentially, and the data is fast. Can be written.

[Embodiment] Prior to the description of this embodiment, an overall configuration of an example of the special effect device for a high definition video system described above will be briefly described with reference to FIG. Basically, the special effect device consists of two field memories, a field 0 memory (1) and a field 1 memory (2), a write address generator (3) and a read address generator (4). These circuits are interconnected by switches (5), (6), (7) and (8), each of these switches operating at the field frequency. The input data supplied at the input terminal (9) is transferred to the field 0 via the switch (5).
It is selectively supplied to the memory (1) or the field 1 memory (2). The output data selectively extracted from the field 0 memory (1) or the field 1 memory (2) via the switch (6) is supplied to the output terminal (10).
The write address generator (3) and the read address generator (4) are selectively and alternately connected to the field 0 memory (1) and the field 1 memory (2) by switches (7) and (8).

During operation of the special effects device, the input analog signal is sampled 2048 times per horizontal scan line, and the resulting sample value is pulse code modulated into an 8-bit word to form input digital data, which is applied to the input terminal (9). Supplied.
Depending on the position of the switch (5) and under the control of the write address generator (3), writing is alternated to the field 0 memory (1) and the field 1 memory (2). Not only is it easy to write or read the individual digital signals into or out of the appropriate memory (1) or (2), but also the position of the individual digital signals in the cathode ray tube screen raster can be changed to achieve the required. The calculation of the complex address required to achieve the special effect is performed either by controlling the signal supplied to the write address generator (3) via the input terminal (11) or via the input terminal (12). It can be achieved under the control of the signals supplied to the read address generator (4). The manner in which this calculation is done is not important to the present invention and is therefore not described in further detail here. When the entire field is written to the memory (1) or (2), the switches (5) to (8) change position and then the digital signal stored in that memory (1) or (2) is read out. It is continuously read out under the control of the address generator (4) and supplied to the output terminal (10), during which the digital signal for the next field is written in another memory (2) or (1). .

The invention relates in particular to the construction and operation of the memories (1) and (2), for example to transfer the data to the memories (1) and (2) in the required manner and at the very high speed as described above. You can write.

In FIG. 3, each of the memories (1) and (2) in FIG. 2 consists of an n × m memory array (21), where n is at least 2, and in this example n is Equivalent to eight memory modules (22). The actual physical location of the memory module (22) on the circuit board is the memory array (21)
It is understood that each memory module (22) is addressed by its row and column number of memory array (21) as shown in FIG. 3, although it is understood that it need not correspond to the locations shown in FIG. Each memory module (22) consists of a random access memory (RAM) and associated latch circuit. Each of the RAMs can store m 8-bit words, especially in this example m equals 16K, so the memory array (21) can store n ² m words as a whole, which is equivalent to 1 field of the video signal. Is enough.

Another view of the memory array (21) is that it has 8 rows and 8 columns, with 16K levels in depth. Therefore, to write a word to the memory array (21) and read a word from it,
The required address has level, row and column information.

FIG. 4 shows the relationship of the memory array (21) of FIG. 3 to the raster of the screen (31) of the cathode ray tube.

Each square in FIG. 4 corresponds to one level of the memory array (21), and the number in each square is each memory module (2 in FIG. 3).
Corresponds to the number of rows and columns in 2). Therefore, considering the screen (31) of FIG. 4, the first 8 of the first 8 scan lines
3 sample values are stored at the top level or level 0 of the memory array (21) of FIG. 3, and the next 8 sample values of the first 8 scan lines are at level 1 of the memory array (21). This is the same for all areas of the screen (31) that are stored.

During use of the memory array (21), up to eight 8-bit words corresponding to each sample value at up to eight adjacent collinear sample positions of the raster on the screen (31) are simultaneously written. The effect is that even if the sample positions on the same straight line adjacent to one or exactly two boundaries of the square in FIG. 4 overlap, the memory module (22)
None of these have more than one word written to it during each write cycle. This is the fifth
A brief description of why up to eight sample values are written during each write cycle rather than the usual eight is given below with reference to FIGS. 6 and 6. In fact, from the original digital data, the number of sample values selected for writing is usually eight, but this number is reduced due to special effect processing. Taking a simple example, if the special effects processing halves the linear dimension (Iinear dimension) of the image, then any eight selected adjacent collinear sample values would be Reduced to individual pieces.

In FIGS. 5 and 6, each of these squares is
Figure 4 shows the top left square and three directly adjacent squares. These boxes, which correspond to the levels of the memory module (22), start at 0 and proceed continuously along the top of the screen (31) and have the level address following the box of the next row etc. The level address of the first square in the square of the second row is N.

Now consider the example of FIG. This shows the writing of eight adjacent collinear sample values at 0 ° to the horizontal of the screen (31). To write these 8 sample values, 8 of the memory array (21)
The memory modules (22) are addressed simultaneously and supplied with each 8-bit word representing the sample value stored therein. Eight addresses are 0,2,3; 0,2,4; 0,2,5; 0,
2,6; 0,2,7; 0,2,8; 1,2,1 and 1,2,2, where the first number represents the level of each memory module (22), Two
The numbers represent the rows of the memory array (21) and the third numbers represent the columns of the memory array (21).

Now consider an example in FIG. This shows the writing of eight adjacent collinear sample values at 45 ° to the horizontal of the screen (31). To write these eight sample values, the memory modules (22) of the memory array (21) are simultaneously addressed and provided with each 8-bit word representing the sample values stored therein. 8
Addresses are 0,
3,2; 0,4,3; 0,5,4; 0,6,5; 0,7,6; 0,8,7; N, 1,8 and N + 1
It is 2,1.

From these examples, by arranging the video memory and having the write address generator (and calculator) (3) of FIG. 2, the address is presented in that way, and eight adjacent collinear sample values. Is the screen (3
1) It will be appreciated that it is not necessary to write two words to the same memory module (22) during the same write cycle, even if one or two boundaries between the top squares are crossed. While this configuration of memories (1) and (2) alleviates the timing problems described above considerably, it usually takes 64 addresses to access any 8 of the 64 memory modules (22). And one for each data bus, memory module (22), and eight 1:
There is the difficulty of having to provide a 64 demultiplexer. This requires a great deal of hardware, so the present invention further relates to reducing the hardware required to write data to the memories (1) and (2).

As mentioned above, the data written in any one write cycle has a maximum of eight sample values each corresponding to a maximum of eight adjacent collinear sample positions in the screen raster of the cathode ray tube. FIG. 7 shows three possible orientations of eight adjacent collinear sample positions, these methods being 0 ° to the horizontal of the screen (31) and to the horizontal of the screen (31). 45 ° and 90 ° or perpendicular to the screen (31). From FIG. 7, if a bus that is vertical to the memory array (21) of FIG. 3 is arranged, then there are eight buses in any direction from 0 ° to 45 ° with respect to the horizontal through this vertical bus. Data and address can be passed to the sample position of, and if a horizontal bus is provided for the memory array (21), it can be passed through this horizontal bus.
It can be seen that data and addresses can be passed for any of the 8 samples in any direction from 45 ° to 90 °.

FIG. 1 shows a structure of a memory device for video signals according to the present invention. A memory array (21) formed of 64 memory modules (22) and a memory array (21) directly related to the memory array (21) are provided. Memory modules collinear (22)
Addressing and addressed memory module (22)
And means for supplying the data to be written to.

The vertical bus group (41) has eight signal paths respectively connected to the eight memory modules (22) in each of the eight vertical columns of the memory array (21), and the horizontal bus group (41 Four
2) has eight signal paths all connected to eight memory modules (22) in each of the eight horizontal rows of the memory array (21). Each signal path of the vertical bus (41) is 8
Horizontal bus group (42) connected to individual buffer circuits (43)
Each signal path is connected to eight buffer circuits (44). On the input side of the buffer circuits (43) and (44),
Eight input buses denoted by input bus (0) to input bus (7) are connected in pairs. Data and address are supplied to the input terminals (45) and (46), and further supplied to the input bus (0) via the latch circuits (47) and (48). Although not shown, the input terminals (45) and (46) and the latch circuits (47) and (48) are provided for each of the other input buses (1) to (7). The vertical enable terminal (49) is connected to the buffer circuit (43), and the horizontal enable terminal (5
0) is connected to the buffer circuit (44). The buffer circuits (43) and (44) separate the bus groups (41) and (42) from each other.

Next, the operation will be described. 8 of cathode ray tube screen raster
When eight 8-bit words, each corresponding to a sample value at a number of adjacent collinear sample locations, appear for writing in the memory array (21) during one write cycle, the direction of the line with respect to the screen (31). Use vertical enable terminal (49) and horizontal enable terminal (50)
It is determined which of them should provide the enable signal. Assuming that the buffer circuit (43) is enabled, the data and address for each of the memory modules (22) will be transferred to the vertical buses (4) in the form of multi-bit words.
1) to the memory array (21). Three bits are provided to determine the exact memory module (22) selected. The 14 bits of the word indicate which of the 16K levels of the selected memory module (22) is being addressed and the 8 bits of the word are the data stored at that address.

Then, the write cycle is repeated for the next eight 8-bit words, in which case the horizontal bus group (42) is selected by supplying the enable signal to the horizontal enable terminal (50). If the line orientation is 45 ° with respect to the screen (31), then one of the buses (41) and (42) is used, and again the buses that were enabled during the previous write cycle are used again.

The sample values described above are considered luminance sample values, and a similar video signal memory device operating in the same manner can be provided for the color sample values.

The invention is applicable to video signal memory devices and frame memory devices for other types of television devices.
Also, the numbers n and m can be varied taking into account the required writing speed and the amount of stored video digital data. Also, the present invention may be used with other types of raster displays, so the display need not be a cathode ray tube screen.

Although one embodiment of the present invention has been described in detail with reference to the accompanying drawings, the present invention is not limited to this embodiment,
It should be understood that those skilled in the art can make various changes and modifications without departing from the gist of the present invention.

〔The invention's effect〕

As described above, according to the present invention, in the video signal memory device for storing the video data word corresponding to the sample value of the video signal at each sample position on the horizontal scanning line of the video signal forming the screen image of the raster display. A memory device for the video signal has n continuous rows in the horizontal scanning direction included in each square of m squares obtained by dividing the screen screen in the horizontal scanning direction and the vertical scanning direction and in the vertical scanning direction. It comprises n × n memory modules provided corresponding to each video data word of n consecutive n × n video data words, each memory module of said n × n memory modules being said video data A memory means having a capacity for storing m words, and storing the video data word in the memory means. A maximum of n memory modules out of the n × n memory modules are designated as the memory module for storing the video data word, and the memory module storing the video data word is stored in the memory module as an address in the memory module. The address corresponding to the position on the screen screen of the square containing the video data word to be stored is pointed to, and during one write cycle of the memory means, the pointed up to n memory modules are pointed to. A control means for controlling to store the above video data word is provided at the address, and the data can be written at high speed in one or more areas at the same time, which is used for a high definition video system or the like. Are extremely useful.

[Brief description of drawings]

1 is a block diagram showing an embodiment of a video signal memory device according to the present invention, FIG. 2 is a simplified block diagram showing a special effect device for a high definition video system, and FIG. 3 is a video signal according to the present invention. 2 is used in the device of FIG. 2 in a part of the configuration of the memory device of FIG. 4, FIG. 4 is a diagram showing the relationship between the memory device of the video signal of FIG. FIG. 6 is a diagram showing an example of the use of the video signal memory device of FIG. 3, and FIG. 7 is a diagram showing three possibilities for writing data to the video signal memory device of FIG. . (21) is a memory array, (22) is a memory module,
(41) is a vertical bus group, (42) is a horizontal bus group, (43),
(44) is a buffer circuit, and (47) and (48) are latch circuits.

Claims (1)

[Claims] 1. A video signal memory device for storing a video data word corresponding to a sample value of the video signal at each sample position on a horizontal scanning line of the video signal forming a screen image of a raster display. Of n × n video data words continuous in the horizontal scanning direction and n continuous in the vertical scanning direction included in each square of m squares obtained by dividing in the horizontal scanning direction and the vertical scanning direction. N × n memory modules provided corresponding to each video data word, and each memory module of the n × n memory modules has a memory means having a capacity for storing m video data words. A memory module for storing the video data word in storing the video data word in the memory means. A maximum of n memory modules out of the n × n memory modules as a module, and the stored video data word is included as an address in the memory module storing the video data word. An address corresponding to a position on the screen of a quadrangle is designated, and the video data word is stored in the designated address of the maximum n memory modules designated during one write cycle of the memory means. A video signal memory device, comprising: