JPH0831209B2 - Signal presence / absence detection circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal presence / absence detection circuit for detecting the presence / absence of a signal, particularly a signal presence / absence detection circuit suitable for reproducing a high-density record carrier such as an optical disk and easily digitized. It is about.

2. Description of the Related Art In recent years, high-density recording application products such as optical disks have been put into practical use one after another. In this type of product, so-called focusing control and tracking control are essential because of the high density. A signal presence / absence detection circuit is used to turn on / off the control circuit.

Generally, the above control is turned on as soon as a signal is found, and turned off after a predetermined time when there is no signal. This is because the desired signal is missed if the ON timing is delayed at the time of signal discovery, and if the signal is turned OFF immediately when the signal disappears, the control system is often turned OFF due to dropout and the control is disturbed.

An example of a conventional dropout detection circuit will be described below with reference to the drawings.

FIG. 6 is a block diagram of an example of a conventional signal presence / absence detection circuit, and FIG. 7 is a diagram for explaining its operation.

In FIG. 6, reference numeral 101 is a first envelope detector for extracting the envelope of the input signal 102, and the time constant is selected small so as to sufficiently follow the rapid amplitude fluctuation of the input signal. Reference numeral 103 is a second envelope detector similar to 101, but a slightly large time constant is selected so as not to follow a sudden amplitude fluctuation of the input signal. The outputs of the first envelope detector 101 and the second envelope detector 103 are compared in magnitude by the comparator 104, and the output 105 of the comparator 104 is compared.
Is the signal presence / absence detection signal.

Consider the case where the input signal includes a dropout as shown in FIG. 102 'in the above configuration. input signal
102 'is actually a very high frequency, but in FIG. 7 it is simulated and expressed as a low frequency.

In FIG. 7, a curve 111 is the output of the detector 101 of the first envelope, and changes substantially corresponding to the rapid amplitude fluctuation at the time of dropout. A curve (dashed line) 112 is the output of the second envelope detector 103, and does not follow the rapid amplitude variation of dropout. Also the signal
In the steady state 112, the DC potential becomes larger than the signal 111,
In the dropout state, the level shift and the gain adjustment are performed so as to be smaller than the signal 111. As a result, as is apparent from FIG. 7, the output of the comparator 104 is inverted after a predetermined time when the signal disappears and inverted after the predetermined time when the signal comes out.

The above-mentioned signal detection circuit has a drawback that the ON timing at the time of signal discovery is delayed, and a time constant capacitor for envelope detection is required, which is not suitable for miniaturization of equipment, and the process of digitalization of other equipment. Therefore, it does not match these digital circuits.

DISCLOSURE OF THE INVENTION In view of the above problems, the present invention provides a signal presence / absence detection circuit suitable for detecting the presence or absence of a signal with a digital circuit.

Means for Solving the Problems In order to solve the above problems, a signal presence / absence detection circuit according to the present invention comprises a dropout detecting means for detecting a no-signal state, and a signal delay using the output of the dropout detecting means as an input. Means and the output of the signal delay means and the output of the dropout detection means as inputs, the output of the signal delay means is inverted by the inversion of the output of the signal delay means when a no-signal state is detected, and the dropout detection means is detected when the signal is detected. And a logic circuit means for inverting the output by inverting the output.

The dropout detection means basically includes a comparator for determining a low level section of a signal and a counter for measuring the time, and the signal delay means includes a shift register, a counter and a signal delay circuit using a digital filter integration circuit. An AND circuit or an OR circuit is used as the logic circuit means.

With the above-described configuration, the present invention can digitize the signal presence / absence detection circuit, eliminate external components, reduce the size of the device, reduce the cost, and significantly improve the reliability.

Embodiment A signal presence / absence detection circuit according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 11 is a dropout detecting means for detecting a signal defect of the input signal 12, which is composed of a signal retriggerable multivibrator. Reference numeral 13 is a signal delay means using a shift register for delaying the output of the dropout detection means. The output of the signal delay means 13 and the output of the dropout detection means 11 are connected to the input of the logic circuit means 14. In this embodiment, a case where an AND circuit is used as the logic circuit means will be described. Using the output 15 of the logic circuit means 14 as the output of the signal presence / absence detection circuit Regarding the signal presence / absence detection circuit configured as described above,
The operation will be described below with reference to FIG.

FIG. 2 is a diagram for explaining the operation of the signal presence / absence detection circuit of FIG. 1. In FIG. 2, 12 'is an input signal having a dropout, and a broken line 21 is a trigger level of the retriggerable multivibrator. Is. The retriggerable multivibrator 11 which is a dropout detection means at steady signal is always retriggered so that the output 22 becomes low level and becomes high level when the signal has dropout. In FIG. 2, the signal 12 'is in fact very high frequency and therefore the time constant of the retriggerable multivibrator 11 is also very small, showing that the signal 22 changes to a high level as soon as dropout begins. The signal 23 is the output of the signal delay circuit 13 and is delayed with respect to the signal 22 by a predetermined time. AND circuit in which signals 22 and 23 are logic circuit means
Since it is connected to 14, its output 24 is inverted at the rising edge of the output signal of the signal delay means 13 and inverted at the falling edge of the signal of the dropout detection means 11. That is, the signal 24 is inverted with a delay of a predetermined time from the time when the signal of the input signal 12 'disappears, and is inverted immediately when the signal appears. The delay time until reversal when the signal disappears is about 0.1 seconds, the ideal time until reversal when the signal appears is zero, but in practice it is usually set to 10 to 50 microseconds. Is.

FIG. 3 is a diagram showing another embodiment of the present invention. Third
In the figure, 31 is a waveform shaper, which uses a comparator.
This output is connected to the up / down switching terminal of the first up / down counter 33. Clock signal 37 is first
Is connected to the clock input terminal of the up / down counter 33, and high / low time measurement of the up / down input terminal is performed by this clock signal. When there is no dropout in the input signal, the level of the reference signal of the comparator 34 is changed so that the content of the first up / down counter overflows, or an external signal is added / dropped to the up / down switching terminal (not shown). ). When the first up / down counter overflows or underflows, it is clamped to the maximum value or the minimum value inside the counter, respectively. The content value of the counter 33 is connected to one input terminal of the comparator 34. The output of the comparator 34 is connected to the up / down switching terminal of the second up / down counter 35 which is an integrating circuit. The second up-down counter 35 should be underflowed when the input to the up / down switching terminal is at a low level, but its content is set to a value slightly larger than all zeros. Further, when overflowing, it is configured to be clamped to all 1, and its value is set to be larger than the maximum value of the contents of the first up / down counter. The time constant of the second up / down counter as an integrator is selected to be large, and therefore the clock obtained by dividing the clock 37 by the first frequency divider 38 is used. Since such a frequency divider can be commonly used with other systems, the number of stages of the second up / down counter 35 can be reduced. The signal 39 becomes the dropout detection signal. The signal 39 is connected to an up / down switching input terminal of a third up / down counter 40, which is an integrating means, and outputs the output of the third up / down counter and a dropout detection signal 39.
Is connected to the AND circuit 41. The output 42 of the AND circuit 41 becomes the signal presence / absence detection signal. Since the time constant of the third up / down counter may be larger than that of the second up / down counter, the output of the first frequency divider 38 is further divided by the second frequency divider 43 to obtain a clock. Used.

The signal presence / absence detection circuit configured as shown in FIG.
The operation will be described with reference to FIGS.

4 and 5 are diagrams for explaining the operation of the signal presence / absence detection circuit of FIG. 3, where 12 ″ is an input signal having a dropout, and a broken line 51 is a waveform shaper.
31 thresholds. The dropout section is a section of the intersections 52 and 53 of the threshold value 51 and the input signal 12 ″, and the output of the section waveform shaper 31 is at a low level, and as a result, the first up / down counter 33 is at a low level section. Is regarded as long and the contents are all 1. The signal 54 in Fig. 4 indicates the output of the first up-down counter (corresponding to the contents of the counter) between the dropout occurrence point 52 and the rising edge of the signal 54. Although there is a time difference, this represents a measurement delay.This time difference does not matter even if it is several tens of microseconds.In the time after the dropout end point 53, the reverse operation occurs and the signal 54
Goes low again. The signal 55 in FIG. 4 represents the output signal of the second up / down counter 35 and is shown to be slightly more positively biased than the signal 54 prior to dropout inrush. When the output signal 54 of the first up / down counter 33 increases, the output of the second up / down counter also increases, but in the short time dropout shown in FIG.
, The dropout detection signal 39 changes almost the same time as the first up / down counter. The third up / down counter 40 is the integrating means of FIG. 1, and the AND circuit 41 is the same as the AND circuit used in the logic circuit means of FIG. 1, so the output of the third up / down counter 40 is the signal 56. It is obvious that the output 57 of the AND circuit 41 is inverted at the rising edge of the signal 56 and is inverted at the falling edge of the signal 39, as shown in FIG.

The input signal 12 ″ in FIG. 5 shows the case where the input signal is relatively correct after a long time dropout. In such a case, it is better not to detect this dropout as a dropout. This is because the tracking servo is cut off by the dropout signal.
Based on FIG. 5, the operation at the time of plunging into the dropout is the same as that of FIG. 4, but after plunging into the dropout, the output 55 of the second up / down counter 35 is the first at the point of time 60. The output value of the up / down counter 33 of will be exceeded.
As a result, the output 39 of the comparator 34 goes low. The high level section of the signal 39 in Fig. 5 is the section detected as dropout, but it is much shorter than the dropout of the input signal. Even if the servo system is cut for this time, there seems to be no abnormality in signal reproduction. I am doing it. The operations of the third up / down counter 40 and the AND circuit 41 are the same as in the case of FIG.

In FIG. 3, instead of the comparator 34, a logic circuit such as an AND circuit is used, and the second up / down counter 35
It is obvious that the same operation can be realized by simply using as a time measurement and adding both the carry signal and the carry of the first up-down counter to the AND circuit.

EFFECTS OF THE INVENTION As described above, according to the present invention, dropout detecting means for detecting a no-signal state, integrating means for receiving the output of the dropout detecting means, output of the integrating means and output of the dropout detecting means. And a logic circuit means for inverting the output of the integrating means when a signalless state is detected and inverting the output of the dropout detecting means when the signal is detected. As a result, the signal presence / absence detection circuit can be configured by a digital circuit, which achieves downsizing of the device, cost reduction, and high reliability.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG.
FIG. 4 is a waveform diagram for explaining the operation of the embodiment of FIG. 1, FIG. 3 is a block diagram for explaining another embodiment of the present invention, and FIG.
FIG. 5 is a waveform diagram for explaining the operation of the embodiment of FIG. 3, and FIGS. 6 and 7 are a circuit diagram and a waveform diagram showing an example of a conventional signal presence / absence detection circuit. 11 …… Dropout detection means, 13 …… Signal delay means, 14 …… Logic circuit means.

Claims (1)

[Claims] 1. A dropout detecting means for detecting a no-signal state, a signal delaying means for receiving an output of the dropout detecting means, an output of the signal delaying means and an output of the dropout detecting means. And a logic circuit means for inverting the output of the signal delay means upon detection of a no-signal state and inverting the output of the signal delay means, and inverting the output of the dropout detection means upon detection of the signal. A signal presence / absence detection circuit characterized by the above.