JPH0831272B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter referred to as dynamic RAM) having a plurality of memory banks.

[Conventional technology]

The structure of a voltage applying device for a storage gate in a conventional dynamic RAM is shown in FIG. 2, and a conventional technique will be described below with reference to FIG.

In the figure, (1) is a memory bank, and here is shown the case of having four memory banks. Each memory bank (1) includes a plurality of memory cells arranged in a matrix. Each memory cell has a MOS transistor for selection and a capacitor for information storage. The storage gate (not shown) constitutes one electrode of the capacitor of each memory cell.

(2) is an aluminum wiring surrounding the memory banks (1), and (3) is a voltage generation circuit applied to the storage gates of the memory banks (1).

Next, the operation will be described. The voltage generated by the voltage generating circuit (3) arranged in the center of the four memory banks (1) is applied in parallel to the aluminum wirings (2) surrounding each memory bank (1), It is applied from the aluminum wirings (2) to the storage gates arranged in the memory banks (1).

[Problems to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, it is necessary to apply a voltage to all storage gates by one voltage generating circuit arranged in the center,
The output impedance of the voltage generation circuit increases, which causes malfunction due to noise in the storage gate. Further, in order to reduce the resistance of the aluminum wiring, the width of the aluminum wiring must be made large, which causes a problem that the chip area is increased.

The present invention has been made to solve the above problems, by suppressing the increase of the chip area and lowering the output impedance of the voltage generating circuit,
It is an object of the present invention to provide a semiconductor memory device in which the circuit does not malfunction due to the noise.

[Means for solving problems]

A semiconductor memory device according to the present invention is a first voltage generation circuit which is provided commonly to a plurality of memory banks, and which applies a predetermined voltage to one electrode of a capacitor of a memory cell belonging to each of the plurality of memory banks. In a semiconductor memory device provided with, provided corresponding to each memory bank,
It is characterized in that a second voltage generating circuit for applying a predetermined voltage to one electrode of the capacitor of the memory cell belonging to the corresponding memory bank is provided.

Furthermore, a metal wiring for connecting one electrode of a capacitor of a memory cell belonging to each memory bank and one electrode of a capacitor of a memory cell belonging to another memory bank may be provided.

[Action]

In the semiconductor memory device according to the present invention, the first voltage generating circuit is provided commonly to the plurality of memory banks, the second voltage generating circuit is provided for each memory bank, and the first gate is provided at the storage gate of each memory bank. A predetermined voltage is applied from both the second voltage generating circuit and the second voltage generating circuit.
Therefore, the impedance between the arbitrary position of the storage node of each memory bank and the voltage generation circuit becomes smaller as compared with the conventional case in which only the first voltage generation circuit is provided, and malfunction due to noise in the storage gate is prevented. .

Further, by providing a metal wiring for connecting the storage node of each memory bank to the storage node of another memory bank, the impedance between the arbitrary position of the storage node of each memory bank and the voltage generation circuit is further reduced. Therefore, malfunction due to noise of the storage gate can be prevented more reliably.

〔Example〕

 Hereinafter, the present invention will be described in detail.

FIG. 1 shows a dynamic RAM according to an embodiment of the present invention.
FIG. In the figure, (1) is a memory bank, and here, as an example, a case is shown in which four memory banks (1) are provided on a chip. Reference numeral (2) is aluminum wiring around the memory banks (1) and is connected to each other. (3a) to (3e) are voltage generation circuits for the voltage applied to the storage gate, and are the four corners of the chip (3a) to (3a).
A total of five (3d) and (3e) are arranged.

Next, the operation will be described. Voltage generation circuit (3a) ~
The voltage generated by (3e) is applied to the storage gate (not shown) arranged in each memory bank (1) through the aluminum wiring (2) surrounding each memory bank (1). Now, consider the voltage applied to the portion A of the storage gate in the figure. There are three voltage generating circuits (3a), (3d), and (3e) at a short distance from the point A, and the voltage at the point A is kept constant by these three voltage generating circuits. Can be regarded as As a result, the impedance at point A is
The distance to the voltage generation circuit is shortened and the voltage generation circuits are arranged in parallel, which reduces the number of malfunctions and prevents malfunction due to noise. Furthermore, the aluminum wiring width can be made small by the reduction of the impedance, and the chip area can be reduced as a whole even in consideration of the increase in the area of the voltage generating circuit.

〔The invention's effect〕

As described above, according to the present invention, the first voltage generating circuit common to the plurality of memory banks is provided, and the second voltage generating circuit is provided for each memory bank. The impedance between an arbitrary position and the voltage generating circuit can be reduced.
Therefore, the aluminum wiring width can be reduced as much as the impedance is reduced, so that the chip area can be reduced and a semiconductor memory device with less circuit malfunction due to noise can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a dynamic RAM according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of a conventional dynamic RAM. In the figure, (1) shows a memory bank, (2) shows aluminum wiring, and (3a) to (3e) show voltage generating circuits. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display area H01L 27/04 H01L 27/04 B

Claims (2)

[Claims] 1. A semiconductor provided with a first voltage generating circuit which is provided in common to a plurality of memory banks, and which applies a predetermined voltage to one electrode of a capacitor of a memory cell belonging to each of the plurality of memory banks. A memory device is provided with a second voltage generating circuit provided corresponding to each memory bank and for applying a predetermined voltage to one electrode of a capacitor of a memory cell belonging to the corresponding memory bank. Semiconductor memory device. 2. A metal wiring for connecting one electrode of a capacitor of a memory cell belonging to each memory bank and one electrode of a capacitor of a memory cell belonging to another memory bank. The semiconductor memory device according to claim 1.