JPH0831846B2 - Phase comparison circuit - Google Patents

Description

DETAILED DESCRIPTION [Outline] A phase comparison for controlling the output of a phase-locked loop that generates a clock with a predetermined free-running oscillation frequency based on the result of phase comparison between a data write clock and a read clock. Concerning the circuit, it is composed of multiple stages of memory elements for the purpose of realizing a phase comparison circuit that is independent of the number of memory stages and the duty factor of the reference clock, and that does not erroneously control the clock generation circuit. It has the same speed as the input data and the first phase read clock from the read clock generation means for generating a plurality of phase read clocks corresponding to the memory stages to read the input data written in the memory. Compares the phase with the first phase write clock for writing the input data to the first stage of the memory based on the clock And a comparison result output output from the comparison means by a read reference signal at a predetermined speed for accessing the read clock generation means output from the clock generation means including a phase locked loop having a predetermined free-running oscillation frequency. And a synchronization means for restarting.

[Industrial applications]

The present invention relates to a phase comparison circuit that controls the output of a phase locked loop that generates a clock having a predetermined free-running oscillation frequency and a predetermined speed based on the phase comparison result of a data write clock and a read clock.

For example, as one of the synchronization processes for correctly reproducing a signal in a digital transmission system, a stuff synchronization system is adopted in which synchronization is achieved by inserting / removing a stuff pulse.

In such a case, the pulse stuff transmission / reception side uses a phase locked loop (hereinafter referred to as PLL) including a buffer memory, a read clock, a write clock, and a phase comparison circuit, a voltage controlled oscillation circuit (hereinafter referred to as VCO), and the like. By inserting / removing the stuff pulse and converting the clock frequency, synchronization is achieved.

The buffer memory at this time uses a plurality of stages of FIFO memory elements, converts serial data into a plurality of parallel data for writing, and converts parallel data into serial data while reading to convert the clock frequency. .

It is necessary to perform such conversion irrespective of changes in the number of stages of the buffer memory and the duty ratio of the clock, and to reduce the jitter generated during conversion.

[Conventional technology]

FIG. 4 is a block diagram for explaining a conventional example, FIG. 5 is a diagram for explaining a processing situation in the conventional example, FIG. 6 is a block diagram for explaining another conventional example, and FIG. 7 is a process in another conventional example. The figure explaining each situation is shown, respectively.

The conventional example shown in FIG. 4 is an example in which the number of stages of the memory 1 is set to 5 bits. At this time, as a clock phase to be compared by the phase comparison circuit 4, the third phase write clock φ3 (= φn /
2) and the case where the read clock φ1 of the first phase is used.

The write clock generation circuit 2 generates n-phase write clocks .phi.1 to .phi.n from a write reference clock sent in synchronization with write data.

The write clocks φ1 to φn of each phase are n of the memory 1.
It corresponds to each stage (bit). Similarly, the read clocks φ1 to φn of each phase generated from the read clock generation circuit 3 also correspond to n stages (bits) of the memory 1.

The memory 1 converts serially input write data by writing clocks φ1 to φn at each stage (bit) in parallel and holds the writing, and when reading by the reading clocks φ1 to φn, serially converts and reads. .

The clock generation circuit 5 is a digital PLL (hereinafter referred to as DPLL) formed by the read clock generation circuit 3 and the phase comparison circuit 4.
(Referred to as a), the comparison result signal from the phase comparison circuit 4 is used as a DC component, and the free-running oscillation frequency is changed by the magnitude DC component, and this is generated as a read reference clock.

The basic structure of the DPLL is to compare the phase of a digitally converted input signal with a signal output from a digital voltage controlled oscillator (hereinafter referred to as VCO), and the comparison result is used as a digital VCO control signal via a digital filter. It is configured to be applied and, on the one hand, converted into analog and output as an output signal.

FIG. 5A shows a situation in which write data is converted into parallel data and written. That is, when writing the 5-bit data A to E to the memory 1, the data A is written at the write clock φ1.
And write data E at the write clock φ5.

As the phase for reading the memory 1 at this time, it is safest to start the reading from an intermediate phase position of the write clocks φ1 to φ5 against the clock phase variation.

That is, since the timing of write data to the memory 1 and the timing of reading are asynchronous and the speeds are different,
If the reading is started at the same time when the writing of the data to the memory 1 is started, the old data may be read.
If the reading of data is started after the writing of data into the memory, the processing time becomes long and other problems occur.

Therefore, in the case of the above-described 5-bit data A to E, the reading of the data A is set to be started at the time when the writing of the data C is completed at the write clock φ3.

Therefore, the phase comparison circuit 4 performs a phase comparison between the write clock φ3 and the read clock φ1, and when the phases match, the comparison result output is not output at the “0” level, but “H” depending on the shift amount. Or it outputs the "L" signal.

The clock generation circuit 5 receives the comparison result signal ',
Controls the cycle of the read reference clock. That is, as shown in FIG. 5 (B), when the comparison result signal 'is "H", the clock generating circuit 5 controls the cycle to be short, and when it is "L", the cycle is controlled to be long. To occur.

Therefore, as shown in FIG. 5 (C), the phase of the read clock φ1 moves forward and backward with respect to the write clock φ3.

In the conventional example shown in FIG. 4 described above, for example, the number of stages of the memory 1 is changed from 5 bits to 10 bits, and the phase comparison circuit 4
If the write clock φ3 and the read clock φ1 are used for the phase comparison position in the same manner as in the case of 5 bits, FIG.
As indicated by, the margin before and after the read clock φ1 varies.

That is, the front margin varies with 2 bits and the rear margin varies with 8 bits, and there is a possibility that the data reading may read the old data depending on the width of this variation. Need to be uniform.

On the other hand, in another conventional example shown in FIG.
1 and a read clock φ1 have two flip-flop circuits (hereinafter referred to as FF circuits) 61 and 62, and an exclusive OR circuit that performs an exclusive OR operation on the outputs of the FF circuits 61 and 62 (hereinafter (Referred to as an E-OR circuit) 63.

Further, the PLL that constitutes the clock generation circuit 7 at this time is
As shown in FIG. 7, the time difference between the “H” time and the “L” time of the phase comparison result signal ″ is integrated, and the cycle of the read reference clock is changed when the sum of these differences reaches a certain value. To control.

Therefore, in the conventional example shown in FIG. 6, it is not necessary to change the phase position to be compared even if the number of memory stages is changed, and the duty factor of the reference clock is irrelevant.

[Problems to be Solved by the Invention]

As described above, in the conventional example shown in FIG. 4, it is necessary to change the phase position to be compared each time the number of memory stages is changed.
Moreover, in order to set the position of the read clock with respect to the write clock to the center position, the duty factor of the write clock to be compared needs to be 50%.

On the other hand, in the conventional example shown in FIG. 6, even if the number of memory stages is changed, it is not necessary to change the phase position to be compared, and moreover, it is irrelevant to the duty factor of the reference clock. Since the edge is asynchronous with respect to the read reference clock, the clock generation circuit 7 may be erroneously controlled.

It is an object of the present invention to realize a phase comparison circuit which is irrelevant to the number of memory stages and the duty factor of a reference clock and which does not erroneously control a clock generation circuit.

[Means for solving the problem]

 FIG. 1 shows a block diagram illustrating the principle of the present invention.

Reference numeral 81 in the block diagram of the principle of the present invention shown in FIG. 1 indicates a read for generating read clocks .phi.1 to .phi.n of a plurality of phases corresponding to the memory stages in order to read input data written in the memories of a plurality of stages. The phase of the first phase read clock φ1 from the clock generating means 30 is compared with the phase of the first phase write clock φ1 for writing the input data to the first stage of the memory based on the clock having the same speed as the input data. Reference numeral 82 indicates a read reference signal at a predetermined speed for accessing the read clock generating means 30 output from the clock generating means 70 including a phase-locked loop having a predetermined free-running oscillation frequency and output from the comparing means 81. It is a synchronization means for resetting the output of the comparison result, and the means for solving this problem is provided by including such means.

[Operation] The first-phase write clock φ1 which is the timing for writing data to the first-stage memory and the first-phase read clock which is the timing for reading data from the first-stage memory .phi.1 is compared in phase by the comparison means 81, and the comparison result output is corrected by the synchronization means 82 at the timing of the read reference clock for accessing the read clock generation means 30 output from the clock generation means 70. The phase comparison position of the read clock with respect to the write clock can always be maintained at a fixed position without irrelevant control of the clock generation means 70 regardless of the number of stages or the duty factor of the reference clock. Become.

〔Example〕

The gist of the present invention will be specifically described below with reference to the embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG.
Each of the figures is a view for explaining a processing situation in the embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings.

The phase comparison circuit 80a of the present invention shown in FIG. 2 is an embodiment of the phase comparison means 80 including the functional blocks described below, and the phase comparison circuit 80a shown in FIG. Comparing section consisting of FF circuits 61 and 62 and E-OR circuit 63
81a, the synchronizing means 82 is composed of an inverter circuit 82b and a synchronizing section 82a composed of two FF circuits 82c, 82d.

Further, the memory 1 of this embodiment has the same contents as described with reference to FIG. 4 when the number of memory stages is 5 bits, and the write clocks φ1 to φ5 and the read clock φ1 at that time.
~ Φ5 phase comparison is the first phase, write clock φ
1 and the read clock φ1.

The output of the comparison unit 81a for comparing the two clocks φ1 is the signal in the upper stage of FIG.
The signal obtained by re-counting and synchronizing with the read reference clock (signal) in the synchronizing unit 82a is the signal shown in the lower part of FIG. 3C (shown by the synchronous phase comparison output).

The clock generation circuit 70a of the present embodiment has the same contents as described with reference to FIG. 7, and integrates the time difference between the "H" time and the "L" time of the output of the synchronizing section 82a and sums the difference. When a certain value is reached, control is performed to change the cycle of the read reference clock (signal).

At this time, since the output of the synchronization unit 82a is synchronized with the read reference clock (signal), the clock generation circuit 70a
Is prevented from being erroneously controlled.

〔The invention's effect〕

According to the present invention as described above, erroneous control is applied to a clock generation circuit that generates a reference signal for creating a read clock regardless of the number of memory stages and the duty factor of a reference clock. It is possible to realize a phase comparison circuit that does not have any.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a processing situation in the embodiment of the present invention, and FIG. FIG. 5 is a block diagram for explaining a conventional example, FIG. 5 is a diagram for explaining a processing state in the conventional example, FIG. 6 is a block diagram for explaining another conventional example, and FIG. 7 is a diagram for explaining a processing state in another conventional example. , And are respectively shown. In the figure, 1 is a memory, 2 is a write clock generation circuit, 3 is a read clock generation circuit, 4,6 are phase comparison circuits, 5,7,70a are clock generation circuits, 30 is a read clock generation means, 61,62, Reference numerals 82c and 82d denote FF circuits, 70 denotes clock generation means, 80 denotes phase comparison means, 80a denotes phase comparison section, 81 denotes comparison means, and 81a denotes comparison section.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display area H04L 7/033

Claims (1)

[Claims] 1. Read clock generating means for generating read clocks (.phi.1 to .phi.n) of a plurality of phases corresponding to the memory stages for reading input data written in a memory composed of a plurality of stages of memory devices. Based on the first phase read clock (φ1) from (30) and the clock having the same speed as the input data, the first phase write clock (φ1) for writing the input data into the first stage of the memory. ) And a predetermined speed for accessing the read clock generating means (30) output from the clock generating means (70) comprising a phase locked loop having a predetermined free-running oscillation frequency. And a synchronization means (82) for correcting the output of the comparison result output from the comparison means (81) by the read reference signal ().