JPH0831966B2 - Real-time video processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a real-time signal processor for implementing digital signal processing such as digital filtering and high-efficiency coding with software on moving image signals such as television signals. .

(Prior art) The advantage of real-time digital signal processing is that it can realize filters and modulators / demodulators with high accuracy or high stability that cannot be realized by analog signal technology. It is possible to easily realize an adaptive filter and the like. Furthermore, by incorporating the results of digital LSI technology, which has been rapidly developing in recent years, it is possible to reduce the size and power consumption of real-time digital signal processing circuits, and gradually replace analog circuits and apply them to higher functionality. Is progressing to. For more detailed advantages of digital signal processing, see pages 1280 to 1284 (Reference 1) of the December 1982 issue of the Institute of Electronics and Communication Engineers.

Digital signal processing, which has many advantages like this,
On the other hand, it has the drawback of requiring a huge amount of calculation.
For real-time signal processing, sampled input signal 1
It is necessary to perform the given digital signal processing within the sampling period per sample. For example, when telephone speech (8KHz sampling) is subjected to the 4th-order cyclic digital filter processing, multiplication is performed within 125 microseconds. Eight calculations are required. Therefore, the frequency bandwidth is more than 1000 times wider than that of telephone voice, and therefore the signal processing circuit for telephone voice is at least 1000 times faster than the signal processing circuit for telephone voice in order to perform signal processing on video signals with a sampling period of 1/1000 or less. A circuit is needed.

Regarding digital signal processing for signals in the voice domain, it is often desired to change various parameters or part of the signal processing algorithm in order to perform high-speed digital signal processing. Therefore, there is a strong demand for a signal processing device that can change algorithms and parameters by software. As hardware for performing digital signal processing by conventional software, I-I-I-I
Journal of Solid State Circuits (IE
EE Jounral of Solid-State Circuits) SC-16 Vol. 4 (August, 1981), page 372 (reference 2), and the like are signal processors and the like. A typical application example of this signal processor is 1982. Proceedings of International Conference of Acoustics Speech and Signal Processing published by AY
tional Conference on Acoustics, Speech, and Signal
Processing), pages 960 to 963 (reference 3) have 32kbps ADPCM, but they are also targeted for telephone voice processing.

With such a conventional processor format, it is not possible to easily expect a speedup of 1000 times or more no matter how much the speed of the arithmetic circuit can be increased, so software that can perform high-speed digital signal processing that can be performed with audio signals for moving image signals A one-chip processor with control cannot be realized.

Therefore, one screen is divided into multiple partial screens, as described in Volume 2, pages 2-5 (Reference 4) of the Proceedings of the 59th Annual Conference of the IEICE Communications Division (published in October 1959). , A multiprocessor that assigns a signal processor to each, divides it into assigned partial screens, assigns a signal processor to each, and processes the assigned partial screens with a sampling cycle (33.3 msec) of one screen. There is a processor-type video processor.

(Problems to be Solved by the Invention) The moving picture processor of Document 4 processes a partial area of one screen in 1/30 seconds, and realizes real-time processing and digital signal processing by software control. Is what you can do. However, in the meantime, multiple unit signal processors capture and store all the necessary signals in the partial screens that are in charge of processing.
It is necessary to hold all the outputs of the processing section in charge, and there is a disadvantage that the input and output memories become very large.

It is an object of the present invention to provide a software-controlled circuit that can perform high-level digital signal processing on a moving image signal such as a television signal and can be realized with a relatively small amount of input and output memory.

(Means for Solving Problems) According to the present invention, a predetermined input portion position is defined by a vertical synchronizing signal indicating the beginning of one screen of a moving image signal such as a television signal and a horizontal synchronizing signal indicating the beginning of one scanning line. A control unit for generating a signal and an output partial position signal; an input unit for inputting an input partial position signal from the control unit and for inputting a partial screen signal designated by the input partial position signal of a separately input moving image signal; Connected to the capture part,
A processing unit that performs signal processing on the moving image signal captured by the capturing unit in an arbitrary access order until the capturing of the next partial screen starts, and an output order of the processing unit are connected, and the processing result of the processing unit is connected. A plurality of unit processors each of which stores the output of the stored processing result at a partial position designated by the output partial position signal separately input from the control unit; An input bus for supplying the vertical synchronizing signal, the horizontal synchronizing signal, and the moving image signal to each of the processors, and an output bus for transmitting the output partial signal output from each of the plurality of unit processors, one scanning line Alternatively, small areas in the partial screen of the one scanning line or the plurality of scanning line times are processed in an arbitrary access order within a plurality of scanning line times. That.

(Operation) The present invention divides a partial screen for one scanning line or a plurality of scanning lines into a plurality of small partial screens, and allocates one unit signal processor to each partial screen to provide a plurality of sub-screens. Real-time processing of moving images is realized by the unit signal processor of. Usually, a moving image signal (eg NTSC signal) has a bandwidth of about 4.3MHz, and if it is treated as a one-dimensional signal suitable for transmission, it is necessary to sample at about 10MHz. In this case, one sample is generated within a period of about 100nsec. It is necessary to perform the processing around. However, if this moving image signal is processed for a small partial area (one sample or several sample points) that is one scanning line time (an integral multiple of 63.5 microseconds), the processing speed becomes equivalent to the processing in the audio band. Then, in processing all the sampling points of one scanning line or a plurality of scanning lines, a plurality of unit signal processors are prepared, and a small partial region to be processed is preset between each unit signal processor, and each unit signal processor is set. The signal processor selectively takes in a moving image signal required for the assigned processing portion. In this case, the intake portion is generally larger than the processing portion. For example, the two-dimensional sampling signal of coordinates (i, j) is x
(I, j), this two-dimensional signal is the Inbalus bond {h
Consider that it is suitable for the filter of (i, j)}. in this case,
Assuming that the processing portion is the partial screen O shown by the equation (1) and the impulse response bonus h (i, j) belongs to the section P of the equation (1), the output y (i, j) is (2). Given by the formula.

O = {(i, j):-NiN, -NjN} P = {(i, j):-MiM, -MjM} (1) Therefore, the input signal required to obtain the output screen O is {x
From the expressions (1) and (2), the capture screen Q of (i, j)} is Q = {(i, j) :-( M + N) i (M + N),-(M + N) j (M + N)} ( 3)

FIG. 2 shows the relationship between the data capture screen Q and the processing screen O (equal to the output screen). One side 2 (M +
A square capture screen Q of N) and a square processing screen O of 2N on each side are shown. The expression (2) is called a convolution operation, but other correlation operations can be expressed almost in the same way as the expression (2), and the relationship between the captured screen and the processed image can be expressed as shown in FIG.

As described above, in the convolution or correlation calculation, which is the basic operation of digital signal processing, the captured image area and the processed image area are different, but if the processed image area is fixed, the information of the entire screen becomes unnecessary. Further, N representing the size of the partial screen can be made very small. Therefore, a partial screen of one scanning line or a plurality of scanning lines is divided into a plurality of small partial areas, a plurality of unit signal processors for processing each small partial screen are assigned, and each unit signal processor signal processor can be independently operated. In other words, each unit signal processor only needs to process the allocated small partial screen during the above-described processing time (one scanning line or plural scanning line time), and many unit signal processors are operated in parallel. This enables real-time video processing. Also, each unit signal processor is 1
Input data necessary for processing the divided small partial area in the partial screen for scanning lines or multiple scanning lines time is stored and output data as the processing result is stored only for the given processing area. Often, after the processing is completed, the input and output data of the small screen, which is the processing portion for the time of the next one scanning line or plural scanning lines, can be stored in the same place as the previous data. In comparison with the one that stores a given sub-screen of, when the example of the present invention processes in one scanning line time, the best case is 1/525, when processing in multiple scanning line time, the best case Requires only 1/525 scanning lines times the input / output memory capacity.

(Example) An example of the present invention will be described with reference to the drawings. First
The figure shows an embodiment of the present invention in which four unit signal processors are used. The vertical synchronizing signal input terminal 1, the horizontal synchronizing signal input terminal 2, the moving image signal input terminal 3, the unit signal processors 4, 5, 6, 7 are shown. It is composed of a vertical sync signal output terminal 8, a horizontal sync signal output terminal 9, and a video signal output terminal 10. The unit signal processors 4, 5, 6 and 7 are a capturing section 11 and a processing section 1, respectively.
2. The output unit 13 and the control unit 14 are included. Capture unit 1
1 is a memory circuit in which the write address is incremented by 1 and can be read at random, and the output unit 13 is a first-in first-out memory circuit. Details of the processing unit 12 and the control unit 14 will be described later.

The vertical synchronizing signal input from the terminal 1 and the horizontal synchronizing signal input from the terminal 2 are unit signal processors 4,5,6,7.
Are input to the respective control units 14. The control unit 14 identifies the time point at which a signal belonging to a pre-assigned pre-assigned partial area is input to the terminal 3 from the input vertical and horizontal synchronizing signals, and notifies the pre-loading unit 11 as a pre-loaded signal. The capturing unit 11 captures and stores the moving image signal input to the terminal 3 according to the capturing signal transmitted from the control unit 14.

The control unit 14 also transmits an execution signal to the processing unit 12 when a signal of a predetermined capturing partial area is input from the vertical synchronization signal input from the terminal 1 and the horizontal synchronization signal input from the terminal 2 and the processing is performed. The unit 12 performs predetermined digital signal processing from the execution signal input from the control unit 14, for example, the convolution calculation of the above-mentioned equation (2) with respect to the captured moving image signal stored in the capturing unit 11, and the calculation result Is written in the output unit 13.

The control unit 14 further detects a predetermined processing partial area output time point from the vertical synchronizing signal input from the terminal 1 and the horizontal synchronizing signal input from the terminal 2, detects the processing partial area output time point, and detects the processing partial area. Then, the output command signal is transmitted to the output unit 13, and the output unit 13 sequentially outputs the processed data terminals processed and written by the processing unit 12 from the control unit 14 to the output unit 10.

FIG. 3 shows an example of a capture signal, an execution signal, and an output command signal used by the unit signal processors 4 and 5 in the moving picture processor having the configuration of FIG. In order to simplify the explanation, the moving image signal used in FIG.
The case where one scan line time is processed by four unit signal processors is shown. The vertical synchronizing signal applied to the terminal 1 in FIG. 1 signals the start of one screen and is a reference signal when processing is performed for each of a plurality of scanning lines. However, since the processing for each scanning line is described now,
It is necessary only to indicate the area that needs to be processed (the time when the video signal is actually present), and is omitted in the description of FIG.
The horizontal synchronizing signal ((a) in FIG. 3) applied to the terminal 2 in FIG. 1 indicates the start of one scanning line. In the unit signal processor 4 which processes the first first small area, the control unit 14 Of the execution signal 1 (FIG. 3 (b)), and continues the acquisition command until the end of the acquisition area. (C)) As a result, the processing unit 12 may perform signal processing from the rising edge of the execution signal 1 to the next rising edge of the fetch signal 1. The control unit 14 also issues an output command to the output unit 13. Signal 1
Communicate (Fig. 3 (d)). This output command signal 1 is also considered as a position signal of a small processing area of the unit signal processor 4. As described with reference to FIG. 2, since the acquisition partial screen is generally larger than the processing partial screen, the time during which the acquisition signal 1 is turned on in the signals corresponding to each of FIGS. 3 (b) and 3 (d). Is longer than the output command signal 1.

The signals shown in FIGS. 3 (e), (f), and (g) are the take-in signal, the execution signal, and the output command signal of the unit signal processor 5 which processes the second small area. Figure 3 (e)
The relationship between (g) and (g) comes from the difference between the capture partial screen and the processing partial screen shown in FIG. The processing time allowed for the processing unit 12 of the unit signal processor 5 is from the rising of the signal in FIG. 3 (e) to the rising of the output command signal, and this length is the processing unit of the unit signal processor 4.
The same as the time allowed for 12. Although the control signals of only the unit signal processors 4 and 5 have been described above with reference to FIG. 3, the unit signal processors 6 and 7 are similarly operated. Since the time when each unit signal processor outputs is only when each output command power signal is on,
The processed moving image signal is output to the moving image output terminal 10 in the figure in the format shown in FIG. However, here, FIG. 3 (h)
A, B, C, and D are the unit signal processors
It means the output from 4,5,6,7. Therefore, the processed moving image signal is continuously output from the terminal 10.

FIG. 4 is a diagram showing an embodiment of the control unit 14 used in the unit signal processors 4, 5, 6, and 7, and includes a vertical synchronization signal input terminal 20, a horizontal synchronization signal input terminal 21, a capture signal output terminal 22, Execution signal output terminal 23, output command output terminal 24, column counter 25, row counter 26, read-only memories 27, 28
It is composed of gate circuits 29, 30, 31, 32 and a clock signal input terminal 33. The read-only memory 27 is a 3-bit output,
The first bit is programmed to output "1" when the input address value matches the line number on the capture screen, and outputs "0" for the other, and the second bit executes the input address value. It is programmed to output "1" for the line number on the screen at the time when you want to output a command, and "0" for the others, and the third bit is the line number of the processing area as the input address value. It is programmed to output "1" for the matching and "0" for the other.

Similarly, the read-only memory 28 outputs 3 bits, and the first bit is programmed to output "1" when the input address value matches the column number of the captured screen, and outputs "0" for the others. The 2nd bit is programmed to output "1" for the column number on the screen when the value of the input address is to output the execution command, and "0" for the others. Bits are programmed to output "1" when the value of the input address matches the column number of the processing area, and output "0" for the others.

When the vertical sync signal is input from terminal 20, the row counter
26 is reset, and when the horizontal synchronizing signal is input from the terminal 21, the column counter 25 is reset and the row counter 26 is incremented. Assuming that the control unit of the unit processor 4 for processing the first small area in FIG. 1 is considered, the value of the column counter is 0 and the read-only memory 28 is used.
Outputs "1" at the first bit indicating the capture screen and the third bit indicating the output screen, and the second bit is "0". Therefore, the gates 29, 30, and 31 output "1" to the fetch signal terminal 22, "0" to the execution signal output terminal 23, and "1" to the output command output terminal 24, respectively. The sampled video signal is the first
Every time it is applied to the terminal 2 in the figure, a signal is applied to the clock terminal 33 in FIG. For this reason, the first bit of the read-only memories 28, 27 outputs "1" as long as the column counter 25 and the row counter 26 indicate the columns and rows belonging to the capture screen, and the gate 29 thus displays the capture screen. "1" is output to the terminal 22 for the sampling position to which it belongs.

Similarly, the read-only memory is provided only when the column counter 25 and the row counter 26 indicate the values of the column and the row to instruct the start of processing.
28 and 27 each output “1”, and as a result, the gate 30 is connected to the terminal 23.
"1" is output as an output command signal to. Similarly, the read-only memories 28 and 27 each output "1" only when the column counter 25 and the row counter 26 show the values of the column and row corresponding to the output screen, and as a result, the gate 31 outputs an output command to the terminal 24. "1" is output as a signal.

FIG. 5 is a diagram showing a configuration example of processing units in the unit processors 4, 5, 6, and 7 of FIG.
Register 41, gate 42, input terminal 43 from capture unit, address output terminal 44 to capture unit, output unit to output unit 45, address output unit to output unit 46, write signal output terminal 47 to output unit, execution It is composed of a signal input terminal 48 and a capture section output prohibition signal output terminal 49. It is assumed that the signal processor 40 uses the μPD7720 manufactured by NEC described in Reference 2. The μPD7720 is a signal processing processor that has a multiplier and an adder inside and has a unique bus configuration. Details are given in Reference 2. The μPD7720 is designed so that interrupt processing can be activated when a signal arrives at the interrupt input terminal (INT), and further programmable output bits.
I have P1 and P2. Input / output is performed via a bidirectional parallel bus (D), and when a signal is input to the write terminal (W), the write terminal (W) is used as an input direction bus.
Used as an outbound bus when no signal comes in. Now, when an execution signal from the control unit 14 in FIG. 1 is applied to the terminal 48 in FIG. 5, the signal processor 40 starts digital signal processing as interrupt processing. Therefore, the input data from the capture unit 11 in FIG. 1 is required. First, the required address is prepared in the port D and the bit output port is prepared.
Output "1" from P1. At this time, the gate 42 outputs "0", the data of the boat D can be output from the signal processor 40 to the outside, and the address is stored in the register 41. Then P1
Is set to "0", the contents of the register 41 are transmitted to the capturing unit 11 via the terminal 44, and the corresponding data is input from the terminal 43 to the port D. Similarly, to transfer the data processed by the signal processor 40 to the output unit 13, the output unit 13
In order to specify the address to, the required address is prepared in port D, bit "1" is output from bit P1, and register 41
Write the address to. This address is transmitted to the output unit 13 via the output terminal 46. Next, the processed data is prepared in the port D and "1" is output from the bit output port P2.
At this time, the gate 42 outputs “0”, the port D is in a state of being output from the signal processor 40 to the outside, and
The data on the boat D is transmitted to the output section through the terminal 45 in order to notify the capturing section of the output inhibition through the output terminal 49. The “1” of the bit output port P2 is transmitted to the output unit via the terminal 47, and commands the writing of the data transmitted from the terminal 45 to the output unit.

 The present invention can be implemented as described above.

Although the read-only memory is used for the control unit in the above-described embodiments, the positions of the predetermined captured partial image and the processed partial image can be dynamically changed by replacing the read-only memory with a random access memory or the like.

Although the signal generated by the control unit is set at the end of the fetch signal, it may be set in the middle of the fetch signal by a program, and such a change is also included in the scope of the present invention.

Further, in the present invention, the control unit for designating the positions of the captured partial image and the processed partial image is dispersed in each unit signal processor, but it is modified so that these are centralized and only the control signal is distributed to each unit signal processor. However, this does not change the intention of the present invention.

Furthermore, since only the areas of the capture screen and the processing screen differ between unit signal processors, many unit signal processors are installed in parallel to prohibit the output of the unit signal processor that has failed, and to capture other spare unit signal processors. Since the failure can be recovered by changing only the definition of the screen and the processing screen, it can be used as a highly reliable signal processor.

(Effect of the Invention) As has been seen above, according to the present invention, each unit signal processor has only a part of the memory for several lines at most,
Digital signal processing can be realized. Therefore, real-time digital signal processing can be applied to a moving image signal by using many unit signal processors. In addition, the unit signal processors placed in parallel differ only in the designation of the capture screen and the processing screen, and the processing units of each unit signal processor should be processed by the same digital signal processing program, so program development is also a single unit. Only the signal processor needs to be performed, and the program of the other unit signal processor may be a copy of the developed program, so that the program operation becomes easy.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a processing region of the present invention, and FIGS. 3 (a) to 3 (h) are diagrams showing operation timing in the configuration of FIG. FIG. 4 shows the control unit 14
5 is a diagram showing an example of the configuration of FIG. 5, and FIG. 5 is a diagram showing an example of the configuration of the processing unit 12. In the figure, 1 ... Vertical sync signal input terminal, 2 ... Horizontal sync signal input terminal, 3 ... Video input terminal, 4, 5, 6, 7 ... Internal output bus, 8 ... Vertical sync signal output terminal, 9 ...... Horizontal sync signal output terminal, 10 …… Video output terminal, 12 …… Processing section, 13 ……
Output unit, 14 ... Control unit.

 ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-58-181171 (JP, A) JP-A-56-117279 (JP, A) JP-A-59-53964 (JP, A) JP-A-59- 764 (JP, A) JP 58-217072 (JP, A) JP 60-153566 (JP, A)

Claims (1)

[Claims] 1. A predetermined input partial position signal and output partial position signal are generated from a vertical synchronizing signal indicating the beginning of one screen of a moving image signal such as a television signal and a horizontal synchronizing signal indicating the beginning of one scanning line. A control unit, a capture unit that receives an input partial position signal from the control unit, captures a partial screen signal designated by the input partial position signal of a separately input moving image signal, and is connected to the capture unit;
A processing unit that performs signal processing on the moving image signal captured by the capturing unit in an arbitrary access order until the capturing of the next partial screen starts, and an output order of the processing unit are connected, and the processing result of the processing unit is connected. A plurality of unit processors each of which stores the output of the stored processing result at a partial position designated by the output partial position signal separately input from the control unit; An input bus for supplying the vertical synchronizing signal, the horizontal synchronizing signal, and the moving image signal to each of the processors, and an output bus for transmitting the output partial signal output from each of the plurality of unit processors, one scanning line Alternatively, small areas in the partial screen of the one scanning line or the plurality of scanning line times are processed in an arbitrary access order within a plurality of scanning line times. Real-time video processor that.