JPH0831983B2 - Image reduction processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reduction processing device, and more particularly to an image reduction processing device used in a special effect device for displaying an image while performing image reduction processing.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a special effect image reduction processing apparatus of this type. The input image data is supplied to the band limiting filter 2, the frequency band is limited by the filter, and the image data is written and stored in the frame memory 1. The frame memory sequentially writes the input image data to the write address generated by the write address generation circuit 5 and stores the image data for one frame.

1 stored in the frame memory 1
The image data for the frame is read by the read address generation circuit 6
Is read according to the read address generated from. At the time of this data reading, the read address generating circuit 6 is 0, 1, 2, 3, ...
The read address is generated while incrementing each. When obtaining a 1/2 reduced image, the read address generation circuit 6 generates a read address while incrementing by 0, 2, 4, 6 ,.

In the case of this image reduction processing, if the read address is simply changed and read out as described above, aliasing noise appears in the output image. Therefore, the band limiting filter 2 is provided at the input stage of the frame memory. Is provided and the input image data is band-limited in advance to cut high frequency components.

A filter coefficient setting circuit 9 is provided in order to set the filter coefficient of the band limit 2, and the input image data of the input image data is generated in accordance with the filter coefficient generated by the filter coefficient generator 9 according to the reduction rate of the image. The frequency band is limited. In this way, when the original image is reduced and output, it is possible to prevent the aliasing noise from appearing in the output image by applying the band limiting filter according to the reduction rate, and it is possible to improve the image quality. ing.

[0006]

When performing image reduction by the image reduction processing apparatus shown in FIG. 5, the input image data is subjected to a band limiting filter according to a predetermined reduction rate, and then the image is written into the frame memory. Since data is written, when outputting a plurality of the same images having different reduction rates on the same screen, there is a drawback that a band limiting filter suitable for each reduction rate cannot be applied.

Further, since the band limiting filter is single,
There is also a problem that the filter cannot work effectively for all reduction ratios in a wide range and the aliasing noise appearing on the reduced image cannot be effectively removed.

An object of the present invention is to provide an image reduction processing apparatus capable of applying a band limiting filter suitable for each reduction rate even when a plurality of same images having different reduction rates are output on the same screen. That is.

Another object of the present invention is to provide an image reduction processing apparatus capable of applying an appropriate band limiting filter to all reduction rates over a wide range.

[0010]

An image reduction processing apparatus according to the present invention reduces the frequency band of input image data to 1/2 ⁱ (i
= 0, 1, 2, 3, 3, ..., N), and n frame memories that are provided corresponding to each of these filters and store the outputs of the corresponding filters,
A unit for generating a write address of the frame memory, a unit for generating a read address of the frame memory according to an image reduction ratio, and two units according to the reduction ratio.
It is characterized by including a selecting means for selecting the read image data of the frame memory and a linear interpolating means for deriving the read image data outputs of the two frame memories by linear interpolation processing according to the reduction ratio.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The input image data is input to each of the n (n is an integer of 2 or more) frame memories 1.1 to 1 · n. At this time, the image data is provided corresponding to each frame memory 1.1 to 1 · n. 1/2 ⁱ band-limited filter (i = 0, 1,
2, 3, ..., N) are supplied to the corresponding filters 1.1 to 1 · n via 2 · 0 to 2 · (n−1). In addition, 1 of i = 0
It should be noted that the / 2 ⁰ band limiting filter is equivalent to not actually passing the filter, so that the filter 2.0 is not specifically shown in FIG. 1.

Data writing to these frame memories 1.1 to 1.n is performed by a write address from the write address generating circuit 5, and data reading is performed by a read address from the read address generating circuit 6.
The write address generation circuit 5 has 0, 1, 2, 3, ... And +1.
As in the conventional example, the write addresses are generated in ascending order, and the read address generating circuit 6 generates the read addresses at a fixed number of intervals according to the reduction rate x.

The read data from these frame memories 1.1 to 1.n are input to the multiplexer 3, and two of n inputs are selected and output according to the select signal 10 from the select signal generating circuit 7. The two selected outputs are input to the linear interpolation circuit 4 and linear interpolation processing is performed on the two selected image data according to the interpolation coefficient k generated by the interpolation coefficient generation circuit 8.

The select signal generation circuit 7 is for generating the select signal 10 for the multiplexer 3 in accordance with the reduction rate x, a concrete example of which is shown in FIG. Figure 2
Referring to FIG. 3, n comparators 7.1 to 7 · n are provided, and whether or not the input reduction ratio x exists in the numerical range depends on these n comparators 7.1.
˜7 · n.

In the comparator 7.1, the value of x is 1/2 <x
When ≦ 1 (= 1/2 ⁰ ) is satisfied, the detection output is 10 · 1
Is set to “1” (active), and the comparators 7.2 are x
When the value of is less than 1/2 ² <x ≦ 1/2, the detection output 10.2 is set to “1”. In general, comparator 7j
(Where j = 1 to n−1), the value of x is 1/2 ^j <x ≦ 1.
When / 2 ^j-1 , the detection output 10 · j is set to "1". j
= N, the value of x in the comparator 7 · n is 0 <x ≦
When 1/2 ⁿ⁻¹ , the detection output 10 · n is set to “1”.

The multiplexer 3 detects these outputs 10.
Two read data of n frame memories are selected according to the active state of 1 to 10 · n. For example, if x = 1/5 (= 0.2), the comparator 7
Only the detection output 10.3 of 3 becomes "1", whereby the multiplexer 3 causes the frame memories 1.3 and 1 which store the image data whose band is limited to 1/4 and 1/8, respectively.
・ Select the read data with 4.

Generally, when the detection output 10.multidot.j of the jth comparator becomes active "1", 1/2 ^j-1.
The read data of the frame memories 1 · j and 1 · (j−1) in which the band-limited filter outputs are stored in 1 and 1/2 ^j , respectively, are selected by the multiplexer 3.

The interpolation coefficient generation circuit 8 calculates the interpolation coefficient k for the linear interpolation processing based on the reduction rate x and the select signal 10 (detection outputs 10.1 to 10.n by the comparators 7.1 to 7.n). It occurs, and a specific example thereof is shown in FIG. Referring to FIG. 3, the select signal 10
Numerical value generation circuit 80 which inputs (10-1-10n)
Are provided, and the n input signals 10.
When the j-th signal of n becomes active "1", the numerical value generating circuit 80 generates two numerical values A = 1/2 ^j and B = 2 ^j .

This circuit 80 has an input signal of 10-1 to 10-
RO that outputs two numerical values A and B with n as an address
However, the present invention is not limited to this.

The numerical value A is input to the subtracter 81 and subtracted from the reduction ratio x of the other input, and (x-A) is output.
The value of (x-A) is input to the multiplier 82 and multiplied by the numerical value B of the other input, and (x-A) * B is output. This calculation result (x−A) × B is output as the linear interpolation coefficient k.

The linear interpolation circuit 4 receives the interpolation coefficient k and performs linear interpolation processing on the two selection screen data.
This linear interpolation processing is executed by the well-known linear interpolation calculation shown in the following equation.

Linear interpolation output = M × (1−k) + N × k (1) In this equation (1), M is image data that has passed through the 1/2 ^j−1 band limiting filter, and N is 1. It is image data that has passed through a / 2 ^j band limiting filter.

An example will be described below. Reduction rate x
If There is 1/5 (= 0.2), the third comparator 7-3 detection output 10.3 (see FIG. 2) "1", the multiplexer 3 1/2 ² (= 1/4 ) And 1/2
³ (= 1/8), and the image data whose band is limited is selected.

In the interpolation coefficient generating circuit 8, two numerical values of A = 1/8 and B = 8 are generated from the numerical value generating circuit 80, and k = (1/5) by the subtracter 81 and the multiplier 82. −1/8) × 8 = 0.6 is calculated, and an interpolation coefficient of 0.6 is obtained.

Therefore, the linear interpolation output by the linear interpolation circuit 4 becomes the image data of (0.4M + 0.6N) according to the equation (1), and the output image data after passing through the band limiting filter suitable for the reduction ratio of 1/5. Therefore, the aliasing noise is eliminated. In order to actually obtain the reduced data of 1/5, the read address of the read address generation circuit 6 is incremented by +5 such as 0, 5, 10, 15 ,.

The same applies to other reduction ratios, all reduction ratios in a wide range can be dealt with, and an appropriate band limiting filter can be applied according to the reduction ratio.

When the same images 40 and 41 with different reduction ratios are displayed on the same screen as shown in FIG. 4, the read address generating circuit 6 outputs the read address in the area of the image 40 with the reduction ratio 1/2. , 0, 2, 4, ..., If the reduction ratio 1/2 is given to the select signal generation circuit 7 and the interpolation coefficient generation circuit 8 at that time, the filter corresponding to the value is applied.

Similarly, in the area of the image 41 with the reduction ratio of 1/5, the read address generation circuit 6 sets the read address to 0,
.., and the reduction ratio 1/5 is applied to the select signal generation circuit 7 and the interpolation coefficient generation circuit 8 at that time, the filter corresponding to the values is applied. The present invention can be applied not only to a special effect device for ordinary television broadcasting, but also to other television image processing such as high-definition broadcasting.

[0030]

As described above, according to the present invention, it is possible to apply a band limiting filter suitable for each reduction ratio to image data for all reduction ratios in a wide range, so that the quality of an output image is improved. Further, even when a plurality of the same images having different reduction ratios are displayed on the same screen, the filter corresponding to each reduction ratio can be applied, which also has the effect of improving the image quality.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of a select signal generation circuit in the block of FIG.

3 is a diagram showing a specific example of an interpolation coefficient generation circuit of the block of FIG.

FIG. 4 is a diagram showing an example in which the same image with different reduction rates is displayed on the same screen.

FIG. 5 is a block diagram of a conventional image reduction processing apparatus.

[Explanation of symbols]

 1.1-1.n Frame memory 2.1-2. (N-1) Band limiting filter 3 Multiplexer 4 Linear interpolation circuit 5 Write address generation circuit 6 Read address generation circuit 7 Select signal generation circuit 8 Interpolation coefficient generation circuit 7・ 1 to 7 ・ n Comparator 80 Numerical value generation circuit 81 Subtractor 82 Multiplier

Claims (3)

[Claims] 1. The frequency band of input image data is 1/2 ⁱ
N band limiting filters limiting to (i = 0, 1, 2, 3, ..., N), and n frame memories provided corresponding to each of these filters and storing the outputs of the corresponding filters, A unit for generating a write address of the frame memory, a unit for generating a read address of the frame memory according to an image reduction ratio, and two units according to the reduction ratio .
An image characterized by including a selection unit for selecting read image data of the frame memory and a linear interpolation unit for deriving the read image data outputs of the two frame memories by linear interpolation processing according to the reduction ratio. Reduction processing device. 2. The selecting means sets the reduction ratio x to 1/2.
<X ≦ 1,1 / 2 ² <x ≦ 1/2, 1/2 ³ <x ≦ 1 /
2 ² , ..., 0 <x ≦ 1/2 ⁿ⁻¹ , and 1st to nth detection means for detecting that they are in the respective ranges, and jth (j is 1 to 1).
When the detection output of the n integer) of the detecting means is in the active state, frame corresponding to the two filters to restrict the 1/2 ^j frequency band and 1/2 ^j-1 of the filter
The image reduction processing apparatus according to claim 1, further comprising means for selecting image data to be read out from the memory. 3. The linear interpolation means generates a linear interpolation coefficient k according to a detection output of the detection means, and the two frames selected according to the linear interpolation coefficient k.
3. The image reduction processing apparatus according to claim 2, further comprising means for performing linear interpolation calculation processing on the read image data output of the memory.