JPH0650525B2 - Mask processing method - Google Patents

Description

The present invention relates to a mask processing method, and more particularly to a mask processing method for performing thinning, thickening, edge extraction, filtering, etc. on an input image.

(Prior Art) Generally, when a mask of (2K + 1) × (2L + 1) is performed, y = q−L to q + L, x = of an input image as shown in FIG.
Each time the part of p−K to p + K is read, the product sum with the mask coefficient is performed to obtain one pixel (p, q) of the output image.

(Problems to be Solved by the Invention) Conventionally, in this type of mask processing method, in the case of performing (2K + 1) × (2L + 1) mask processing on an image of −M × N, it is necessary to read with an input image mask coefficient. Each MN (2K + 1)
Memory access is required x (2L + 1) times and MN times for writing the output image. Generally, the memory inside the processor is fast, but the capacity is small and the memory that stores images is large but not so fast, so it took a long time to process because the number of accesses to the memory containing images is large. .

An object of the present invention is to provide a mask processing method capable of reducing the number of times of accessing such a medium speed memory and processing at high speed.

(Means for Solving Problems) The mask processing method of the present invention is a means for storing an M × N input image, a M work area, and a (2K + 1) × (2L + 1) mask, and writing to the output image. Means for generating y = 1 to N as the indent (x, y) address and x = 1 to M for each y, and the output address generating means as the read (x, y) address from the input image = Q, x
= 1 to M each time y = q−L to q + L is generated,
Means for generating x = 1 to M for each y, and j = y−q, i = −K to each time the input address generating means generates one address as a mask read (i, j) address.
The means for generating K and the input address generating means for writing to the work area and the read (k) address are 1
Means for generating k = x−K to x + K each time an address is generated, and each of the input address generation means and the mask address generation means read out each time the work area address generation means generates one address. There is provided means for multiplying by a value, adding to the value of the work area value read by the work area address generating means, and writing back to the same work area again.

(Example) Next, the Example of this invention is described with reference to drawings.

FIG. 1 shows an embodiment of the present invention. Referring to FIG. 1, this embodiment uses a means 10 for storing an input image, an output image, a work area and a mask, a means 11 for generating a write address to the output image, and a read address from the input image for generating an output address. The means 11 for generating the output address by the means 11 and the mask means 13 for generating the mask read address each time the input address generating means generate one address, and the write / read address for the work area are input. Each time the work area means 14 for generating an address and the input address generation means 12 generate one address, the value read by the input address is multiplied by the value read by the mask address, and the work area value is summed. FIG. 2 includes a means 15 for writing back data to the same work area again. Indicates the means of payment. In FIG. 2, the storage means 10 of the present embodiment assumes the size of each memory as follows. First, the process for outputting the q-th line of the output image will be described. The value Axy is sequentially read from the input image by generating addresses y = q-L to q + L and x = 1 to M for each y. When one pixel Axy is read, an address of i = -K to K is generated for a line corresponding to the y-th line of the mask, that is, the number of lines of the portion read from the input image, and Mij (j = y-q) is generated. Read out and multiply this by Axy. This value is added to the k = xi-th value in the work area and updated. That is, the processing represented by the following equation is performed.

B'xi = Axy × Mi, y-q + Bx-i (i = -K to K) B'xi; updated value of the xi-th work area Bx-i; 〃 previous value Axy; from the input image The read address (x, y) value Mi, yq; the mask address (i, yq) value This state is shown in FIG. That is, when one pixel Axy is read from the input image, the mask coefficient is generated in the direction of the arrow, the address is generated and multiplied by Axy, the work area is generated in the direction of the arrow, and the product of this value and the above is summed. Write back again.

This is repeated for Axy obtained by reading y = q−L to q + L, x = _{1 to M} of the input image, and the work areas B _{1 to} B _M are output to the qth line of the output image. The results are cumulative. Finally, the work area is divided by the sum of the mask coefficients and copied to the output image q-th line.

By performing this processing for all output image lines y = 1 to N, (2K + 1) × (2L + 1) of M × N images
Can be masked.

FIG. 4 shows a work area which is changed by each processing in this embodiment. In FIG. 4, when the 8 × 8 input image is subjected to the 3 × 3 mask processing, every time one pixel input image is read, three pixels in the work area are accessed and the product of the mask coefficient is written. As a result, all input images are masked. Next, as a device for specifically realizing the present embodiment, as shown in FIG. 5, an image memory 51, output bus interfaces 54 and 55, and an image memory bus interface 52 are constituted by a ring-shaped processing section. In this apparatus, the input image and the output image are stored in the image memory 51, the work area and the mask are stored in the memory inside the output bus interface, and the processing is speeded up. That is, the image memory 51
Access is 3x8x8 inputs and 8x8 outputs,
The total is 256 times. On the other hand, in the conventional method, 3 × 3 × 8 ×
A total of 640 times with 8 inputs and 8 × 8 outputs.

(Effects of the Invention) As described above, the present invention applies (2K
+1) × (2L + 1) mask processing Generally, the number of accesses to the medium speed memory is MN (2K + 1) (2L + 1) + M
There were N times, but MN (2L + 1) + MN times were less, and the effect became even greater as the mask size increased. In addition, the access to the high-speed memory inside the processor is conventionally 3MN by reading / writing the work area and reading the mask.
(2K + 1) (2L + 1) In the present invention, 3MN (2K + 1) (2L
Same as +1).

Therefore, according to the present invention, the processing can be performed at high speed by reducing the number of times of accessing the medium speed memory including the image.

[Brief description of drawings]

FIG. 1 is a claim correspondence diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing a storage means in the present embodiment, FIG. 3 is a diagram showing a read address of a mask coefficient and a read / write address of a work area in a mask processing system in an embodiment of the present invention, and FIG. FIG. 5 is a diagram showing a processing state of a work area in the embodiment, FIG. 5 is a diagram showing an apparatus for realizing the present invention, and FIG. 6 is a diagram showing a conventional mask processing system. 10 ... Storing means, 11 ... Output image address generating means, 12 ... Input image address generating means, 13 ... Mask reading address generating means, 14 ... Work area address generating means, 15 ... Work area writing back means .

Claims (1)

[Claims] 1. An M × N input image, an M × N output image and M
Means for storing the work area and the (2K + 1) × (2L + 1) mask, and writing (x, y) into the output image
Y = 1 to N are generated as addresses, and x = 1 for each y
~ M, and y = q each time the image output address generating means generates y = q, x = 1 to M as a read (x, y) address from the input image. Generate −L to q + L, x = 1 for each y
~ M input image address generating means and j = y-q, i = every time the input image address generating means generates one address as a mask read (i, j) address.
Mask read address generation means for generating -K to K,
Work area address generating means for generating k = x−K to x + K each time the input image address generating means generates one address as a write (k) address for writing to a work area, and the work area address generating means. Each time one address is generated, the value is multiplied by each value read by the input image address generating means and the mask read address generating means, and added to the value of the work area value read by the work area address generating means. And a means for writing back again to the same work area.
= Q−L to q + L, x = 1 to M,
A mask processing method characterized by obtaining a portion of y = q, x = 1 to M of an output image subjected to a mask processing of (2K + 1) × (2L + 1).