JPH0834289B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI semiconductor device, and more particularly to a capacitor that requires a specific accuracy.

[Conventional technology]

Semiconductor devices that require specific capacitance accuracy include integrators and switched capacitor circuits. Here, a switched capacitor filter will be described as an example.

FIG. 3 shows a circuit diagram of a first-order switched capacitor low-pass filter. In the figure, IN is an input terminal, OUT is an output terminal, Amp is an operational amplifier, C ₁ and C ₂ are capacitors, and SW is a switch. Here, C ₁ = 0.5PF and C ₂ = 5PF. FIG. 4 shows a mask pattern design example of a semiconductor device obtained by patterning the circuit diagram shown in FIG. 3 of the related art. An operational amplifier Amp is formed in a semiconductor integrated circuit configuration on a semiconductor substrate, a lower electrode is provided on the entire surface of each of the capacitors C ₁ and C ₂ , and a unit upper electrode having a reference width is provided on the lower electrode. plurality, the upper electrode and interconnect to form a capacitor C ₂ in the wiring l, C _1, constituting the switched capacitor filter with the switch SW and an operational amplifier Amp.

The transfer function of the low-pass filter in Fig. 3 is The characteristics are determined by the ratio C ₁ / C ₂ of the capacitances C ₁ and C ₂ . As described above, when a semiconductor device in which the relative accuracy is a problem, not the absolute value of the capacitance, is integrated into an LSI, a mask pattern is designed by connecting unit capacitances in parallel as shown in FIG. According to this method, there is an advantage that the error of the planar processing accuracy does not become the capacitance ratio error.

Another factor of the capacitance ratio error is the parasitic capacitance generated at the intersection of the upper electrode wiring 1 and the lower electrode of each of the capacitors C ₁ and C ₂ . In order to explain the parasitic capacitance, the portion of the capacitance C ₁ in FIG. 4 is shown in FIG. Parasitic capacitance is generated at the intersection of the wiring 1 of the upper electrode and the lower electrode (the black portion in FIG. 5) connected to the contact portion a of the capacitance C ₁ . Wiring l
The width l _1, and the length of the intersection of the line l and the lower electrode and l _2, if the unit capacity and ^{0.4 × 10 -4 PF / μ 2} l 1 = l 2 =
At 2.5μ, the capacitance value is 0.4 × 10 ⁻⁴ × 2.5 ² = 0.00025PF.

The switched capacitor filter shown in FIG.
When patterned as shown, with respect to the capacitance C _1, the intersection of the wiring and the lower electrode of the upper electrode is one place l ₁ × l ₂ is, in sensitized to the capacitor C _2, l ₁ × l ₂ There are 14 parasitic capacitances. Therefore, the parasitic capacitance of the capacitance C ₁ is 0.00025PF, the parasitic capacitance of the capacitance C ₂ is 0.00025 × 14 = 0.0035PF, and the capacitance value is C ₁ ′ = 0.500.
25PF, C ₂ ′ ＝ 5.0035PF. Desired capacity ratio C ₁ / C ₂ = 0.1
Is C ₁ ′ / C ₂ ′ = 0.09998, which is a gain error of 1.74 × 10 ⁻³ dB.

[Problems to be Solved by the Invention]

Although the above-mentioned conventional semiconductor device is required to have high capacitance ratio accuracy, it is not possible to obtain the characteristics as designed by the circuit due to the influence of the parasitic capacitance generated at the intersection of the upper electrode wiring and the lower electrode of the capacitance. There is a drawback that.

[Means for solving the problem]

A semiconductor device according to the present invention is a semiconductor device in which n unit capacitors of a plurality of unit capacitors provided on a semiconductor substrate are interconnected to form a capacitor. At least two or more electrodes are arranged at equal intervals in both directions, and a lower electrode integrally formed on the entire surface is provided below all of the plurality of unit capacitors, and the upper electrodes are independently provided for each unit capacitor. The interconnection is performed by n linear wirings having a constant width for wiring the upper electrode. As another mode, in a semiconductor device having first and second capacitances having a capacitance ratio of 1: n, the area of the intersection of the lead wiring of the upper electrode and the lower electrode of the first capacitance, The area ratio of the intersection of the upper electrode lead-out wiring and the lower electrode of the second capacitor is set to 1: n.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the semiconductor device of the present invention. First
All symbols in the figure are the same as in FIG. An operational amplifier Amp is formed on a semiconductor substrate in the form of a semiconductor integrated circuit. On the other part of the semiconductor substrate, lower electrodes of the capacitance parts C ₁ and C ₂ are formed via an insulating film. A plurality of upper electrodes each having a unit area are formed on the lower electrode via a dielectric film. The upper electrode of the capacitor C ₂ is interconnected by a wiring l, and the area of the intersection of the upper electrode wiring and the lower electrode of the capacitor C ₂ is defined as the ratio of the respective capacitance values (10: 1 in this case). Is proportional to. That is, at the intersection of the wiring l of the upper electrode of the capacitor C ₁ and the lower electrode, there is one intersection of the area of l ₁ × l ₂ , and there are 10 intersections of the capacitor C ₂ . Therefore, the capacitance value is C ₁ ′ ＝
0.50025PF, C ₂ ′ ＝ 5.0025PF, capacity ratio C ₁ : C ₂ = 1: 10
Has been realized.

FIG. 2 shows a semiconductor device according to another embodiment of the present invention.
2 is also a pattern of the circuit diagram shown in FIG. 3, but the semiconductor device of this embodiment does not use parallel connection of unit capacitors unlike the semiconductor device of FIG. This is a case where a capacity smaller than the unit capacity is realized, or a case where a fraction which cannot be represented by the unit capacity is realized.

In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals. Further, a is a contact, W ₁ is the wiring width of the upper electrode of the capacitance C ₁ , and W ₂ is the wiring width of the upper electrode of the capacitance C ₂ .

For example, when C ₁ = 0.1PF, C ₂ = 0.4PF, parasitic capacitance C ₁ ′,
To make the ratio of C ₂ ′ C ₁ ′: C ₂ ′ ＝ C ₁ : C ₂ = 1: 4, W ₁ : W ₂
When it is set to 1: 4, a semiconductor device having a high capacitance ratio accuracy can be obtained without being affected by the parasitic capacitance.

Here, the example of the switched capacitor filter has been described, but the same applies to other semiconductor devices such as a sample hold circuit and an integrator that require capacitance ratio accuracy.

〔The invention's effect〕

As described above, the present invention eliminates the capacitance ratio error due to the parasitic capacitance by making the parasitic capacitance generated at the intersection of the upper electrode wiring and the lower electrode of the capacitance forming the semiconductor device proportional to each capacitance value. There is an effect that a semiconductor device having a high capacity ratio precision can be realized.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device of the present invention,
FIG. 2 is a plan view showing another embodiment of the present invention, and FIG.
A circuit diagram of the next low-pass filter, and FIGS. 4 and 5 are plan views showing an example of a conventional semiconductor device. IN: input terminal, OUT: output terminal, Amp: operational amplifier, SW: switch composed of MOS transistors, C ₁ , C ₂ ... capacitance, a ... contact, l ... capacitance upper electrode Wiring.

Claims (2)

[Claims] 1. A semiconductor device in which n unit capacitors out of a plurality of unit capacitors provided on a semiconductor substrate are interconnected to form a capacitor, wherein the plurality of unit capacitors are arranged in both vertical and horizontal directions. At least two or more are arranged at equal intervals, a lower electrode integrally formed on the entire surface is provided below all of the plurality of unit capacitors, and the upper electrode is independently provided for each unit capacitor, The semiconductor device according to claim 1, wherein the interconnection is performed by n linear wirings having a constant width for wiring the upper electrode. 2. A semiconductor device having first and second capacitances having a capacitance ratio of 1: n, in which the area of the intersection of the lead-out wiring of the upper electrode and the lower electrode of the first capacitance and the second capacitance The semiconductor device having an area ratio of the intersection of the upper electrode take-out wiring and the lower electrode of 1: n is 1: n.