JPH083515B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH083515B2 JPH083515B2 JP63148759A JP14875988A JPH083515B2 JP H083515 B2 JPH083515 B2 JP H083515B2 JP 63148759 A JP63148759 A JP 63148759A JP 14875988 A JP14875988 A JP 14875988A JP H083515 B2 JPH083515 B2 JP H083515B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- inverter
- basic logic
- circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に関し、特に基本論理素子
（OR素子,AND素子，インバータ素子、NAND素子およびNO
R素子）の特性を調べるため、基本論理素子が複数段接
続されている回路を備えた半導体集積回路に関する。The present invention relates to a semiconductor integrated circuit, and more particularly to a basic logic element (OR element, AND element, inverter element, NAND element and NO element).
The present invention relates to a semiconductor integrated circuit including a circuit in which basic logic elements are connected in a plurality of stages in order to investigate the characteristics of R elements.
従来、この種の半導体集積回路は第３図に示すように
インバータ素子の出力に負荷のインバータと次段のイン
バータ素子の入力を接続した回路を１段として、４段接
続した回路で、パルスａが入力端子を介して初段のイン
バータ素子から次のインバータ素子に供給され最終段の
インバータ素子f1からパルスｂとして送出されるように
構成されている。いま仮に１つのパルスａを入力端子に
供給すると、最終段の出力端子にパルスｂが伝達される
ことによりインバータ素子の特性を評価していた。Conventionally, a semiconductor integrated circuit of this kind is a circuit in which four stages are connected with a circuit in which an output of an inverter device is connected to an input of a load inverter and an input of an inverter device in the next stage as shown in FIG. Is supplied from the first-stage inverter element to the next-stage inverter element via the input terminal, and is transmitted as the pulse b from the last-stage inverter element f 1 . Now, assuming that one pulse a is supplied to the input terminal, the pulse b is transmitted to the output terminal at the final stage to evaluate the characteristics of the inverter element.
〔発明が解決しようとする課題〕 上述した従来の半導体集積回路は、基本論理素子の出
力に負荷ゲートと次段の基本論理素子の入力が接続した
回路を１段として多段に構成した回路であって、負荷ゲ
ートの出力がオープンとなっているので、負荷ゲートの
動作の検出ができず、また、負荷ゲートの入力がオープ
ン状態になった場合、電源とGND間に貫通電流が流れる
が、貫通電流が流れている箇所が基本論理素子の出力に
接続される負荷ゲートによるものか、また他の素子の不
良によるものかを判別するのが困難であるという欠点が
ある。[Problems to be Solved by the Invention] The above-described conventional semiconductor integrated circuit is a multi-stage circuit in which a circuit in which a load gate and an input of a basic logic element in the next stage are connected to the output of the basic logic element is multistage. Since the output of the load gate is open, the operation of the load gate cannot be detected.When the input of the load gate is open, a through current flows between the power supply and GND. There is a drawback in that it is difficult to determine whether the location where the current is flowing is due to the load gate connected to the output of the basic logic element or due to a defect in another element.
上述した従来の半導体集積回路に対し、本発明は基本
論理素子の出力に接続される負荷ゲートの出力の動作を
確認するための回路を付けるという相違点を有する。The present invention is different from the above-described conventional semiconductor integrated circuit in that a circuit for confirming the operation of the output of the load gate connected to the output of the basic logic element is added.
本発明の半導体集積回路は、OR素子、AND素子、イン
バータ素子、NAND素子およびNOR素子の少なくとも一つ
の基本論理素子の特性を調べるため、前記基本論理素子
の同じ素子が複数段直列に接続された回路を備えた半導
体集積回路において、前記基本論理素子の各々の出力に
OR素子、AND素子、インバータ素子もしくはNOR素子の負
荷ゲートを接続した回路と、前記複数段の基本論理素子
に接続された負荷ゲートの出力をそれぞれAND素子とOR
素子に接続し、このAND素子とOR素子の出力をEX−OR素
子に接続し、前記EX−OR素子の出力を“L"または“H"に
よって、複数段の負荷ゲートの動作が正常か否かを検出
する回路とを有する。In the semiconductor integrated circuit of the present invention, in order to examine the characteristics of at least one basic logic element of an OR element, an AND element, an inverter element, a NAND element and a NOR element, the same element of the basic logic element is connected in multiple stages in series. In a semiconductor integrated circuit having a circuit, the output of each of the basic logic elements
The output of the load gate connected to the circuit connected to the load gate of the OR element, the AND element, the inverter element, or the NOR element and the output gate of the plurality of stages of the basic logic elements and the OR
Connect the output of the AND element and the OR element to the EX-OR element, and set the output of the EX-OR element to "L" or "H" to determine whether the operation of the load gate in multiple stages is normal. And a circuit for detecting whether or not.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す回路図である。 FIG. 1 is a circuit diagram showing one embodiment of the present invention.
第１図において、本実施例は入力端子１、出力端子2,
3を有しており、入力端子１と２の間に特性評価用の基
本論理素子（インバータ素子）11,21,31,41が設けら
れ、更に各段の基本論理素子に対する負荷のインバータ
素子12,22,32,42が設けられている。インバータ素子51,
52は奇数段の負荷のインバータ素子12,32の出力に接続
されている。AND素子53はインバータ素子51,52の出力と
偶数段の負荷のインバータ素子22,42の出力とに接続さ
れた素子であり、OR素子54はインバータ素子51,52の出
力と偶数段の負荷のインバータ素子22,42の出力とを入
力するOR素子であり、更にEX−OR素子55はAND素子53の
出力とOR素子54の出力に接続するEX−OR素子である。In FIG. 1, the present embodiment has an input terminal 1, an output terminal 2,
3 is provided, and basic logic elements (inverter elements) 11, 21, 31, 41 for characteristic evaluation are provided between the input terminals 1 and 2, and an inverter element 12 of a load for the basic logic element of each stage is further provided. , 22, 32, 42 are provided. Inverter element 51,
52 is connected to the outputs of the inverter elements 12 and 32 of the odd-numbered load. The AND element 53 is an element connected to the outputs of the inverter elements 51 and 52 and the outputs of the inverter elements 22 and 42 of the even-stage loads, and the OR element 54 is the element of the outputs of the inverter elements 51 and 52 and the even-stage loads. It is an OR element that inputs the outputs of the inverter elements 22 and 42, and the EX-OR element 55 is an EX-OR element that is connected to the output of the AND element 53 and the output of the OR element 54.
次に、本実施例の動作について説明する。 Next, the operation of this embodiment will be described.
今、入力端子１に１つのパルスを入力すると出力端子
２に１つのパルスが出力し、出力端子３は“L"レベルが
出力される。次に、負荷ゲートの１つの入力がオープン
となって、負荷ゲートの入力がフローティングレベルに
なると、負荷ゲートの出力が不安定となり、出力端子３
は、“H"レベルを出力し負荷ゲートの出力動作をおかし
いことを検出することができる。Now, when one pulse is input to the input terminal 1, one pulse is output to the output terminal 2, and the output terminal 3 outputs "L" level. Next, when one input of the load gate becomes open and the input of the load gate becomes a floating level, the output of the load gate becomes unstable and the output terminal 3
Can output "H" level and detect that the output operation of the load gate is abnormal.
第２図は本発明の他の実施例を示す。第２図におい
て、この他の実施例は、第１図の基本論理素子を２入力
NOR素子や２入力NAND素子に入れかえて、段数を合せて
並列にならべた回路に奇数段の負荷ゲート（インバータ
素子）の出力には各段ごとにNAND素子304,306に接続
し、偶数段の負荷ゲートの出力には各段ごとにOR素子30
5,307に接続し、NAND素子304,306,OR素子305,307に出力
をそれぞれAND素子308とOR素子309に接続し、AND素子30
8とOR素子309の出力をEX−OR素子310に接続し、OR素子1
05の出力端子につなぐ。入力端子101はデータ入力で、
出力端子103はNOR素子の特性の波形の出力で、出力端子
104はNAND素子の特性の波形の出力である。コントロー
ル信号102の“H"と“L"によって、NOR素子とNAND素子の
特性の波形の出力を出力端子103と104に出力し、出力端
子105の出力が“L"のときは、負荷ゲートの出力動作は
正常で、“H"のときは負荷ゲートの出力動作がおかしい
ことが検出できる。FIG. 2 shows another embodiment of the present invention. Referring to FIG. 2, another embodiment of the present invention has two inputs of the basic logic element of FIG.
Replace with NOR element or 2-input NAND element, and arrange the number of stages in parallel, and connect the output of odd-numbered load gates (inverter elements) to NAND elements 304 and 306 for each stage to load even-numbered stages. The output of is OR element 30 for each stage
5, and connected to the NAND elements 304 and 306, and the outputs to the OR elements 305 and 307 to the AND element 308 and the OR element 309, respectively.
8 and the output of OR element 309 are connected to EX-OR element 310, and OR element 1
Connect to the output terminal of 05. Input terminal 101 is for data input,
Output terminal 103 is the output of the waveform of the characteristics of the NOR element.
Reference numeral 104 is an output of the waveform of the characteristic of the NAND element. The control signal 102 “H” and “L” outputs the waveform of the characteristic of the NOR element and the NAND element to the output terminals 103 and 104. When the output of the output terminal 105 is “L”, the load gate The output operation is normal, and when it is "H", it can be detected that the output operation of the load gate is abnormal.
なお、各段の基本論理素子に対する負荷ゲートをイン
バータ素子を用いて説明したが負荷ゲートとしてはイン
バータ素子の他のNAND素子、NOR素子、OR素子、AND素子
が含まれる。Although the load gate for the basic logic element of each stage is described using the inverter element, the load gate includes other NAND elements, NOR elements, OR elements, and AND elements of the inverter element.
以上説明したように本発明は、基本論理素子の出力に
負荷ゲートを接続した回路を１段として複数段つなげた
回路において、負荷ゲートの出力の動作が正常か否かを
検出する回路を付けることにより、負荷ゲートの入力の
１つがオープンであるなどの不良が論理チェックのみで
判別することができる効果がある。As described above, according to the present invention, in a circuit in which a circuit in which a load gate is connected to the output of a basic logic element is one stage and is connected in plural stages, a circuit for detecting whether or not the operation of the output of the load gate is normal is provided. Thus, there is an effect that a defect such as one of the inputs of the load gate being open can be identified only by the logic check.
第１図は本発明の一実施例を示す回路図、第２図は本発
明の他の実施例を示す回路図、第３図は従来の基本論理
素子の特性を調べる回路を示す図である。 1,101,102…入力端子、2,103,104,105…出力端子、11,2
1,31,41,c1,d1,e1,f1…基本論理素子（インバータ素
子）、111,121,131,141…基本論理素子（NOR素子）、21
1,221,231,241…基本論理素子（NAND素子）、12,22,32,
42,112,122,132,142,212,222,232,242,c2,d2,e2,f2…負
荷ゲート（インバータ素子）、51,52,303…インバータ
素子、53,308…AND素子、54,305,307,309…OR素子、30
1,302,304,306…NAND素子、55,310…EX−OR素子。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a diagram showing a circuit for examining characteristics of a conventional basic logic element. . 1,101,102 ... Input terminals, 2,103,104,105 ... Output terminals, 11,2
1,31,41, c1, d1, e1, f1 ... Basic logic element (inverter element), 111,121,131,141 ... Basic logic element (NOR element), 21
1,221,231,241 ... Basic logic element (NAND element), 12,22,32,
42,112,122,132,142,212,222,232,242, c2, d2, e2, f2 ... Load gate (inverter element), 51,52,303 ... Inverter element, 53,308 ... AND element, 54,305,307,309 ... OR element, 30
1,302,304,306 ... NAND element, 55,310 ... EX-OR element.
Claims (1)
素子およびNOR素子の少なくとも一つの基本論理素子の
特性を調べるため、前記基本論理素子の同じ素子が複数
段直列に接続された回路を備えた半導体集積回路におい
て、前記基本論理素子の各々の出力にOR素子、AND素
子、インバータ素子もしくはNOR素子の負荷ゲートを接
続した回路と、前記複数段の基本論理素子に接続された
負荷ゲートの出力をそれぞれAND素子とOR素子に接続
し、このAND素子とOR素子の出力をEX−OR素子に接続
し、前記EX−OR素子の出力を“L"または“H"によって、
複数段の負荷ゲートの動作が正常か否かを検出する回路
とを有することを特徴とする半導体集積回路。1. An OR element, an AND element, an inverter element, a NAND
In order to investigate the characteristics of at least one basic logic element of the element and the NOR element, in the semiconductor integrated circuit including a circuit in which the same element of the basic logic element is connected in multiple stages in series, the output of each of the basic logic element A circuit in which a load gate of an OR element, an AND element, an inverter element or a NOR element is connected, and outputs of load gates connected to the basic logic elements of the plurality of stages are respectively connected to an AND element and an OR element, and the AND element and The output of the OR element is connected to the EX-OR element, and the output of the EX-OR element is "L" or "H",
A semiconductor integrated circuit, comprising: a circuit that detects whether or not the operation of a plurality of stages of load gates is normal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63148759A JPH083515B2 (en) | 1988-06-15 | 1988-06-15 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63148759A JPH083515B2 (en) | 1988-06-15 | 1988-06-15 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH022963A JPH022963A (en) | 1990-01-08 |
| JPH083515B2 true JPH083515B2 (en) | 1996-01-17 |
Family
ID=15460005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63148759A Expired - Fee Related JPH083515B2 (en) | 1988-06-15 | 1988-06-15 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH083515B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0487308B1 (en) * | 1990-11-21 | 2000-01-26 | Canon Kabushiki Kaisha | Color image communication |
-
1988
- 1988-06-15 JP JP63148759A patent/JPH083515B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH022963A (en) | 1990-01-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |