JPH083797B2 - Microcomputer logic simulation method - Google Patents

Description

The present invention relates to a logic simulation method for a microcomputer.

[Conventional technology]

FIG. 3 is a conceptual diagram showing a conventional logic simulation method of a microcomputer. In the figure, 1 is a 1-chip microcomputer, 1a is a microcomputer input port, and 2 is a ROM address bus 1.
b, an external ROM connected to the one-chip microcomputer 1 via the ROM data bus 1c, which constitutes a logic simulation target circuit 10. Reference numeral 3 is a test program written in assembler language, 4 is a cross assembler for converting the test program 3 into an instruction code, and 5 is a conversion program for generating a logic simulation command for storing the instruction code in the external ROM 2.

Next, the operation will be described. The test program 3 is converted into an instruction code by the cross assembler 4. The conversion program 5 generates a logic simulation command for storing the instruction code in the external ROM 2.

When the microcomputer model of the 1-chip microcomputer 1 and the external ROM 2 is logically simulated, an instruction is input from the external ROM 2 and processed by the 1-chip microcomputer 1.

FIG. 4 shows a conceptual diagram of the operation of the port input instruction. In FIG. 4, when the reset signal 1g is input to the one-chip microcomputer 1, the program counter 1e operates to output the ROM address to the ROM address bus 1b and the instruction code 2a from the external ROM 2 to the data bus 1c. CPU1d, instruction code 2a
Is processed and the result is output to the output port 1h.

In case of the port input instruction, the CPU 1d generates the port control signal 1f _a , turns on the port input gate 1f _b ,
Read the data set in port 1a. Therefore, when the port input instruction is logically simulated, it is necessary to set the data in the input port 1a so as to match the output timing of the control signal generated by the CPU 1d.

The method shown in FIG. 3 is a logic simulation of a port input instruction, where the port input instruction is logically simulated once and the generation time of the control signal (1f _{a in} FIG. 4) output by the CPU 1d is observed, and then the simulation command is executed. Manually specify the data and time by
This is a method of sequentially simulating port input instructions in a test program by executing logic simulation.

[Problems to be solved by the invention]

Since the conventional microcomputer logic simulation method is configured as described above, the logic simulation is sequentially executed for each port input instruction, the port control signal output time is checked, and the port is manually input. -It is necessary to specify the data and time. In addition, it is necessary to execute the logic simulation repeatedly for all the port input instructions in the test program in order to know the specified time, which requires the logic simulation execution time and human labor, and the logic simulation period is long. There was a problem.

The present invention has been made to solve the above-mentioned problems. For a port input instruction in a test program, the CPU does not manually specify the time to set the data in the port, and the CPU does not operate at the time of logic simulation. It is an object of the present invention to obtain a logic simulation method capable of automatically setting sequential data to an input port when a logic simulation is executed by using an output port control signal.

[Means for solving problems]

A microcomputer logic simulation method according to the present invention converts a test program into instruction code data by a cross assembler, and converts the instruction code data into a first instruction code data.
Is converted into a command for logic simulation by the conversion program and stored in the first storage means connected to the one-chip microcomputer, and port input data in the test program is converted into a command for logic simulation by the second conversion program. The converted data is stored in the first storage means, and when there is a port input instruction, a port control signal is generated from the one-chip microcomputer, and the necessary data is generated based on the address signal from the counter to which this port control signal is input. Read from the second storage means,
It is designed to be set to the input port of the chip microcomputer.

The data for the port input command in this invention is
It is stored in the port ROM for logic simulation in advance, and every time the port input instruction in the test program is executed, the control circuit that receives the control signal from the CPU and counts it up is automatically and sequentially input to the input port. By setting the data, manpower is not required and the logic simulation period is shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In Fig. 1, 3a is a new type of test program,
It describes the port data given externally to the port input instruction. Reference numeral 4 is a cross assembler for generating the instruction code of the test program, and 5 is a first conversion program for generating a logic simulation command for storing the instruction code in the external ROM 2 as the first storage means. Reference numeral 6 is a second conversion program for reading the port data described in the new format test program and generating a logical simulation command for storing it in the port ROM 7 as the second storage means described later.

Reference numeral 1 is a 1-chip microcomputer, 2 is an external ROM for storing an instruction code, and these have the same configuration as in FIG. 7 and 8 are model circuits for logic simulation, and 7 is a port that stores data for port input instructions.
ROM and 8 are counter circuits for inputting control signals generated by the CPU 1d.

Next, the operation will be described. The new format test program 3a is input to the cross assembler 4 and converted into an instruction code, and then the first conversion program 5 converts the instruction code into a logical simulation first command for storing it in the external ROM 2. Also the above test program
3a is input to the second conversion program 6 and converts the port data described in the test program into a second command for logical simulation for storing in the port ROM.

Then, the logic simulator is activated to execute the first and second commands, store the instruction code in the external ROM, and store the port data in the port ROM. Then, by applying a reset signal, the external
The instructions in ROM2 are executed sequentially.

If the instruction is a port input instruction, CPU1 in microcomputer 1
d generates the port control signal 1f _a . The port control signal 1f _a is input to the external counter circuit 8 and outputs the port ROM address. Therefore, data is read from the port ROM 7 in synchronization with the signal 1f _a ,
Data is set to input port 1a.

Similarly, every time the port input instruction is executed, the counter circuit 8 counts up the port ROM address and sets the data in the input port 1a.

Fig. 2 is a block diagram showing the logic simulation method when the port of the port input instruction is an input / output (I / O) port. In Fig. 2, 1A is an I / O port and data input and Data output is performed by the port control signals 8a and 8b.

In this case, the external RAM 9 and the above signals 8a and 8b are used for proper R
A counter circuit 8A for calculating the AM address is added. The counter circuit 8A needs to prevent writing of data to an address for input data.

In FIGS. 1 and 2, in order to make the on / off timing of the port gate appropriate, the gate delay of the logic simulation model circuit is set to zero and a delay gate is provided around the port gate. You may add.

〔The invention's effect〕

As described above, according to the present invention, the port control signal output from the CPU is used to automatically set the data sequentially to the input ports when the logic simulation is executed. Thus, it is not necessary to repeatedly execute the logical simulation to know the time to set the data in the input port, and it is not necessary to manually specify the data and the time by the command. Therefore, the logic simulation execution time is short, human labor is not required, and there is an effect that the logic simulation period is shortened.

[Brief description of drawings]

1 is a block diagram showing a logic simulation method according to one embodiment of the present invention, FIG. 2 is a block diagram showing a logic simulation method according to another embodiment, and FIG. 3 is a block diagram showing a conventional logic simulation method. Fourth
The figure is a conceptual diagram showing the operation of a port input instruction. 1 is a 1 chip microcomputer, 1a is an input port, 2 is an external ROM
(First Storage Means) 5, 5 is a first conversion program, 6 is a second conversion program, 7 is a port ROM (second storage means), and 8 is a counter. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A logic simulation of a one-chip microcomputer comprising a logic simulation model circuit having a first storage means and a second storage means connected to a microcomputer body, and a test program for testing the microcomputer. As a second step, the test program is input to the cross assembler and converted into an instruction code, and then the first conversion program converts the instruction code into the first command for logic simulation for storing in the external ROM. The test program is input to the second conversion program to convert the port data described in the test program into a second command for logic simulation for storing in the port ROM, and as a third step, a logic simulator. To execute the first and second commands, and execute the external R After the instruction code is stored in OM and the port data is stored in the port ROM, the microcomputer of the logic simulation model circuit is reset, the instructions stored in the external ROM are sequentially read and executed, and the port input instruction is executed. Then, a port control signal is generated from the one-chip microcomputer, and necessary port data is read from the second storage means on the basis of an address signal from a counter that counts the port control signal, and the one chip is read. A logic simulation method for a microcomputer, characterized by setting the input port of the microcomputer.