JPH083848B2 - Image feature extraction processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a calculation device for performing image processing such as image smoothing and edge extraction by image filtering calculation, as well as automatic assembly of industrial products and products. The present invention relates to an image feature extraction device required for image recognition such as component positioning and defect detection in inspection.

(Prior Art) Conventionally, a convolution operation used as an image filtering operation is expressed by the following equation.

Here, f ₁ (i, j) is a signal value (hereinafter, referred to as a pixel value) at a pixel (i, j) of an image which is an input of calculation, f ₂
(I, j) is a pixel value of the output image, w (k, l) is a secondary data table called a mask function, and specifies a neighborhood area that is a range of calculation.

FIG. 5 is a diagram showing an example of an edge extraction mask function used in a conventional convolution operation.

For example, as w, size 3 as shown in FIG.
When the table of × 3 is used, an image obtained by extracting the edge of the input image f ₁ (i, j) is obtained as the output image f ₂ (i, j).

In such a convolution operation, a general-purpose image processing operation such as image smoothing and edge enhancement can be realized by changing the shape (value of w (k, l)) of the mask function.

(Reference: Makoto Nagao, "Digital Image Processing", Modern Science Co., Ltd., 1978, pp. 185-204) On the other hand, the variance value σ ² of the image is calculated by using the average value μ of the image. Can be represented by In general Represents the n-th statistic of the image.

Both the convolution operation and the image statistic operation such as the variance σ ² are basic image processing operations.
In a conventional image processing apparatus or image processing system, they are often used in combination in order to perform image analysis, classification, recognition extraction, recognition, and the like.

However, in one image processing device or an image processing system, if the two arithmetic functions are individually realized,
The scale of the arithmetic circuit device increases, resulting in a redundant device configuration.

Furthermore, as is clear from the definition formula, the two conventional operations are all pixel of the image {(i, j); i = 1,2, ... I, i = 1,2, ... J)}. On the other hand, it is a uniform operation for repeatedly performing the same operation. However, in image processing, especially in image feature extraction processing, by selectively performing convolution calculation or statistic calculation for points satisfying certain conditions in the image,
It becomes possible to calculate a more appropriate feature amount.

Since the conventional arithmetic unit performs uniform arithmetic, there is a drawback that such flexible and fine arithmetic cannot be realized.

(Object of the Invention) An object of the present invention is to unify the convolution calculation and the nth-order statistic calculation, which have been conventionally performed individually, and to effectively reduce the size of the calculation device. It is an object of the present invention to provide an image feature extraction calculation device that can perform various calculations that can realize the above, and that can realize various image feature extraction calculations that cannot be calculated only by two conventional calculations.

(Structure of the Invention) (Differences between Features of the Invention and Conventional Techniques) The present invention is characterized in that the image feature extraction operation is uniformly executed by the weighted product-sum operation represented by the following equation.

Ie However F (i, j, k, l) = {f 1 (i + k, j + l) -Cf 2 (i, j)} n
{When f ₃ (i + k, j + 1) = C ′} or = 0 {when f ₃ (i + k, j + 1) ≠ C ′} where S is a constant and w (k, l) is a conventional convolution operation Mask function (two-dimensional data table) that specifies the neighborhood area of the same operation as, f ₁ (i, j) and f ₂ (i, j)
Is an input image, f ₃ (i, j) is a control image for controlling the calculation, and f ₄ (i, j) is an output image showing the calculation result.

Further, n is a natural number 0, 1, 2, ..., C is a calculation parameter of 0 or 1, and C ′ is a control parameter which is an arbitrary constant value.

In this arithmetic unit, the input images f ₁ (i, j), f
₂ (i, j), control image f ₃ (i, j), operation parameters n, C and control parameter C ′ are selected to realize the conventional convolution operation and n-th order statistic operation in a unified manner. You can

For example, if all the values of f ₃ (i, j) are 1, n = 1 and C =
If 0, C '= 1, and S = 1, this operation is a conventional convolution operation.

Also, f ₃ (i, j) ≡1, n = 1, C = 0, C ′ = 1, w (k, l) ≡
When 1, S = (2K + 1) (2L + 1), the operation output f ₄ (i,
j) gives the average value μ (i, j) within the range (area S) of the mask function for the input image f ₁ (i, j).

Therefore, next, the average value μ (i, i calculated by the above method is
j) as an input image f ₂ (i, j), f ₃ (i, j) ≡1, n = 2, C = 1, C ′ = 1, w (k, l) ≡1, S = (2K + 1 ) (2L + 1), this calculation method can calculate the variance value σ ² (i, j) of the input image f ₁ (i, j).

Generally, if n = 2, 3, 4, ..., Higher-order statistics of an image for each order can be calculated.

Another feature of the present invention different from the conventional convolution calculation and n-th order statistic calculation is that the control image f ₃ (i,
The calculation can be controlled by the value of j).

That is, in the above arithmetic expression, f ₃ (i + k, j +
l) = C ′, F (i, j, k, l) can be made to contribute to the output image f ₄ (i, j) only in the image (i + k, j + 1), so that the control image f ₃ (i, If an image having a value C ′ only in the image to be calculated as j) and a value not C ′ in other pixels is used, the input image f ₁ (i, j), f ₂ (i, j) is identified. The calculation can be executed by selecting only the image of.

(Embodiment) FIG. 1 is a calculation block diagram for executing an image feature extraction calculation in the present invention.

This is a block configuration diagram for realizing an arithmetic processing unit 33 described later.

Bus selectors 1, 2 and 3 respectively select an image memory to be an input by switching three video buses.

Reference numeral 4 denotes a selector which outputs the input image (f ₂ ) selected by the bus secreter 1 in the case of C = 1 according to the value of the operation parameter C in the above-mentioned arithmetic expression, and in the case of C = 0,
It outputs "0" and stores the result in the register 5. Reference numeral 6 denotes a subtractor, which performs subtraction with the input image (f ₁ ) selected by the bus selector 2 and stores the result in the register 7.

According to the value of the operation parameter n designated by the terminal 21, the selector 13 selects “1” from the terminal 8 when n = 0 and the value of the register 7 when n = 1. n =
When the value is 2, a value obtained by squaring the value of the register 7 is obtained by the square table 9, and the value is selected by the selector 13.

Similarly, if n = 3 and n = 4, the cube and 4
Multiplied values are obtained from the tables 10 and 11 and selected by the selector. Here, the selector 13 determines the image value (f ₃ ) of the input image selected by the bus selector 3 and the constant register 19
If the results are not equal, the value "0" input from the terminal 12 is preferentially selected.

The selector 13 is the output value _{F = {f 1 (i +} k, j + l) -Cf 2 (i, j)} by the above operation ⁿ {f ₃ (i
+ K, j + l) = C ' when} or _{= 0 {f 3 (i +} k, j + l) ≠ C' to compute the} when.

14 is a multiplier, 40 is a mask function table, and w (k,
l) · F is calculated, and the result is adjusted by the shifter 15 to adjust the significant digit of the operation and output to the register 16. The adder 17 and the register 18 calculate the cumulative operation ΣΣw (k, l) · F. The adder 22 and the register 23 accumulate the numbers when the output value of the comparator 20 is 1 (when the determination is coincident).

The selector 25 selects the register 23 or the register 24 in which a constant is written in advance, writes the result in the register 26, and sets it as the value of S.

27 is a divider, which calculates 1 / S.ΣΣ
Calculate w (k, l) · F and write the result in register 28.

The calculation result calculated by the above configuration is output to the output terminal 29.
Is output to the image memory via the system bus or the video bus.

Since the arithmetic processing unit 33 shown in this embodiment is configured to select an input image for arithmetic operation from N image memories and write the arithmetic result again to the designated image memory,
The output image obtained by one operation can be used again as the input image for the next operation. Therefore, it is possible to repeat the calculation sequentially while selecting and changing the parameters in the calculation formula as necessary, and it is possible to execute more complicated image processing calculation and feature extraction calculation by combining the calculations.

FIG. 2 is a block diagram for implementing the present invention.

Reference numeral 30 is an image pickup device such as a television camera or a scanner for inputting an image, 31 is an analog / digital conversion of the input image, and the result is the image memory 1 to the image memory N of the image memory 32.
Is an A / D conversion unit that outputs to either of the above.

In the present invention, at least three image memories are required, and each image memory is connected to at least three video buses and a system bus mainly used for controlling operation.

Reference numeral 33 denotes an arithmetic processing unit for executing an image processing arithmetic operation, which specifies any three of N image memories,
Calculations such as convolution calculation are performed, and the result is written again in the image memory.

34 is a control unit for controlling the whole operation, 35 is a threshold processing unit for binarizing the contents of the image memory by using a threshold, and 36 is a unit for sending the calculation result to another computer, a display device, etc. The communication control unit 37 is an output terminal.

In the present invention, since at least two image memories are used as input and one is used as output, at least three video buses are prepared, and the arithmetic processing unit can access the three image memories at the same time. There is. However, the configuration may be such that only one video bus is provided and the input and output image memories are alternately accessed and used.

FIG. 3 and FIG. 4 are explanatory views of the calculation using the control image memory in the present invention.

For example, as shown in FIG. 3, if a grayscale image is written as an input image in the image memory 1 and an edge direction obtained from the input image is written in the image memory 3,
The arithmetic processing unit 33 uses the image memory 1 and the image memory 3 as the input image f ₁ and the control image f ₃ , respectively, and performs a convolution operation of pixels on the input image corresponding to an edge in a specific direction and statistics such as an average value. The amount can be calculated.

In addition, as shown in FIG.
The number of pixels in the image memory 3 whose edge strength is greater than or equal to the threshold is 1,
By writing the edge strength with other values set to 0, it is possible to calculate a statistic such as an average value in the edge direction for pixels whose edge strength is equal to or greater than a threshold value.

Furthermore, if the average value in the edge direction is written in the image memory 2 and the remaining state is unchanged, then a higher-order statistic such as variance can be calculated.

(Effects of the Invention) As described above, according to the present invention, the conventional convolution calculation, n, is performed on the image input by the image pickup apparatus.
Sub-statistical calculation, various image processing using the control image memory, and feature extraction calculation can be performed in a unified manner by one calculation processing unit. Therefore, an arithmetic circuit in configuring the image processing device and the image feature extraction device. It has a great effect on downsizing and simplification.

Also, depending on the specification of calculation parameters and the type of image data to be input, many processes that cannot be executed by conventional convolution calculation and nth-order statistic calculation can be executed, and image processing and feature extraction calculation with excellent versatility can be performed. There is an advantage that it can be realized.

[Brief description of drawings]

FIG. 1 is a calculation block diagram for executing an image feature extraction calculation according to the present invention, FIG. 2 is a block diagram of a device configuration for implementing the present invention, and FIGS. 3 and 4 are controls in the present invention. FIG. 5 is an explanatory diagram of a calculation using an image memory, and FIG. 5 is an example of an edge extraction mask function used in a conventional convolution calculation. 1,2,3 …… Bus selector, 4,13,25 …… Selector, 5,7,1
6,18,23,26,28 ... Register, 6 ... Subtractor, 8,12,21 ...
… Numerical value input terminal, 6 …… Square table, 10 …… Curve table, 11 …… Quadrature table, 14 …… Multiplier, 15 …… Shifter, 17,22 …… Adder, 19,24 …… Constant register, 20 ……
Comparator, 27 ... Divider, 29 ... Output end, 30 ... Imaging device, 31 ... A / D conversion unit, 32 ... Image memory, 33 ... Arithmetic processing unit, 34 ... Control unit, 35 ... Threshold processing unit, 36 ... Communication control unit, 37 ... Output end, 40 ... Mask function table.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-55474 (JP, A) JP-A-61-237132 (JP, A) JP-A-61-138335 (JP, A) Actual development Sho-60- 44147 (JP, U) Actually open 61-37554 (JP, U)

Claims (1)

[Claims] _1. An image memory A for storing an input image f ₁ , an image memory B for storing an input image f ₂ , an image memory D for storing a control image f ₃ for controlling calculation, and a calculation result f ₄ . An image feature extraction arithmetic unit comprising an image memory for accumulating and an arithmetic processing unit, wherein the arithmetic result f calculated by the arithmetic processing unit.
₄ is wired so that it can be used as the input image f ₂ , and the arithmetic processing unit causes the input image f ₁ and the input image f _{2 to be}
And the control image f ₃ are input, and when C is a parameter and n is a power value as the first calculation, F = {f ₁ (i + k, j + 1) -Cf ₂ (i, j)} ⁿ (however, when f ₃ (i + k, j + 1) = C ′) F = 0 (however when f ₃ (i + k, j + l) ≠ C ′) is calculated, and the second calculation is S with W as a parameter. If is a mask function, perform cumulative calculation and The image feature extraction arithmetic unit is configured to rewrite any one or all of the values n, C, C ′, and W in the arithmetic processing unit.