JPH084134B2 - Device simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A device simulator for analyzing each parameter of a semiconductor device by solving simultaneous equations indicating the operation of the semiconductor device by an indirect method. What is the shape of the semiconductor device? Even if there is, for the purpose of high-speed analysis, each information of the semiconductor device to be analyzed is input by the input device, and based on that, the analysis condition setting section and the simulation initial setting section respectively set the analysis condition setting and the simulation initial setting. Each of the matrix equations A · X = b (A · X = b (1) created by the simulation execution control unit by the Poisson matrix creating unit, the electron current continuity formula matrix creating unit, and the hole current continuity formula matrix creating unit. Where A is a coefficient matrix, X is a matrix to be solved, and b is a known matrix) The coefficient matrix A
By performing an incomplete LU factorization on the lower triangular matrix L and the upper triangular matrix U, and using the matrix (L · U) obtained by the incomplete LU factorization to perform an operation by the indirect method in the indirect method matrix operation unit. A device simulator that repeatedly obtains a solution of each element of the matrix X and outputs the solution to an output device via a simulation post-processing unit under the control of a simulation execution control unit, the matrix creating unit of the Poisson's equation , The electron current continuity equation matrix creating unit and the hole current continuity equation matrix creating unit apply the semiconductor device to a rectangular work area as the coefficient matrix A regardless of the shape of the semiconductor device, Of the elements of the discrete points in the region in which the semiconductor device exists, and the elements of the discrete points in the non-analysis region in which the semiconductor device does not exist and the elements in the boundary region. The minute element is an integer, and the other elements are means for generating a matrix consisting of a dummy having a value of "0", and the indirect method matrix operation unit uses the matrix (L · U) to increase the number of elements. The arithmetic unit is configured to separately process the analysis region and the boundary region of the semiconductor device by the incomplete LU decomposition method.

[Industrial applications]

The present invention relates to a device simulator, and more particularly to a device simulator that analyzes each parameter of a semiconductor device by solving simultaneous equations indicating the operation of the semiconductor device by an indirect method.

In order to increase the degree of integration and response speed of very large scale integrated circuits (VLSI), it is necessary to miniaturize the device, and it is difficult to develop submicron devices empirically because of this. .

Therefore, in order to research and develop VLSI semiconductor devices, a device simulator is required to grasp the internal state and external characteristics of the device by simulation. The device simulator is required to analyze a device of any shape with high convergence, high accuracy, and high speed.

[Conventional technology]

As a semiconductor device to be analyzed by a device simulator, for example, a substrate 21 having a thickness of 8 μm as shown in FIG.
A MOS type field effect transistor (source region 22 and drain region 23 each having a width of about 2 μm and an oxide film 24 made of silicon dioxide (SiO ₂ ) having a width of 1 μm and a film thickness of about 300 Å ( When analyzing a FET, first, three basic equations (Poisson's equation, electron current continuity equation, hole current continuity equation) describing the inside of the semiconductor are prepared.

Where Poisson's formula is And the equations for the continuous current are Is. However, in the formulas (1) to (3), ε is the induction rate and V
Is the potential, q is the charge amount, N _d is the donor concentration, N _a is the acceptor concentration, p is the hole density, n is the electron density, J _p and J _n are the current densities, and U is the generation / recombination term.

Poisson's formula is the electric field through a closed surface It is shown that the total flux of is equal to the total charge in the closed surface, and the current continuity equation shows that the increment of the current (density) in a certain minute section is the time change of carriers in that region. It shows that they are equal.

Solving the above equations (1) to (3), the potential V and the hole density p
, And the electron density n are obtained, but it is difficult to solve the second-order partial differential equation, so the discretization is performed using the finite difference method. Here, in Poisson's equation, n and p on the right side are functions of the electric potential V and are nonlinear throats, and are linearized using the Newton method.

That is, as shown in FIG. 7 (A), the MOS FET to be analyzed is divided into a plurality of rectangular meshes in the analysis area inside the MOS FET, and a plurality of discrete points (intersection points of the meshes) obtained thereby are obtained. (Also referred to as a grid), the physical quantity at each discrete point is represented together with the physical quantity around it. For example, the potential V _{jk at} an arbitrary discrete point (j · k) is not only V _jk , but also V _{(j-1) k} , V _{j (k-1)} , V _{j (k + 1)} , V _{(j + 1) k} using equation (1), A _1jk・ V _jk −A _2jk・ V _{(j-1) k} −A _3jk・ V _{(j + 1) k} −A _4jk・ V _{i (k-1)} − It can be expressed as A _5jk · V _{j (k + 1)} = A ₆ (4).

Similarly, if we obtain the above equation for each of the other discrete points,
As shown in FIG. 7 (B), the matrix equation of A · V = b (5) is obtained.

The other two current equations of currents of holes and electrons were discretized in the same manner to obtain the matrix equation similar to the equation (5).

As the solution of the matrix equation of the equation (5), the direct method (Gaussian elimination method, the Crout method, etc.) and the indirect method (sequential excessive relaxation method (SOR) method, incomplete LU decomposition CGS with increasing number of elements)
(ILUCGS) method).

The direct method is a method of obtaining the inverse matrix A ^-1 and obtaining the elements of the matrix V (here, the potentials at each discrete point) from A ^-1 · b. If there is no rounding error, an exact solution can be obtained by a finite number of calculations. can get. Further, even when the approximate solution is obtained, the required number of calculations is determined almost independently of the required accuracy.

On the other hand, the indirect method starts with one approximate solution and obtains a more accurate solution for each iteration, but infinite iterations are required to obtain an exact solution even if there is no rounding error. Yes, the accuracy of the solution depends on the number of iterations.

However, the direct method needs to obtain the inverse matrix A ^-1 as described above, but since the inverse matrix A ^-1 is a sparse large matrix, the amount of calculation, the memory capacity, and the calculation time are extremely large. Used the indirect method to find the solution without using the inverse matrix A ^-1 .

[Problems to be solved by the invention]

According to the above indirect method, the coefficient matrix A in the equation (5) is used. However, since the coefficient matrix A is conventionally created for the discrete points inside the input device shape, the coefficient matrix A is shown in FIG. In the case of the MOS type FET shown, there is a problem that the cycle of the coefficient matrix A changes depending on the shape of the oxide film 17 and the versatility is poor.

Further, conventionally, the boundary region forming the outer edge of the device is set as a non-discrete point, and the analysis is not performed.

Further, since semiconductor devices have become more and more miniaturized and highly integrated in recent years, the impurity distribution and the element shape have become complicated, and the electric field and carrier density change greatly depending on the location. , Non-definiteness became strong, convergence was insufficient in the conventional method, calculation time became long, and a solution could not be obtained in some cases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a device simulator capable of performing high-speed analysis regardless of the element shape of a semiconductor device.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. 1 in the figure
Is an input device, 2 is an analysis condition setting unit, 3 is a simulation initial setting unit, 4 is a simulation execution control unit, and 5, 6
And 7 are matrix creating sections for creating Poisson's equation, electron current continuity equation, and hole current continuity equation, and 8 is an incomplete matrix.
An LU decomposition processing unit, 9 is an indirect method matrix calculation unit, 10 is a post-simulation processing unit, and 11 is an output device for outputting a solution.

According to the present invention, each coefficient matrix in the matrix equation A · X = b (where A is a coefficient matrix, X is a matrix to be solved, and b is a known matrix) created by the matrix creating units 5, 6 and 7, respectively. It is characterized by the creation of A and the calculation processing of the indirect method matrix calculation unit 9.

That is, each of the matrix generation units 5, 6 and 7 has a coefficient matrix A
As a result, the semiconductor device is applied to a rectangular work area regardless of the shape of the semiconductor device, and elements for each discrete point of the area where the semiconductor device exists in the work area, as well as the discrete points of the non-analysis area where the semiconductor device does not exist. Among the elements for each of, a diagonal element is generated as an integer, and other elements generate a matrix of dummy values of "0".

Further, the indirect method matrix operation unit 9 uses the matrix (L · U) obtained by the incomplete LU decomposition to increase the number of elements incomplete LU decomposition (ILUCGS: Incomplete LU Conjugate Gradient Square).
By applying the method d), the analysis region of the semiconductor device and the boundary region are separately processed to calculate the elements of the matrix X.

[Action]

The shape of the semiconductor device input by the input device 1 is, for example, as shown by 14 in FIG. 2 (A), the MO shown in FIG.
Assuming that the structure of the S-type FET is similar to that of the S-type FET, each of the matrix forming sections 5, 6 and 7 is independent of the element shape as shown in FIG.
Second, apply it to the rectangular work area 15 as shown in
A matrix equation A · X = b as shown in FIG.

Among them, the coefficient matrix A is a discrete point (mesh) of a region where the semiconductor device 14 exists in the work region 15 shown in FIG. 2A (which is composed of the analysis region 16 and the boundary regions 17 and 18). Of each of the discrete points of the non-analysis regions 19 and 20 in which the semiconductor device 14 does not exist is substituted as the dummy D, and the diagonal of the matrix of the dummy D For example, the value of the component is “1”, and the other dummy values are “0”.

The reason why the value of the dummy D is selected in this way is that when the incomplete LU factorization processing unit 8 of the matrix thereafter,
There is a process of performing division by each element of the diagonal term of the coefficient matrix A. At that time, if each element of the diagonal term is "0", an error occurs, so the dummy D of the diagonal term is an integer "1". "It was placed,
Further, by setting the dummy D other than the countermeasure item to “0”, all the elements x of the matrix X obtained by multiplication with this dummy D finally become “0”, and there is no influence of the dummy D in calculation. Because it can be done.

On the other hand, by substituting the dummy D as described above, the coefficient matrix A always has a constant period regardless of the element shape, and can be expressed in a band shape having many zero components, which simplifies the calculation.

Further, for the boundary regions 17 and 18, the Dirichlet condition (V, n, p in the equation (1) are fixed values respectively) is applied in the normal simulation initial setting unit 3, and as shown in FIG. The Neumann condition (derivative coefficient in the normal direction = 0) is also applied to the natural boundaries at the left and right ends of). For this reason, conventionally, when calculating as an actual coefficient matrix, these regions have been treated as non-analytical regions.

However, the calculation process by the ILUCGS method described below is in progress. In the calculation of the direction vector that minimizes the error scale, a difference occurs in the calculated direction vector when the boundary region is taken into consideration and when it is not taken into consideration. Therefore, in the present invention, similarly to the above-described non-analyzing region, the coefficient matrix A in which the dummy processing is applied to the boundary regions 17 and 18 is created.

In this way, it is possible to obtain the coefficient matrix A that is completely unaffected by changes in the element structure and element shape.

The matrix equation based on Poisson's formula created by the matrix creating unit 5 is supplied to the incomplete LU factorization processing unit 8 of the matrix under the control of the simulation execution control unit 4 in FIG. After incomplete LU decomposition into a triangular matrix L and an upper triangular matrix U to form a matrix (L · U), the matrix (L · U) is supplied to the indirect method matrix operation unit 9 where the CGS method is applied and the semiconductor device is analyzed. The solution of each element of the matrix X is calculated by repeating the calculation until the solution converges separately for each of the area and the boundary area.

When the calculation of this solution is completed, the matrix equation based on the electron current continuity equation created by the matrix creating unit 6 and the matrix equation based on the hole current continuity expression created by the matrix creating unit 7 are also sequentially performed. The solution is calculated at.

Here, the separate processing of the analysis area and the boundary area by the indirect method matrix calculation unit 9 will be described in more detail. For example, as shown in FIG. 3, the discrete points (analysis points) of the semiconductor device 14 are in the horizontal direction. There are a total of 56 in total, 8 in total and 7 in the vertical direction, and the potential (potential) at each discrete point.
Let V ₁ , V ₂ , ..., V ₅₆ , the matrix equation formed is as follows.

Here, in the above equation, the leftmost coefficient matrix A is 56 × 56 rows, 56 × 56
In the matrix of columns, the shaded area indicates the coefficient of the boundary area, and the blank area indicates the coefficient of the analysis area (not shown).

Usually, when this calculation is performed using a computer, an array is given to each coefficient, and a value is subtracted from the array when performing the calculation. Now the coefficient A1
And give an array to each element, A1 (1), A1
(2), ..., A1 (56). Similar processing is applied to other coefficients.

Using this, any one formula in ILUCGS method r ₀ =
Considering the case of performing the calculation by b-Ax ₀ , the calculation is performed by the following formula.

_{r 0 (1) = b (} I) -A1 (I) × x 0 (I) -A2 (I) × x 0 (I-1) -A3 (I) × x 0 (I + 1) -A4 (I) × x ₀ (I-8) −A5 (I) × x ₀ (I + 8) (7) When this is calculated for all discrete points, the number I of discrete points is 56 as shown in FIG. I'm 1 so I
Vary from to 56.

Then, for example, when I = 1, x ₀ (I-8) becomes x ₀ (−
7), and when I = 56, x ₀ (I + 8) is x ₀ (64)
Therefore, the array of this part must be secured as a work area. In order to do this,
It is conceivable to carry out by increasing A1 (-7) to A1 (64). However, in that case, the work area is large and the memory used by the computer increases.

Therefore, in the present invention, the boundary region (I = 1 to 8,49 to 56) and the analysis region (I = 9 to 48) are sequentially calculated separately, and when I = 1 to 8 is calculated when the boundary region is calculated. A4 in equation (7)
The term of (I) × x ₀ (I-8) is deleted, and when I = 49 to 56, by deleting A5 (I) × x ₀ (I + 8) in the equation (7), A1 (I ) -A5 (I), b (I) are all calculated with 56 sequences.

As described above, the solution obtained by the indirect method matrix calculation unit 9 is output to the output device 11 via the simulation post-processing unit 10 under the control of the simulation execution control unit 4 in FIG.

〔Example〕

FIG. 4 is a flow chart for explaining the operation of the embodiment of the main part of the present invention. First, the basic equation, element structure and element shape are substituted by the above-mentioned input device (step S ₁ ), and analysis conditions, initial values and boundary values are set in the analysis condition setting unit 2 and the simulation initial setting unit 3. Then, based on the information input through the simulation execution control unit 4, the matrix creating unit 5 discretizes the Poisson's formula (1) (steps in FIG. 4).
After the matrix equations of S ₂ ) and (5) are created, the coefficient matrix A is subjected to a dummy process by the above-described method to form a coefficient matrix which is not affected by the element shape (at the same step,
S ₃ ).

Next, under the control of the simulation execution control unit 4, the coefficient matrix A in the matrix equation based on the above Poisson's equation is incomplete LU decomposed by the matrix incomplete LU decomposition processing unit 8 and the eigenvalues are clustered in diagonal terms. Then (step S 4 in FIG. ₄ ), the CGS method is applied based on the matrix (L · U) thus obtained to obtain the element solution of the matrix X.

The ILUCGS algorithm itself, which is one of the indirect methods, is well known (for example, Naruto Sato: “Highly convergent matrix calculation method for device simulator”, IEICE Transactions, '86
/ 11 vol.J69−C No.11, p, 1396).

That is, in FIG. 4, the initial value x ₀ of the approximate solution vector is given, the residual vector r ₀ is calculated (step S ₅ ), the gradient α is calculated using the residual vector r _0, and the next by the k-th iteration. After sequentially calculating (h: work) the solution vector x _{k + 1} (step S ₆ ), a convergence judgment is made (step S ₇ ), and if not converged, the obtained solution vector is used. Calculate the residual vector r _{k + 1} at the k-th iteration, and compare it with the previous residual vector to calculate the gradient β _k and the direction vector P _{k + 1} (e: work) (Including the boundary area: step S ₈ ). Direction vector P _{k + 1} obtained after that
After determining the predicted new following approximate solution vector a deviation from the true solution based on (Step S _6), performs the convergence determination again (step S _7).

Hereinafter, in the same manner as described above, the calculation of steps S ₈ and S ₆ is repeated until the solution converges, and when the solution converges, the solution is output (step S ₉ ) and the convergence determination of the solution is performed again (step S ₉ ).
S ₁₀ ). If not converged output solutions here, returns to the processing in step S _3, after obtaining a coefficient matrix having been subjected to the dummy processing, the processing operation in steps S ₄ to S _9. The solution thus obtained is subjected to convergence determination again in step S ₁₀ .
Thereafter, the same operation as described above is repeated until convergence is reached, and the solution determined to be converged at step S ₁₀ is output (step S
₁₁ ). Here, it is the solution of the matrix equation of Poisson's equation, and the electric potential at each discrete point is obtained.

After the solution of the matrix equation based on Poisson's equation is obtained, the matrix equation based on the electron current continuity equation and the matrix equation based on the hole current continuity equation are similarly performed by steps S _{3 to} S _{11 in} FIG. Are sequentially solved for. The output of the solution in step S ₁₁ is performed by the output device 11 through the post-simulation processing unit 10 in FIG.

Incidentally, in FIG. 4 as described above, the processing of steps S ₅ to S ₈ separately for analysis region and the boundary region is performed sequentially.

Meanwhile, if the determination is made that does not converge in step S ₁₀ obtained, led to S ₅ through step S _3, S _4, although given the initial value x ₀ of the approximate solution vector where successive approximation The calculation speed in the ILUCGS method is the initial value x ₀
Greatly depends on how close to the solution is chosen.

Therefore, in this embodiment, the previous calculation result (that is, the solution output in step S ₉ ) is used as the initial value as the initial value x ₀ of the approximate solution vector of the ILUCGS method. As a result, according to this embodiment, it is possible to improve the convergence.

According to the experiments by the present inventor, the gate voltage V _G of the MOS type FET shown in FIG. 6 is 4 V, the source voltage V _S is 0 V, and the back gate voltage V is
_{When BG} was set to −2 V and the drain voltage V _D was increased by step bias, the simulation result as shown in FIG. 5 was obtained. In the figure, the vertical axis represents the number of convergences of the inner loop including step S _{7 in} FIG. 4, and the horizontal axis represents the number of convergences of the outer loop including step S _{10. The} initial calculation result is x ₀ and the previous calculation result is shown. In the case of this embodiment using
It has been confirmed that the calculation speed is about 1.2 times faster than the characteristic II shown by the broken line when ₀ is always used as the initial value x ₀ .

Further, the results of analysis when the conventional Gaussian elimination method and SOR method and this embodiment were simulated for the MOS type FET shown in FIG. 6 under the same conditions, respectively, are as shown in the following table.

As can be seen from the above table, according to the present embodiment, the solution is about 1.5 times faster than the conventional Gaussian elimination method (one of direct methods) and SOR method (one of indirect methods). We were able to obtain it, and it was possible to solve even with a higher bias with considerably good accuracy.

〔The invention's effect〕

As described above, the present invention has the following various features.

It is possible to create a coefficient matrix having a constant period that does not depend on the element shape of the semiconductor device, is versatile, and can perform simulation by a high-speed matrix solution method.

Since the boundary region is also regarded as an analysis point and dummy processing is performed, it is possible to obtain a direction vector considering the entire device in the solution process of the ILUCGS method.

Since the boundary area and the analysis area are separately and sequentially processed in the solution process of the ILUCGS method, the memory capacity used can be reduced.

Since the previous calculation result is used as the initial value of the approximate solution vector of the ILUCGS method, the solution can be obtained in a shorter time than when the initial value is always constant.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of matrix formation of a main part of the present invention, FIG. 3 is an explanatory diagram of calculation processing of a boundary region of the present invention, and FIG. 4 is a main part of the present invention 5 is a flow chart for explaining the operation of one embodiment of the present invention, FIG. 5 is a comparative explanatory view of the number of convergences in the present invention, FIG. 6 is a structural cross-sectional view of an example of a MOS type FET to be analyzed, and FIG. 7 is a conventional example. It is a matrix creation explanatory drawing. In the figure, 1 is an input device, 2 is an analysis condition setting unit, 3 is a simulation initial setting unit, 4 is a simulation execution control unit, 5 is a Poisson matrix creating unit, 6 is an electron current continuity matrix creating unit, 7 is a matrix creating unit of the formula of continuous hole current, 8 is an incomplete LU decomposition processing unit of the matrix, 9 is an indirect method matrix calculation unit, 10 is a simulation post-processing unit, 11 is an output device, 14 is a semiconductor device, 15 Indicates a work area, 16 indicates an analysis area, 17,18 indicates a boundary area, and 19,20 indicates a non-analysis area.

Claims (1)

[Claims] 1. Information of a semiconductor device (14) to be analyzed is input by an input device (1), and based on the information, an analysis condition setting unit (2) and a simulation initial setting unit (3) respectively set analysis condition and perform simulation. Initialization is performed and the simulation execution control unit (4) controls the Poisson equation matrix creation unit (5), the electron current continuity equation matrix creation unit (6), and the hole current continuity equation matrix creation unit (7). ), Each matrix equation A * X = b (where A is a coefficient matrix, X is a matrix to be solved, and b is a known matrix) are sequentially supplied to the incomplete LU decomposition processing unit (8). Then, the coefficient matrix A is subjected to incomplete LU decomposition into a lower triangular matrix L and an upper triangular matrix U, and an indirect method matrix operation unit (9) is used by using a matrix (LU) obtained by the incomplete LU decomposition. ), The matrix is obtained by repeating the operation by the indirect method. Is a device simulator which obtains a solution of each element of the Poisson and outputs the solution to the output device (11) through the simulation post-processing section (10) under the control of the simulation execution control section (4). The formula matrix creating unit (5), the electron current continuity formula matrix creating unit (6), and the hole current continuity formula matrix creating unit (7) use the shape of the semiconductor device (14) as the coefficient matrix A. Irrespective of the above, the semiconductor device (14) is applied to a rectangular work area (15), together with the elements for each discrete point of the area (16) in the work area (15) in which the semiconductor device (14) exists. , The semiconductor device (1
4) Of the elements of the non-analyzed region (19,20) where there is no boundary and the boundary region (17,18), the diagonal elements are integers, and the other elements are "0". The indirect method matrix operation unit (9) is a means for generating a matrix composed of a dummy, and analyzes the semiconductor device (14) by an incomplete LU factorization method with increasing number of elements using the matrix (L · U). A device simulator, characterized in that the device simulator is a calculation unit that repeatedly calculates each of the region (16) and the boundary regions (17, 18) until the solution converges to obtain the solution of each element of the matrix X.