JPH084339B2 - Disk playback demodulator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video disc reproducing apparatus for reproducing and demodulating a high-definition (high-definition television) band compressed signal.

Conventional technology High-definition video signals, which provide higher definition images than the current standard television system, are transmitted by broadcasting satellites.
A band compression transmission method called MUSE has been proposed in which one channel with a 27 MHz bandwidth is used for transmission.

Reference (1): Yuichi Ninomiya et al., "Satellite 1-channel transmission system (MUSE) for high-definition television", Technical Report of the Institute of Television Engineers, Technical Circuit Research Group, TEBS95-2, March 1984, 1984.
The transmission method shown here is for compressing and transmitting a high-definition signal originally having a band of 20 MHz or more to about 8 MHz by sub-Nyquist sampling, and transmitting it. In this case, one image is completed in four fields, that is, two frames. Therefore, the image receiving device has a memory for two frames in terms of the transmission signal rate, and one image is completed by interpolating the transmitted television signal by frame.

On the other hand, since the HDTV signal is compressed from the band of 20MHz or more to about 8MHz by this method, it is useful not only for satellite broadcasting but also for recording and reproducing, and its application to VTRs and video discs is considered.

Especially for video discs, high-definition, high-definition, wide and powerful images can easily be enjoyed by ordinary households, so it can be expected to spread quickly. The major difference between this MUSE type video disc and the current television type is that the sync signal cannot be amplitude-separated from the reproduced signal easily because the sync signal is positive polarity synchronization, and therefore disc rotation control with jitter and other time axis fluctuations, etc. In addition, the synchronization signal cannot be easily separated and used. Therefore, it has been proposed that a pilot signal is multiplexed with a television FM signal and recorded on a disc, and this pilot carrier signal is detected and used at the time of reproduction to control rotation of the disc.

Reference (2): Yuichi Ninomiya et al., "Home video disk by MUSE method", Technical report of the Institute of Television Engineers of Japan, Circuit Circuit Study Group, TEBS 99-4, September 20, 1984, explained in Reference (2) above. As described above, the MUSE signal is a method that is realized by sub-Nyquist sampling, so if there is time-axis fluctuation or jitter in the reproduced signal, the resemble phase will shift and the original signal cannot be decoded, so it is necessary to correct the jitter. .

Problems to be Solved by the Invention As described above, the jitter correction is important in the MUSE type video disc, but from the viewpoint of reproduction signal quality, a digital time base collector (hereinafter abbreviated as TBC) using a digital memory is used. ) Is effective. On the other hand, since the MUSE television signal has a band of 8 MHz or more, in order to convert it into a digital signal without damaging the reproduction band, generally, at least a sampling clock of 24 MHz or more is used for analog-digital conversion (hereinafter referred to as A / Abbreviated as D) is required. However, the frequency of this level is almost the limit of the normal TTL logic IC, and high-speed type IC
However, there is a drawback that power consumption is large.

Therefore, MUSE sampling clock 16.2MH
It is possible to resample at the frequency of z,
In this case, the resampling phase is very important, and the phase must be accurately matched with the input signal having jitter. For this purpose, it is necessary to create a resampling clock using the pilot carrier signal in the disc reproduction signal shown in the reference (2), and the pilot carrier and the reproduced MUSE signal have a phase relationship. Since it is not specified, there is a problem that it is necessary to detect the sampling phase and control the phase of the resampling clock separately.

In view of the above point, the present invention has an object to provide a simple sampling phase detection circuit and a disk reproduction demodulation circuit having a circuit capable of performing efficient resample clock phase control in combination therewith.

Means for Solving the Problems The present invention relates to a disc reproducing apparatus for reproducing a video disc on which a television FM modulated signal, a pilot carrier and the like are recorded, and a reproducing FM signal is demodulated from an output signal of the disc reproducing apparatus. An FM demodulation circuit, an analog-digital conversion circuit that converts a television signal demodulated by this FM demodulation circuit into a digital signal, and a time axis fluctuation of the digital television signal converted by this analog-digital conversion circuit is absorbed. A clock generator constituted by a time base collector circuit, a pilot carrier extraction circuit for extracting a pilot carrier from the output signal of the disc reproducing device, and a phase locked loop oscillation circuit for generating a clock signal synchronized with the extracted pilot carrier. Circuit and the analog-to-digital Sync signal detection circuit that detects the sync signal in the converted signal, and the sampling phase of the analog-digital conversion circuit leads or lags the normal sampling phase from the sync signal detected by this sync signal detection circuit. In the time axis fluctuation compensating means, which comprises a phase detection circuit for detecting whether or not the phase of the sampling clock supplied to the analog-digital conversion circuit is changed, and controlling the output of the phase detection circuit. An address generator composed of an up-down counter which is switched up or down by a signal, and a clock which is substantially input by switching the delay time of the output signal of the clock generator by the output signal of the address generator. By changing the phase of the signal, the analog - a disc reproducing demodulating apparatus characterized by comprising a clock signal phase circuit for supplying the digital converter circuit.

The disc reproducing / demodulating device according to the present invention generates the control signal of the up-down counter of the next stage according to the detected advance or lag of the sampling phase by the means, and uses the counter output as an address signal to output a plurality of different phases.
By switching the 16.2MHz resample clock and supplying it to the A / D conversion circuit, the optimum phase is always achieved.

EXAMPLE A concrete configuration example and an example of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a disc reproducing device for reproducing an FM signal or the like from a disc on which a video signal is recorded by a pickup, 2 is an FM demodulation circuit for demodulating the reproduced FM signal into an original video signal, and 3 is a demodulator A / D converter circuit for converting analog video signals to digital, 4 writes jittery video signals in memory with a clock synchronized with it, and reads jitter with another stable clock (not shown) A digital-time base corrector (TBC) 5 for obtaining a taken television signal is a demodulator for demodulating a jitter-corrected television signal, that is, a MUSE signal into an original wide band high-definition signal.

Reference numeral 6 is a pilot carrier extraction circuit for extracting a pilot carrier in the FM signal reproduced from the disc, 7 is a phase comparison circuit for comparing the phase of the pilot carrier with an output signal of a frequency divider circuit described later, and 8 is the phase Voltage controlled oscillator (VCO) controlled by output of comparator circuit, 9
Is a frequency divider circuit that divides the clock signal that is the output of the VCO to make the same frequency as the pilot carrier, and the portion 14 surrounded by the dotted line consisting of the above 7, 8 and 9 circuits is synchronized with the pilot carrier. Configure a phase-locked loop (PLL) circuit that generates a clock.

10 is a sync signal detection circuit that detects the frame pulse and the horizontal sync signal that are vertical sync signals from the digitally converted MUSE signal, and 11 is the resample phase of the A / D conversion circuit from the detected sync signal from the normal position Phase detection circuit for detecting whether it is advancing or lagging, 12 counts up or down according to the output signal of the phase detection circuit, and supplies up-down for supplying a value for switching the clock phase as an address signal to the next stage A counter, 13 is a clock phase shift circuit that selects a clock of a corresponding phase from a plurality of clock phase signals according to an input address signal and supplies it as a resample clock of the A / D conversion circuit.

The input video signal with jitter and the clock whose time-axis fluctuation completely match can be obtained by 14 PLL circuits, but as explained in the section of the prior art, the clock phase cannot be adjusted as it is. That is, the optimum phase is obtained by the clock phase shift circuit shown in FIG.

Generally, the phase of the pilot carrier with respect to the video signal is determined at the time of recording on the disc and does not change during reproduction of one disc. Therefore, as shown in this configuration example, the response of control of the resample phase may be slow. Further, since the re-sampling phase detection of the horizontal synchronizing signal is performed once in one horizontal scanning period, any further speed is meaningless. From the above, a horizontal synchronizing pulse or a pulse obtained by dividing the horizontal synchronizing pulse is suitable for the clock of the up-dow counter.

Next, FIG. 2 shows the principle of detecting the resample phase from the horizontal synchronizing signal. For details, see Reference (1) above.
Therefore, only the parts necessary for the present invention will be described here. In the figure, reference numeral 20 denotes a horizontal synchronizing signal waveform, the polarity of which is actually inverted every scanning line. Numerals 21 to 24 are marks showing the regular resample positions, and among them, the values of 22, 23 and 24 are used for the actual calculation. As shown in the figure, each value is D1, D
If 2, D3, it can be determined whether the resample position is ahead of or behind the normal position depending on whether the value calculated by (D1 + D3) / 2-D2 is positive or negative. Can also be calculated. As described above, the polarity of the signal is actually inverted for each scanning line, so that it is necessary to perform processing such as inverting the data accordingly.

Next, in FIG. 3, a phase detection circuit (FIG.
A block diagram of a specific circuit of 11) will be described. The details of the phase detection and phase synchronization are described in detail in, for example, Japanese Patent Laid-Open Publication No. 59-221091, "Clock Phase Locking Method". In the figure, 30 is a digital video signal input terminal, 31 and 32 are delay elements having a delay time of 2τ ₀ when the time of one cycle of the clock is τ _0, and 33 adder outputs data of 0τ ₀ and 4τ ₀ . What to add,
34 is a divider that halves the data of the adder, and 35 is the 1
A subtracter for subtracting 2τ ₀ data from the / 2 data, 36 is a gate circuit for extracting only the data of the horizontal synchronizing signal portion from the operation result, and 37 is an operation result output terminal.

The resample phase can be detected as described above. However, in the present invention, since it is sufficient to determine only the lead / lag, the number of bits until the operation shown in FIG. However, binary data, that is, 1-bit data may be used thereafter. Specifically, only the most significant bit after calculation may be supplied to the next stage.

Next, the specific configurations of the up-down counter and the clock phase shift circuit (FIGS. 12 and 13 in FIG. 1) will be described with reference to FIG. In the figure, 40 is a clock signal input terminal obtained by the PLL circuit (Fig. 1), 41 is a minute delay element (delay time τ ₁ ), and is connected in series by the number of stages required to obtain a plurality of clock phases. It is connected. The relationship between this delay time (τ ₁ ) and the number of stages is that the frequency of the sampling clock is 16.2 MHz in the case of the MUSE signal, so if the precision of the controlled phase is 2 nsec or more, τ ₁ will be 1.93 nsec, and a 32 stage configuration will be used. All phases will be obtained. Reference numeral 42 denotes a switching circuit, which receives a clock of each phase from each connection point of the delay elements 41 connected in series, and selects a corresponding one of the above phases by an address signal applied to another control terminal. It is output as a resample clock, and is supplied from the terminal 32 to the next stage. According to the example described above, the control signal has 5 bits because there are 32 stages, and the optimum phase is selected from 32 types of phases. Reference numeral 44 is a lead / lag 1-bit signal input terminal supplied from the phase detection circuit, and 45 is a 32-stage counter that counts up or down according to the lead / lag signal (1 or 0). Reference numeral 46 is an input of a clock for operating the counter, and in the example of the present invention, a horizontal synchronizing pulse or its frequency-divided pulse is used. 47 is a counter output 32 stages, that is, 5
It is added to the control signal input of the switching circuit 42 as a bit address signal.

Since the specific contents of the circuits other than those described above are all known, the description thereof is omitted here.

According to the disc reproducing / demodulating device of the present invention, in the MUSE video disc of the pilot carrier recording system,
The re-sampling phase control circuit when re-sampling with the transmission sampling clock to configure the digital TBC can be realized very easily, and many circuits such as the phase detection circuit are the same as the MUSE decoder.
In the case of being made into an IC, the IC can be used, and since the circuit added to the IC is simple, there are various merits such as that the disc player can be manufactured at low cost, and the effect is very large.

[Brief description of drawings]

FIG. 1 is a block diagram of a disc reproducing / demodulating device according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining a horizontal synchronizing signal and a resample position of a MUSE signal, and FIG. 3 is a block diagram of a phase detecting circuit. FIG. 4 is a block diagram of an up-down counter and a clock phase shift circuit according to the present invention. 1 ... Disk playback device, 2 ... FM demodulation circuit, 3 ... A /
D conversion circuit, 4 ... Digital TBC, 5 ... MUSE demodulator, 6 ... Pilot carrier extraction circuit, 7 ... Phase shift comparison circuit, 8 ... Voltage controlled oscillation circuit, 9 ... Dividing circuit, 10
...... Sync signal detection circuit, 11 …… Phase detection circuit, 12 …… Up-down counter, 13 …… Clock phase shift circuit, 14 ・ ・ ・
… PLL circuit, 41 …… Small delay element, 42 …… Switching circuit, 45 …… Up-down counter.

Claims (1)

[Claims] 1. A disc reproducing device for reproducing a video disc on which a television FM modulated signal, a pilot carrier and the like are recorded, an FM demodulation circuit for demodulating a reproduced FM signal from an output signal of the disc reproducing device, and the FM. An analog-digital conversion circuit for converting a television signal demodulated by the demodulation circuit into a digital signal; a time base collector circuit for absorbing a time base fluctuation of the digital television signal converted by the analog-digital conversion circuit; A pilot carrier extraction circuit for extracting a pilot carrier from the output signal of the disk reproducing device, a clock generation circuit configured by a phase locked loop oscillation circuit for generating a clock signal synchronized with the extracted pilot carrier, and the analog-digital circuit. The same in the converted signal A sync signal detecting circuit for detecting a signal, and whether the sampling phase of the analog-digital conversion circuit leads or lags the normal sampling phase from the sync signal detected by the sync signal detecting circuit is detected to detect the analog- In a time axis fluctuation correcting means composed of a phase detection circuit for generating a control signal for changing the phase of the sampling clock supplied to the digital conversion circuit, the control signal output from the phase detection circuit is used to switch between counting up and counting down. An address generator composed of an up-down counter, and by switching the delay time of the output signal of the clock generator circuit by the output signal of the address generator, the phase of the input clock signal is substantially changed to change the phase. Used for analog-digital conversion circuit And a clock signal phase circuit for supplying the same.