JPH087940B2 - Data demodulation circuit - Google Patents

Description

The present invention relates to a data demodulation circuit for demodulating data stored in a magnetic storage device such as a prop disk device (hereinafter referred to as FDD), and more particularly to a data demodulation circuit thereof. Provided inside,
The present invention relates to a signal generation circuit that generates a reference signal for defining the pulse width of a window signal.

(Prior Art) Conventionally, as a technology in such a field, for example, there is one described in Interface Magazine (1983-5.) CQ Publisher P.186-192. Hereinafter, the configuration and operation (1)-
(4) will be described with reference to FIGS. 2 to 9.

(1) Circuit Configuration of FIG. 2 FIG. 2 is a block diagram showing a configuration example of a conventional data demodulation circuit.

This data demodulation circuit is of a variable frequency oscillator (VFO) type that uses a phase-locked loop circuit (hereinafter referred to as PLL circuit). For example, a read data signal RDATA from the FDD is input to the data demodulation circuit. A signal generation circuit 1 for generating a pulse signal by a monostable multivibrator (monostable multivibrator, hereinafter simply referred to as MM), and a PLL circuit 2 for outputting an oscillation frequency signal tuned to the output pulse signal of the signal generation circuit 1. , And a control circuit 3 for controlling the data demodulation operation.

The signal generation circuit 1 is composed of an MM11, a capacitor 12 and a variable resistor 13, is triggered by a read data signal (first input signal) RDATA, and has a pulse width of a pulse determined by the time constant of the capacitor 12 and the variable resistor 13. It is a circuit that outputs a signal (reference signal) PDI ₀ and supplies it to the PLL circuit 2.

The PLL circuit 2 includes a phase comparator 21, a low pass filter (LPF) 22 and a voltage controlled oscillator (VCO) 23 that are connected in cascade.
A divider 24 connected to the feedback loop of the voltage controlled oscillator 23 and the phase comparator 21 and a multiplexer (MP for signal selection).
X) 25, and a data separation circuit 26 and an OR circuit (hereinafter referred to as OR) 27 provided on the input side of the multiplexer 25.

The phase comparator 21 includes an output pulse signal PDI ₀ from the signal generation circuit 1 and an output pulse signal (second pulse signal) from the multiplexer 25.
Input signal) PDI ₁ at a falling timing, and outputs a comparison signal having a pulse width proportional to the phase difference to the low-pass filter 22. The low-pass filter 22 removes the high frequency component of the comparison signal and supplies it to the voltage control oscillator 23. The voltage control oscillator 23 outputs an oscillation signal having a frequency proportional to the voltage level of the input signal and supplies it to the frequency divider 24. Is.

The frequency divider 24 is the oscillation signal 1 / N of the voltage controlled oscillator 23 (however,
(N; integer) frequency division, and outputs a window signal WD to the multiplexer 25, the data separation circuit 26 and the control circuit 3. The multiplexer 25 is a circuit for switching and outputting two input signals by a switching signal SW given from the control circuit 3, and a window signal WD which is an input signal.
Of the output signals of OR and OR27, when the switching signal SW is logic "0", the window signal WD is selected and output as the signal PDI ₁ , and when the switching signal SW is logic "1", the output of OR27 is output. Select signals and output them as signal PDI ₁
The PDI ₁ is supplied to the phase comparator 21.

The data separation circuit 26 uses the signal PDI ₀ from the signal generation circuit 1 in which the clock bit pulse and the data bit pulse are mixed.
Is input and the signal PDI ₀ input when the window signal WD is logic “0” is regarded as a data bit pulse, and a pulse signal (data pulse) DP indicating a data bit is output, and the window signal WD is set to logic “1”. Is a circuit that outputs a pulse signal (bit pulse) CP indicating a clock bit by regarding the signal PDI ₀ input at the time of "as a clock bit pulse, and giving the pulse signal DP or CP to the OR 27 and the control circuit 3. . OR27 takes the logical sum of the pulse signals DP and CP,
This is a circuit that supplies it to the multiplexer 25.

Further, the control circuit 3 receives the window signal WD and the pulse signal DP or CP, generates a switching signal SW based on these inputs, and supplies the switching signal SW to the multiplexer 25.

(2) Description of FIG. 3, FIG. 4 and FIG. 5 FIG. 3 shows an example of the structure of the read data signal RDATA from the FFD and the switching signal SW from the control circuit 3.
It is a figure showing the waveform of.

The read data signal RDATA is a signal that is stored for each sector that partitions the concentric tracks in the disk-shaped FDD, and that signal is stored in the gap area GAP that fills the space between the data areas DA and the head portion of the data area DA. Attached sync area S
It is composed of a YNC, a data mark area DM indicating that the area is a data area DA, and an area DATA in which recording data that is the main body of the area is stored. For example, in case of FDD for 8-bit personal computer, sync area SYNC
Has 12 data 00 _H with "0" arranged, so that area SYN
C contains only the clock. Note that T in the switching signal SW in FIG. 3 indicates the lock pull-in period of the PLL circuit 2.

Here, the demodulation of data will be briefly described with reference to the signal waveform diagrams of FIGS. 3, 4, and 5.

Data storage methods include a single density (FM) method and an improved double density (MFM) method. As shown in FIG. 4, in the MFM method, the read data signal RDAT is generated when the clock is at the H level at “1” in the area DATA of FIG.
This is a method in which A is output and the read data signal RDATA is output when the clock is at the L level where "0" continues for two or more in the area DATA. Corresponding to the clock is the window signal WD of FIG. 2 at the time of reading.

The process of data demodulation is performed in the steps of FIG.
The window signal WD having a predetermined pulse width is obtained by performing phase matching (that is, in synchronization) with the reference clock of the synchronization area SYNC. Then, in a step, as shown in FIG. 5, the window signal WD and the read data signal RDAT
Compared with A, a predetermined data signal (DATA
Signal). Hereinafter, the data demodulation operation will be described with reference to FIGS.
Further details will be given with reference to the drawings.

(3) Circuit operation of FIG. 2 FIG. 6 is a timing chart for explaining the circuit operation of FIG. 2 in the synchronizing signal SYNC of the switching signal SW = "0",
FIG. 7 is a timing chart for explaining the circuit operation of FIG. 2 when the switching signal SW = “1”, that is, in the data mark area DM or area DATA beyond the synchronization area SYNC.

(3) (i) When SW = “0” in FIG. 6 The control circuit 3 in FIG. 2 is a circuit for controlling the reading operation of the data of the FDD cross, and at the start of the reading operation, first, the switching signal SW = “0” is set to the lock pull-in mode of the PLL circuit 2.

In the lock pull-in mode, the multiplexer 25 inputs the window signal WD from the frequency divider 24 and outputs it, so that PDI ₁ = WD. Therefore, the PLL circuit 2 is triggered by the pulse of the read data signal RDATA, and the timing of the falling edge of the signal PDI ₀ and the voltage-controlled oscillator 23 with reference to the signal PDI ₀ exchanged by the signal generating circuit 1 to have a constant pulse width. With the timing of the falling edge of the window signal WD (that is, PDI ₁ ) whose output signal is divided by the divider 24,
The entire loop tries to operate so that the phase difference becomes zero.

The state where the phase difference between the signals PDI ₀ and PDI ₁ becomes 0 and which is stable in time is called the lock state. When the signal SW = “0”, the PLL circuit 2 can enter the lock state if the read data signal RDATA has a constant cycle, but if the read data signal RDATA does not have a constant cycle, , The PLL circuit 2 cannot enter the lock state. This is because if the phase of the reference signal PDI ₀ changes in each cycle, the loop of the PLL circuit 2 loses the reference to follow.

When the read data signal RDATA as shown in FIG. 3 is input to the signal generation circuit 1 and the read operation is started, the PLL
The circuit 2 enters the lock state when the period of the read data signal RDATA reaches a constant region.

Now, the case of the MFM mode as the FDD data format will be described as an example.

Generally, in the MFM mode, the gap region G in FIG.
In AP, the read data signal RDATA is a pulse train signal that does not have a fixed cycle, and when it enters the synchronization area SYNC, it becomes a pulse train signal with a fixed cycle. Therefore, the PLL circuit 2 is pulled into the locked state only after entering this area SYNC.

FIG. 6 is a timing chart in the synchronization area SYNC, and t0 in the figure shows the synchronization of the read data signal RDATA. The output signal PDI ₀ from the signal generation circuit 1 triggered by the read data signal RDATA has a pulse width t 1
Signal. The value of t1 is a value determined by the capacitor 12 and the variable resistor 13 in the signal generation circuit 1, and can be changed by the variable resistor 13.

The signal PDI ₁ is the same signal as the window signal WD, and the time width of the “1” level is t2 and the time width of the “0” level is t3.
And usually t2 = t3. FIG. 6 shows the case where the PLL circuit 2 enters the lock state, in which the falling timings of the signals PDI ₀ and PDI ₁ match and the phase difference between them is 0. The data separation circuit 26 generates a signal CP indicating a clock bit or a signal DP indicating a data bit from the two signals PDI ₀ and WD. Window signal WD
If the signal PDI ₀ rises when = "1", the data separation circuit 26 generates the signal CP. The data separation circuit 26 operates so as to generate the signal DP if the signal PDI ₀ rises when the window signal WD = “0”.
Then, there is no pulse of the signal PDI ₀ when WD = “0”.

The control circuit 3 captures both the signals CP and DP for each cycle of the window signal WD to generate a clock bit string and a data bit string, and detects the synchronization area SYNC.
For example, clock bit = "1" and data bit =
When the combination of "0" continues 16 times, it can be determined that the current read data signal RDATA is in the synchronization area SYNC. This is because, in the MFM mode in the synchronization area SYNC, the above combination usually continues for 8 bits × 12 times (12 bytes) = 96 times.

When the control circuit 3 detects the synchronization area SYNC by such a detection operation of the synchronization area SYNC, the control circuit 3
Set SW and set to "1" as shown in Fig. 3. PLL circuit 2
In the sense that it is in the lock state, the period T from when the synchronization area SYNC is entered until the signal SW becomes “1” is called the lock pull-in period.

(3) (ii) When SW = “1” in FIG. 7 When the switching signal SW becomes “1”, the multiplexer 25 is switched and the logical sum signal of the signals CP and DP is the output signal PDI _{1 of the} multiplexer 25. Becomes This state is shown in FIG.

When the read data signal RDATA exceeds the synchronization area SYNC and enters the data mark area DM or the area DATA, its pulse period is generally not constant. As shown in FIG.
In terms of the interval between adjacent pulses, t0, 3/2 · t0, and 2 · t
The signal has three time intervals of 0 mixed. Therefore the signal P
Similarly, DI _{0 is} also a pulse train signal in which three types of time intervals of t0, 3/2 · t0, and 2 · t0 are mixed.

Therefore, when the switching signal SW = 1, the signal PDI ₁
Using the signals CP and DP generated by the data separation circuit 26 as
Only when the pulse of the signal PDI ₀ is input to the phase comparator 21, a pulse is generated in the other input signal PDI _1, and so on. Therefore, the numbers of pulses of the signals PDI ₀ and PDI ₁ are the same. Here, these signals CP and DP are generated by the data separation circuit 26 so that the signal CP falls at the falling timing of the window signal WD and the signal DP falls at the rising timing of the window signal WD. Therefore, the falling timings of the signals CP and DP coincide with the inversion point of the window signal WD produced by the output of the voltage controlled oscillator 23. Since the phase comparator 21 compares the phases at the falling timings of the two inputs, it can be seen that the operation as the PLL circuit 2 is performed even when the switching signal SW = “1”. In Fig. 7, signal PD
It is a result of the above operation that I ₁ is drawn corresponding to the pulse of the signal PDI ₀ .

In FIG. 7, DT is a data signal, which is a signal resulting from capturing the signal DP at the rising timing of the window signal WD. Therefore, the data signal DT indicates a data string "00110100" in which one cycle of the window signal is one bit period. In this way, the data is extracted from the read data signal coming from the FDD.

(4) (i) Reading error in FIG. 7 In FIG. 7, the pulse A and the pulse B of the read data signal RDATA are in the direction of the arrow in the figure with respect to the position (the position drawn by the broken line) according to the above pulse interval Are shifting to the left and right. This is called peak shift, and it is a phenomenon that shifts to the left and right when reading when the interval between adjacent pulses is not equal to the pulse position when writing, which is unique to magnetic storage devices. is there. This causes the phases of the signals PDI ₀ and PDI ₁ to shift by Δt ₁ or Δt 2. In the case of FIG. 7, the data is read correctly in the data signal DT, but a read error may occur depending on the shift amount of the peak shift and the pulse width of the signal PDI ₀ determined by the signal generation circuit 1. is there.

(4) (ii) Explanation of reading error using FIGS. 8 and 9 FIGS. 8 and 9 are timing charts when the pulse of the reading data signal RDATA comes during the period of the window signal WD = “0”. In Fig. 8, t1 = t3 / 2, and in Fig. 9, t1 <
The case of t3 / 2 is shown.

Δt is the maximum value of the peak shift amount, and indicates that the pulse position of the read data signal RDATA may be shifted to the B or C position. The pulse position A is the center position and is the position determined by the pulse width t1.

In FIG. 8, since the signal DP indicating the data bit has "1" both at the position B and at the position C, no read error occurs.

In FIG. 9, when the pulse of the read data signal RDATA comes to the position C, the signal DP is not set and "0"
Since it remains as it is, a read error occurs. This occurs because the value of the pulse width t1 that determines the center value of the pulse of the read data signal RDATA is smaller than Δt. Conversely, when the value of the pulse width t1 is larger than (t3−Δt), the pulse at the B position of the read data signal RDATA deviates from the window signal WD = “0” area,
Similarly, it happens that the signal DP is not set. Therefore, if the pulse width t1 is set beyond the range of Δt <Δt1 <t3−Δt, a read error may occur. In particular, pulse width t1 = t3 / 2
When, the margin for error is the largest. Therefore, the signal generating circuit 1 is provided to provide a margin for a read error.

(Problems to be Solved by the Invention) However, the data demodulation circuit having the above configuration has the following problems.

In the conventional circuit, the factors that determine the pulse width t1 are the capacitor 12 and the variable resistor 13. Usually a variable resistor
By adjusting the resistance value of 13, t1 is adjusted to t3 / 2, but in reality there is an adjustment error, the adjustment position of the variable resistor 13 fluctuates, or the temperature of the capacitor capacity and resistance value changes. The pulse width t1 always includes an error with respect to t3 / 2 due to a change caused by the above. Therefore, the conventional circuit is
The margin for reading error from FDD is small,
Furthermore, there was a disadvantage in terms of man-hours of adjusting the variable resistor. Moreover, since the variable resistor is used, it cannot be completely on-chip on the IC.

Therefore, in order to solve such a problem, for example,
It is conceivable to apply the window pulse forming circuit technology disclosed in Japanese Utility Model Laid-Open No. 58-34458. In the technique of this document, the output signal of the voltage controlled oscillator 23 and the output pulse signal PDI ₀ of the signal generation circuit 1 are compared by a pulse width comparator, and a comparison signal of a level corresponding to the difference between the pulse widths of the two is output. To do. And
This comparison signal is supplied as a delay time control signal to the signal generation circuit 1 via the hold circuit, and the delay time of the signal generation circuit 1 is controlled.

The above-mentioned problems may be solved by using the technique of such a document. However, when generating the pulse signal PDI ₀ having a predetermined pulse width, it is difficult to accurately and repeatedly generate a pulse having the same width as the pulse width in the data area DA. Therefore, the reading margin of the data from the pulse signal (data pulse) DP may fluctuate, and accurate data demodulation may not be performed. Here, since it is difficult to always generate a pulse having the same width over a long period, the variation in the data reading margin is particularly remarkable when the data area DA is long.

SUMMARY OF THE INVENTION The present invention provides a data demodulation circuit that solves the problem that the above-mentioned conventional techniques have, that the reading margin of data varies and accurate data demodulation cannot be performed.

(Means for Meeting Problems) In order to solve the problems, the present invention generates, for example, a reference signal (PDI ₀ ) having a predetermined pulse width based on the first input signal (RDATA). A signal generation circuit, a phase comparator (21) for comparing the phases of the reference signal and the second input signal (PDI ₁ ) and outputting a corresponding comparison signal, and a signal from which high-frequency components of the comparison signal have been removed. A low-pass filter (22), a voltage-controlled oscillator (23) that outputs an oscillation signal having a frequency corresponding to the output signal of the low-pass filter, a bit pulse (CP) based on the oscillation signal and the reference signal, and A data separation circuit (26) for generating a data pulse (DP); and a multiplexer (25) for outputting one of the output pulse of the data separation circuit and the oscillation signal as the second input signal. Day The demodulation circuit, the signal generating circuit, a third input signal having a predetermined pulse width (a,) and the input signal generating circuit for generating a (54), the pulse width comparator circuit (52,53,58,59)
, A counter (55), and a pulse width regulation signal generation circuit (6
3, 64) and a reference signal generation circuit (50, 51).

Here, the pulse width comparison circuit (52, 53, 58, 59) compares the pulse width of the third input signal with the pulse width of the reference signal, and the pulse width of the reference signal is the third pulse width. It is a circuit that outputs the first level comparison signal (d of "0") when it matches the pulse width of the input signal, and outputs the second level comparison signal (d of "0") when it does not match. . A counter (55) updates the count value based on the third input signal while the second level comparison signal is being output, and counts while the first level comparison signal is being output. It is a circuit that holds a value. The pulse width defining signal generating circuit (63, 64) is a circuit for outputting the pulse width defining signal (i) at a time interval according to the count value of the counter. In addition, the reference signal generation circuit (50, 51) includes the second
While the level comparison signal is being output, the reference signal having a pulse width based on the pulse width defining signal and the third input signal is generated, and the first level comparison signal is being output. The interval is a circuit that generates the reference signal having a pulse width based on the pulse width defining signal and the first input signal.

(Operation) According to the present invention, since the data demodulation circuit is configured as described above, the input signal generation circuit generates the third input signal, and the third input signal is supplied to the pulse width comparison circuit, the counter, and the reference signal generation circuit. Given. In the pulse width comparison circuit,
The pulse width of the third input signal is compared with the pulse width of the reference signal generated by the reference signal generation circuit, and when the pulse width of the reference signal matches the pulse width of the third input signal, the first
A level comparison signal is output, and when they do not match, a second level comparison signal is output.

The counter updates the count value while the second level comparison signal is being output, and the counter holds the count value while the first level comparison signal is being output. The pulse width defining signal generating circuit outputs a pulse width defining signal corresponding to the count value of the counter and supplies it to the reference signal generating circuit. Then, the reference signal generation circuit generates a reference signal having a pulse width based on the pulse width defining signal and the third input signal while the second level comparison signal is being output, and compares the first level comparison signal. While the signal is being output, a reference signal having a pulse width is generated based on the pulse width defining signal and the first input signal, and these reference signals are given to the pulse width comparing circuit.

In this way, the pulse width of the window signal is defined based on the reference signal generated by the signal generation circuit, and the data is demodulated. Therefore, accurate data demodulation can be performed without fluctuation in the data reading margin. Therefore, the above problems can be eliminated.

(Embodiment) FIGS. 1 and 10 to 12 show configurations, operations, advantages, and modified examples (I) to (V) of the data demodulation circuit of the embodiment of the present invention.
Description will be made with reference to the drawings.

(I) Data demodulation circuit of FIG. 1 FIG. 1 is a block diagram showing the configuration of a data demodulation circuit showing an embodiment of the present invention. The same elements as those in the conventional FIG. 2 are designated by the same reference numerals.

This data demodulation circuit differs from the conventional one in that
A signal generation circuit having a different configuration in place of the signal generation circuit 1 in the figure
40 is provided. The signal generation circuit 40 adjusts the pulse width of the read data signal RDATA based on the clock signal CLKO and the trigger signal TRG provided from the control circuit 3 and outputs the signal PDI _0, which is output from the phase comparator 21 and the data separation circuit. It is a circuit to give to 26. The control circuit 3 is provided with, for example, eight output terminals 41 connected by eight signal lines.

The operation of the data demodulation circuit configured as above will be described.

Since the operation of the PLL circuit 2 is similar to the conventional one, the operation of the signal generating circuit 40 will be mainly described.

First, the trigger signal output from the control circuit 3
When TRG is input to the signal generation circuit 40, the signal generation circuit 4
At 0, the clock signal C given from the control circuit 3
The adjustment is performed so that the pulse width of the output signal PDI ₀ coincides with the time t10 corresponding to one cycle of LKO. When this operation is completed, the signal generation circuit 40 outputs a signal PDI ₀ having a pulse width of time t10 which is triggered by the pulse each time the pulse of the read data signal RDATA is input and which is initially adjusted. It is given to the phase comparator 21 and the data separation circuit 26.

The signal PDI ₀ is the input reference signal of the PLL circuit 2, and the pulse width t1 of the signal PDI _{0 in} FIGS. 6 and 7 has a value corresponding to the cycle t10 of the clock signal CLKO.

Here, in the control circuit 3, an oscillator such as a crystal oscillator having a high stability is used, the output signal thereof is divided to generate a clock signal CLKO, and the cycle t10 of the clock signal CLKO is set to a half cycle width of the window signal WD. If it is set to 1/2 of t3, the data demodulation operation can be performed in the state where the margin for the read error is the largest as shown in FIG. In addition, the control circuit 3 causes the trigger signal TR
If the timing of issuing G is just before the start of the reading operation, the pulse width of the signal PDI ₀ is adjusted to t ₀ each time the reading operation is performed, so that the pulse width is actually a factor of error such as temperature dependence and aging. The advantage is that you don't have to think about.

(II) Pulse width adjusting circuit in FIG. 10 FIG. 10 is a diagram showing an example of the circuit configuration of the signal generating circuit 40 in FIG.

The signal generation circuit 40 includes a multiplexer 50, D-type flip-flops (hereinafter, D-FF) 51 to 53, T-type flip-flops (hereinafter, T-FF) 54, and a down counter 5.
5, a delay circuit (DELAY) 56, AND circuits (hereinafter referred to as AND) 57 to 61, inverters 62 and 63, and a ladder circuit 64.

The multiplexer 50 is a circuit in which two input signals are switched by the output signal b of the D-FF52, and the output signal b is "0".
At the time of, the read data signal RDATA is input and is output as the signal e. When the output signal b is "1", the output signal a of the T-FF54 is input and is output as the signal e. To the clock input pin of D-FF51.

The D-FF51 has its data input terminal D connected to the power supply VDD, its reset input terminal R connected to the output side of the AND57, and its output terminal Q connected to the data input terminal D of D-FF52. In the D-FF51, when the reset input terminal R is "1", the signal f of "0" is output from the output terminal Q and is given to the D-FF52, and the reset input terminal R is "1" to "0". Then, when the reset input terminal R is "0", the signal level "1" of the data input terminal D at the rising timing of the input signal e to the clock input terminal is output to the output terminal Q.
If there is no rising signal inversion in the input signal e to the clock input terminal, the output terminal Q holds the current signal level. The multiplexer 50 and the D-FF 51 form a reference signal generation circuit.

The clock input terminal of the D-FF52 is connected to the output side of the AND58, the output terminal thereof is connected to the data input terminal D of the D-FF53, and the trigger signal TRG is input to the reset input terminal R thereof. This D-FF52 performs the same operation as the D-FF51, and outputs the signal b inverted from the output of the D-FF51 from its output terminal, and outputs it to the multiplexer 50,
Give to D-FF53 and AND59. The clock input terminal of D-FF53 is the output terminal Q of T-FF54, and its output terminal Q is AND5.
Each of them is connected to 9 and operates in the same manner as D-FF51 to output a signal C from an output terminal Q and give it to AND59. D
-FF52, 53 and AND58, 59 form a pulse width comparison circuit.

The output terminal Q of the T-FF54 is multiplexer 50 and D-.
It is connected to the FF53, its output terminals are connected to the input sides of the ANDs 58 and 61, respectively, and the clock signal CLKO is input to its clock input terminal and the trigger signal TRG is input to its reset input terminal R, respectively. This T-FF54 is a clock signal CLKO
The signal (third input signal) a of the output terminal Q, changes only at the falling timing of (3), and has a function of performing 1/2 frequency division operation, and constitutes an input signal generation circuit.

The clock input terminal of the down counter 55 is AND60.
Output terminals "1" to "4" on the output side of the ladder circuit
The trigger signal TRG is input to the set input terminal S thereof. This down counter 55
When the trigger signal TRG input to the set input terminal S is "1", the output terminals "1" to "4" are all set to "1"
When the trigger signal TRG is inverted from "1" to "0", the following down-count operation is performed at the rising timing of the signal j input to the clock input terminal. When the output terminal “1” is weighted with 1, “2” with 2, “3” with 4, and “4” with 8 weighting, the trigger signal TRG is changed from “1” to “0”.
, The values represented by the signal levels of the output terminals "1" to "4" are 15,14,13, ... 3,2,1,0, ... at each rising timing of the clock signal j. It changes in the order of 15,14,13 ....

The delay circuit 56 delays the signal f given from the output terminal Q of the D-FF 51 as it is for the time td, and outputs its output signal g.
It is a circuit given to AND57. The delay time td has a value of about 1/4 cycle of the clock signal CLKO.

The AND 57 takes a logical product of the output signal g of the delay circuit 56 and the output signal i of the inverter 63 and gives it to the D-FF 51 as a reset signal. The AND58 takes the logical product of the output signal of the AND59 (the comparison signal of the first and second levels) and the output signal of the T-FF54 and gives it as the clock signal of the D-FF52.
The AND 59 takes the logical product of the output signals b and c of the D-FFs 52 and 53 and gives the signal d to the ANDs 58 and 60. The AND 60 takes the logical product of the output signal d of the AND 59 and the output signal of the AND 61 and gives the signal j to the down counter 55 as a clock signal. AN
D61 is a circuit that takes the logical product of the output signal and the clock signal CLKO and gives it to the AND60.

The inverter 62 inverts the output signal f of the D-FF 51 and supplies it to the ladder circuit 64, and the inverter 63 inverts the signal h from the ladder circuit 64 and outputs its signal (pulse width defining signal) i.
It is a circuit given to AND57. The inverter 63 and the ladder circuit 64 constitute a pulse width defining signal generating circuit.

The ladder circuit 64 includes resistors R1 to R5 and a capacitor C1 connected in series between the power supply VDD and the ground, a switch circuit 65 connected in parallel to the capacitor C1, and a switch circuit 66 connected in parallel to each of the resistors R1 to R4. It consists of ~ 69 and.
The connection point between the capacitor C1 and the resistor R5 is on the input side of the inverter 63, the control input terminal of the switch circuit 65 is on the output side of the inverter 62, and the control input terminals of the switch circuits 66 to 69 are the output terminals of the down counter 55 ``. 1 ”to“ 4 ”, respectively. Each of the switch circuits 65 to 69 is in an off state when the output signal of the inverter 62 and the output signals k, l, m and n of the down counter 55 which are given to their control input terminals are “0”, in an off state and when they are “1”. Turns on. The resistance values of the resistors R1 to R4 have a relationship of R2 = 2.R1, R3 = 4.R1, R4 = 8.R1.

(III) Description of Operation of Circuit of FIG. 10 by FIG. 11 The operation of the signal generation circuit 40 of FIG. 10 will be described with reference to the timing chart of FIG.

In FIG. 11, t10 is the period of the clock signal CLKO, t11 to t15 are the pulse width of the signal f, td is the delay time of the delay circuit 56, VT in the signal h is the threshold voltage level of the inverter 63, and VDD is the power supply voltage. Each level is shown. The contents of the down counter 55 represent the numerical values shown by the four outputs as in the case where the above-mentioned weighting is applied, and .about. Indicate the sequence of operation timing.

First, when the pulse of the trigger signal TRG is input to the signal generation circuit 40, the pulse width adjustment mode is entered from that point.
The signal b is a signal indicating this mode. Upon entering this mode, multiplexer 50 signals PDI ₀ (ie, f).
The clock signal is output to the clock input terminal of D-FF51.
A signal a (that is, e) which is a 1/2 frequency-divided signal of CLKO is supplied.

Output signal f of D-FF51 at the rising timing of signal e
Is inverted from "0" to "1". At this time, since the content of the counter 55 is 15, all the switch circuits 66 to 69 are in the ON state. Therefore, as shown by the timing, the capacitor C1 after the switch circuit 65 is switched from on to off
The time constant of the falling voltage at the connection point signal h of the resistor R5 is C1.R5. The voltage level of signal h is inverter 63
Crossing the threshold voltage VT of, the output signal i of the inverter 63 is inverted from 0 to “1” at the timing, thereby resetting the D-FF 51, and at the timing, the signal f
Is inverted from "1" to "0". The pulse width t11 of the signal f at this time is expressed by the following equation.

t11 = K · C1 · R5 (1) Here, K is a proportional constant, which is ideally expressed by the following equation.

K = Ln (VDD / VT) (2) In order to compare the reference pulse width t10 and the pulse width t11 of the signal f, the signal f is sampled by the D-FF 52 at the timing corresponding to the falling edge of the signal a. Signal b of output terminal of D-FF52
Is “1”, t10 <t11, and when the signal b is “0”, t1
It is determined that 0 <t11. In this case, since t10> t11, the signal b remains "1" like the timing. When this judgment is over and the signal b remains "1",
A pulse is generated in the output signal j of the AND 60 like the timing, and the content of the down counter 55 changes from 15 to 14.
As a result, the switch circuit 66 is turned off.

Next, when the output signal e of the multiplexer 50 rises, the same operations as the above timings 1 to 3 are performed. D-FF in this case
The pulse width t12 of the output signal f of 51 is expressed by the following equation.

t12 = K · C1 · (R5 + R1) (3) The pulse width has increased from the previous pulse width t11 by K · C1 · R1. Even in this case, since t10> t12, the down counter 55 is further counted down, and the above timing
The operation of. The pulse width t13 of the signal f in this case is t13 = K.C1. (R5 + R2) = K.C1. (R5 + 2.R1) (4), which is increased by K.C1.R1 from the previous t12. .

From the above operation, if the operation from timing to is one step and the number of steps is N (1,2 ...), the pulse width t1N of the signal f at the Nth step is expressed by the following equation.

t1N = K · C1 · {R5 + (N−1) · R1} (5) That is, the pulse width t1N increases by K · C1 · R1 at each step, and when t10 <t1N is detected, it is different. In other words, when the signal b is inverted from "1" to "0" in the step, the pulse width adjustment mode is ended and the down counter 55
Indicates the count content at that time and the trigger signal again after that.
Hold the TRG pulse as it is input.

As a result of the above-mentioned operation, the pulse width t1N of the signal f has a value of t1N = t10 + (0 to K · C1 · R1) (6). FIG. 11 shows the case where N = 5.

When the pulse width adjustment mode ends and the signal b becomes "0",
The read data signal RDATA is output as it is by the multiplexer 50, and the signal RDATA becomes the clock signal e of the D-FF 51.
Pulse signal PDI _{0 with} pulse width t1N triggered by the rising edge of
Is output. That is, the pulse width of the signal PDI ₀ in FIGS. 1 and 10 is t10 + ( ₀ to K · C1 · R1). K ・ C1 ・ R1 is a negative factor of the margin for reading error, but if the number of bits of the down counter 55 is increased and the resolution of the adjustment resistors R1 to R4 is increased in Fig. 10, the value of K ・ C1 ・ R1 will be obtained. It can be made smaller.

(IV) Advantages of the Embodiment The advantages of this embodiment can be summarized as follows.

(IV) (i) When converting the read data signal RDATA from the FDD into a signal with a constant pulse width, the pulse width is automatically adjusted based on the stable cycle of the clock signal CLKO, and the adjustment operation is performed. Since the reading operation is performed every time the reading operation is started, the margin for the reading error at the time of data demodulation can be maximized.

For example, in the case of FDD, when 1 μsec is set as the pulse width t10, it is considered that there is no problem in terms of performance if K · C1 · R1 = 25 nsec.

To further explain, if the pulse of the pulse width adjustment trigger signal TRG is generated immediately before each reading operation and the pulse width adjustment mode is completed before the reading starts, FIG. C1, R1 ~ R in
It is not necessary to consider the temperature dependence of various factors that determine the pulse width of the signal PDI ₀ such as 5 and VT, or the change over time. For example, in the case of FDD, the above can be easily realized if the pulse of the trigger signal TRG is placed at the rising edge of the head load signal.

(IV) (ii) The pulse width of the signal PDI ₀ (that is, f) is controlled by the count value of the down counter 55 whose count value does not change unless a signal is externally applied. That is, the pulse width of the signal PDI ₀ is defined based on the count value held at the time when the width reaches the predetermined width (the latter half of the synchronization area SYNC), and therefore the data area DA
It can always be kept constant within. That is, it is possible to accurately and repeatedly generate pulses having the same width a plurality of times. As a result, the read margin of data from the pulse signal (data pulse) DP is always constant regardless of the length of the data area DA, and accurate data demodulation can be performed.

(V) Modifications The present invention is not limited to the illustrated embodiments, and various modifications are possible. For example, as the ladder circuit 64 in FIG.
A circuit configuration as shown in Fig. 12 can be adopted. The ladder circuit in Fig. 12 has five capacitors C11 connected in parallel.
To C15, a resistor R connected in series with these capacitors C11 to C15, a switch circuit 65 connected in parallel with this resistor R and switched by the output of the inverter 62 of FIG. 10, and connected in series with each of the capacitors C12 to C15. Down counter 55 shown in Fig. 10
Output signals k, l, m, and n, respectively, and switch circuits 66 to 69. By turning on or off each of the switch circuits 65 to 69 and changing the time constant, and by giving a signal h having a pulse width corresponding thereto to the inverter 63 in FIG. 10, the same operation and effect as in FIG. 10 can be obtained. .

In addition to this, using a ladder circuit with a configuration other than that shown in FIG. 12,
Alternatively, in addition to this ladder circuit, the signal generation circuit of FIG.
In 40, various modifications are possible, such as configuring the down counter 55 with another counter such as an up counter.

(Effect of the Invention) As described in detail above, according to the present invention, the signal generating circuit is configured by the input signal generating circuit, the pulse width comparing circuit, the counter, the pulse width defining signal generating circuit, and the reference signal generating circuit. Therefore, the pulse width of the reference signal is controlled by the count value of the counter whose count value does not change unless a signal is externally applied. In other words, the pulse width of the reference signal is defined based on the count value held at the time when the width reaches the predetermined width (the latter half of the synchronization area), so that it can always be kept constant in the data area. . That is, it is possible to accurately and repeatedly generate pulses having the same width a plurality of times. As a result, the read margin of data from the data pulse is always constant regardless of the length of the data area, and accurate data demodulation can be performed.

[Brief description of drawings]

1 is a block diagram of a data demodulation circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional data demodulation circuit, and FIG. 3 is a block diagram of read data signals and switching signals in FIG. , FIG. 4 and FIG. 5 are signal waveform diagrams for explaining the operation of FIG. 2, and FIG. 6, FIG. 7, FIG. 8 and FIG. 9 are timings for explaining the operation of FIG. Chart, FIG. 10 is a circuit diagram of the signal generating circuit in FIG.
FIG. 11 is a timing chart for explaining the operation of FIG. 10, and FIG. 12 is a circuit diagram of another ladder circuit in FIG. 1,40 ...... Signal generation circuit, 2 ...... PLL circuit, 3 ...... Control circuit, 21 ...... Phase comparator, 22 ...... Low pass filter (LPF), 23 ...... Voltage controlled oscillator (VCO), 24 ...... Frequency divider, 25,50 …… Multiplexer (MPX), 26 …… Data separation circuit, 27 …… OR circuit (OR), 51,52,53 …… D-FF, 54
…… T-FF, 55 …… Down counter, 58,59 …… And circuit (AND), 63 …… Inverter, 64 …… Ladder circuit, RDA
TA: read data signal, CLKO: clock signal, TR
G: Trigger signal.

Claims (1)

[Claims] 1. A signal generating circuit for generating a reference signal having a predetermined pulse width based on a first input signal, and comparing the phases of the reference signal and the second input signal with each other and outputting a comparison signal corresponding thereto. A phase comparator, a low-pass filter that outputs a signal from which the high-frequency component of the comparison signal has been removed, a voltage-controlled oscillator that outputs an oscillation signal of a frequency corresponding to the output signal of the low-pass filter, the oscillation signal and the reference A data separating circuit for generating a bit pulse and a data pulse based on a signal; and a multiplexer for outputting one of the output pulse of the data separating circuit and the oscillation signal as the second input signal, In the demodulation circuit, the signal generation circuit includes an input signal generation circuit that generates a third input signal having a predetermined pulse width, and the third input. Signal pulse width is compared with the pulse width of the reference signal, and when the pulse width of the reference signal matches the pulse width of the third input signal, a comparison signal of the first level is output and they do not match. A pulse width comparison circuit that sometimes outputs a second level comparison signal, and a count value is updated based on the third input signal while the second level comparison signal is being output, and the first level comparison circuit A counter that holds the count value while the signal is being output, a pulse width defining signal generating circuit that outputs a pulse width defining signal at a time interval according to the count value of the counter, and the second level comparison signal Is generated, the reference signal having a pulse width based on the pulse width defining signal and the third input signal is generated, and while the reference signal of the first level is being output, Pa In the reference signal generation circuit for generating the reference signal having a pulse width based scan width defining signal and to said first input signal, the data demodulation circuit which is characterized by being configured.