JPH1185462A - Data buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to surely take in data of a sort having a high data updating rate and send the data to a transfer destination as newest data, in a double buffer circuit for temporarily storing received data combining data and a label indicating the sort of the data in a double buffer as a pair, reading out stored data asynchronously with the received data and sending the read data to the transfer destination. SOLUTION: A label detection part 3 detects a label indicating the data sort of received data, a holding part 5 holds the detected label and a comparator 9 compares the detected label with all reference labels registered in a label registering PROM 8. When a buffer switching condition judging circuit 30 judges that the label at the time of coincidence is a previously set label (having a large updating rate), two buffer writing/reading states in the double buffer circuit 20 are controlled so as to be switched synchronously with a reference trigger (the initial timing of transmission data format operation in a data transfer destination 12) generated immediately after the judgement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data buffer circuit, and more particularly, to a method of receiving a plurality of sets of reception data, which are formatted as a set of a data part and a data type part indicating the type of the data part, and temporarily receive the data. More specifically, the present invention relates to a data buffer circuit which stores the received data and reads out the stored received data asynchronously with the received data.

[0002]

2. Description of the Related Art From an onboard sensor such as GPS or INS, an ARINC429 bus (AERO NAUTICAL RADI
O to temporarily capture various flight information data such as attitude, position, altitude, acceleration, etc. of the aircraft received via a bus conforming to the regulations of INCORPORATED, and format these data asynchronously. When performing data transfer, there is a double data buffer circuit of a system in which a so-called double buffer is used to alternately control writing and reading.

FIG. 6 schematically shows the data format of the ARINC429 bus. As shown in FIG.
The first to eighth bits are label bit portions indicating the data type of the data to be transmitted, and specify 256 types. Next ninth
And the tenth bit indicate a system number, and are used in the case of a multi-system.

Next, the 11th to 29th bits are data portions to be transmitted, and are called parameter bits. Furthermore,
The 30th and 31st bits are sign status bits into which bit information defined in advance is inserted. The last 32nd bit is a parity bit (odd parity).

The received data of such a data type is fetched by one buffer of the above-mentioned double data buffer circuit, and is transmitted while being asynchronously read from the other buffer.

For example, in a double data buffer circuit described in Japanese Patent Application Laid-Open No. 62-78933, received data is written into one buffer, and during this writing, another buffer is used for reading, and during this reading, Each time data reading from the buffer is completed, the memory (buffer) access control unit detects interruption of the received data and switches and controls the state of the buffer.

[0007]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. Sho 62-62
In the technique disclosed in Japanese Patent No. 78933, the state of the buffer is switched after the buffer on the reading side finishes reading all data. Such a method is applied only when one buffer takes in one packet of data from the transmission line and the other buffer reads out one packet of data written one cycle ago. Is possible, but
This is not applicable when the data input from the transmission path and the data read from the buffer and sent to the outside have the following relationships (1) and (2).

[0008] (1) When there is a large difference between the data transfer rate and one packet difference between the data input from the transmission line and the data read from the memory and transmitted to the outside; (2) The input data is as shown in the ARINC429 model. In the case where the update rates of the data contents are different from one another for each data type and the data of a specific data type (particularly, a data type having a large update rate) is desired to be the latest content as much as possible; Technology is difficult to apply.

In other words, the above-mentioned prior art employs a method in which the buffer on the data receiving side takes in one packet of data and then the buffer on the transmitting side sends out the data taken in one cycle before. When one packet length of reception is several times the format length of transmission, data update cannot be reflected on the transmission side.

Therefore, the present invention has been made to solve the problems of the prior art, and its purpose is to repeatedly update the contents of received data (the update rate is increased). An object of the present invention is to provide a data buffer circuit in which, when data exists, buffer switching control is performed in anticipation of the timing at which the data arrives, and updated data can be reliably transmitted to the transmission side.

[0011]

According to the present invention, a data section and a data type section indicating the type of the data section are combined into a set to receive a plurality of sets of reception data and temporarily receive the data. A data buffer circuit for reading out and sending out the stored reception data asynchronously with the reception data, wherein the first and second buffer means store a data portion of the reception data; Determining means for detecting the data type of the received data and determining whether or not the data type matches a preset data type;
And control means for reversely controlling the data write and read states of the buffer means.

[0012] The determination means includes reference data type storage means in which all the data types of the received data are stored in advance, data type detection means for detecting and temporarily storing the data type of the data type part, Means for comparing the data type detected by the data type detection means with all the reference data types stored in the reference data type storage means to determine the data type of the received data; Means for determining whether the data type is the preset data type.

[0013] The control means may control reading of data from the second buffer means during writing of data to the first buffer means in response to an external reference trigger signal. Wherein the control means responds to the coincidence of the judgment result by the judgment means, and the first and second signals are generated by the timing of the reference signal subsequently generated. The data write and read states of the buffer means are controlled in reverse.

The operation of the present invention will be described. Since the data type for which data content is frequently updated is known in advance,
This data type is set from the outside, and when data of the set data type is received, this is detected, and control is performed so as to reversely switch the write / read state of the buffer in response to the detection timing. In this case, instead of switching the buffer state immediately in synchronization with the detection timing, the buffer state is switched after the reference trigger of the transmission data format to be transmitted to the outside is generated, thereby reading out the buffer from which the latest update data is stored. It can be performed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, a data demodulation circuit 1 includes an ARINC 42
9 demodulates the received data and supplies a demodulated output to the label detection unit 3 and the data detection unit 4. The clock demodulation circuit 2 extracts a clock signal from the received data and supplies it to the label hold unit 5.

The label hold unit 5 temporarily stores a label indicating the data type of the received data detected by the label detection unit 3 in synchronization with a clock signal.

N (256) labels indicating all data types are registered in a label registration memory (PROM) 8 in advance. Each label is sequentially read out in accordance with an address by an address counter 7, and is sent to a comparator 9. Then, the received data is compared with the label of the received data held in the label holding unit 5.

The clock generator 6 generates a high-speed clock for generating addresses of the address counter 7 in ascending order and a shift clock for the shift register 10.

The shift register 10 has a label registration memory 8
The reference pulse read out in synchronization with the first (first) label is sequentially shifted in synchronization with the shift clock, and is an N-bit shifter. N AND gates 11 are provided corresponding to the N-bit outputs, respectively. The coincidence pulse from the comparator 9 is used as one common input, and the corresponding shift outputs are supplied to the other inputs.

Each output of these AND gates 11 is input to a buffer switching condition judging circuit 30, and these N
A buffer switching control signal is output in accordance with the state of each AND output and a condition set in advance inside this circuit.

The double buffer circuit 20 includes a data detecting section 4
In response to the reference trigger from the data transfer destination 12 while fetching the detected data, the fetched data is sequentially read out in synchronization with the data transfer request clock. Further, switching control is performed such that writing / reading of two buffers in the double buffer circuit 20 is alternately reversed by a buffer switching control signal.

Since the ARINC 429 received data contains data and a clock, these are demodulated by the data demodulation circuit 1 and the clock demodulation circuit 2, respectively.
That is, in the data demodulation circuit 1, the data portion of the received data is converted from the ARINC429 type to the normal digital format. In the clock demodulation circuit 2, the clock portion of the received data is demodulated and similarly converted into a digital format.

The demodulated data portion is divided into a label bit indicating the data type (see FIG. 6) and a data bit, and detected by the label detecting section 3 and the data detecting section 4, respectively.

As mentioned above, the data received from the ARINC429 data bus includes the attitude, position, altitude,
Information such as acceleration is included in one packet in the format shown in FIG. 6, and these are input in serial format at different update rates.

The label detected by the label detector 3 and the data detected by the data detector 4 are input to the double buffer circuit 20. FIG. 2 shows this double buffer circuit 2
It is a block diagram which shows the example of 0.

In FIG. 2, the detected label is input as an address of the label / buffer address conversion PROM 21 and is converted into an address corresponding to the label of the buffer 24 or 26 for writing data. As a result, all the data of each item label of the received data is written to each predetermined address in the buffer, and if not read, it is overwritten one after another. Data reading is performed in ascending order from the initial setting value of the address counter 27 in synchronization with a data transfer request clock from the data transfer destination 12.

The operation of the double buffer circuit will be described below. The detected data enters one data buffer 24 through the bus driver 22 and is supplied to the multiplexer 23.
Also, the output of the label / buffer address conversion PROM 21 is input to the data buffer 24. As a result, the detected data is sequentially written to the designated addresses on the data buffer 24.

When a buffer switching control signal is input to the present double buffer circuit, the flip-flop 25 latches the buffer switching control signal with a reference trigger indicating the starting point of the format operation of the destination, and then outputs the signal as a switching signal of the multiplexer 23. When this switching signal is input, the multiplexer 23 outputs the write address previously output to the data buffer 24 to the data buffer 26,
The read address generated by the address counter 27 is output to the data buffer 24 from the data transfer request clock. At this time, the bus driver 22 does not output the detection data to the data buffer 24, and the bus driver 2
8 outputs the detected data to the data buffer 26.

As described above, every time the switching control signal is input to the present double buffer circuit, the data buffer 24 and the data buffer 26 alternately repeat writing and reading, and the multiplexer 29 selects the buffer on the reading side. Send out.

Next, a method of generating a buffer switching control signal for controlling switching between two buffers will be described with reference to FIGS. The label detected by the label detection unit 3 is also held by the label hold 5 by the clock signal demodulated by the clock demodulation circuit 2 until the label of the next data item to be received is detected.

The clock generator 6 generates a clock signal having a period smaller than the time obtained by dividing the time during which a certain label is held by the total number N of reference labels, which will be described later, and outputs the clock signal to the address counter 7. Reference labels associated with all items included in the received data are registered in the label registration PROM 8, and are read out by the output of the address counter 7 which is incremented by the cycle of the clock signal from the clock generator 6, and are read by the comparator 9. Is compared with the sequentially held labels.

When a label match is detected, the comparator 9
Outputs a coincidence detection pulse to the AND gate 11. The shift register 10 has outputs for the number of data items and shifts the reference pulse output from the label registration PROM 8 in accordance with the clock signal from the clock generator 6 (see FIG. 3). The reference pulse is written at the same address as the label to be referred to first, and the reference label is written in accordance with a known reception order (known) in one packet of received data.

The AND gates 11 are prepared for the number N of data types in one packet, and output "1" from the position (1 to N) corresponding to the type at the timing when the coincidence detection pulse is output. This AND gate output is input to the buffer switching condition determination circuit 30.

FIG. 4 shows an example of the buffer switching condition determination circuit. The N signals output from the AND gate 11 enter the comparator 31 and are compared with the state set by the switch 32. Each of the switch elements 321 to 32N of the switch 32 has one-to-one correspondence with each of the input signals, and the position of the type (item) to be set as the switching condition is “ON”. The switch can be set to “ON” at a plurality of positions. In comparison 3, the buffer switching control signal is double-buffered when the item “1” among the N inputs coincides with the switch “ON” item. Output to the circuit 20. Thereby, ARINC42
The condition for switching the double buffer can be arbitrarily set for the nine received data, and the transfer corresponding to the data update can be performed.

FIG. 5 shows the relationship between the reference trigger generated from the data transfer destination 12 (see FIG. 1) and the ARINC 429 data, and the flip-flop 25 in the double buffer circuit 20.
2 shows the operation timing of the multiplexer 23 and the timing of the data format of the data transfer destination.

The reference trigger is a signal indicating the starting point of the format operation of the data transfer destination 12, and a buffer switching control signal is latched by the flip-flop 25 in synchronization with the reference trigger, and the multiplexer 23 is switched by the latch output. Is performed.

Therefore, when a label (item) which is selectively set in advance is detected by each of the switch elements 321 to 32N of the switch 32 of FIG. 4, the writing / writing of the buffers 24 and 26 is synchronized with the reference trigger immediately after that. Reading will be switched. As a result, the latest data of the detection label (item) is read out and transmitted in synchronization with the start point of the data format of the transfer destination.

[0039]

As described above, according to the present invention, a condition for switching the double buffer can be set for a desired data type in the data type to be updated, and therefore, a type having a large update rate can be set. However, there is an effect that the latest data can be transmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a double buffer circuit 20 of FIG. 1;

FIG. 3 is a timing chart showing a partial operation of the block in FIG. 1;

FIG. 4 is a diagram illustrating an example of a buffer switching condition determination circuit 30 of FIG. 1;

FIG. 5 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 6 is a diagram showing a format example of received data used in the present invention.

[Explanation of symbols]

 Reference Signs List 1 data demodulation circuit 2 clock demodulation circuit 3 label detection unit 4 data detection unit 5 label hold unit 6 clock generation unit 7 address counter 8 label registration PROM 9, 31 comparator 10 shift register 11 AND gate 12 data transfer destination 20 double buffer circuit 21 PROM for label / buffer address conversion 22, 28 Bus driver 23, 29 Multiplexer 24, 26 Data buffer 27 Address counter 28 Flip-flop 30 Buffer switching condition judgment circuit 32 Switch

Claims (5)

[Claims] A data part and a data type part indicating the type of the data part are received as a set and a plurality of sets of received data are received and temporarily stored, and are asynchronous with the received data. A data buffer circuit configured to read out the stored received data while transmitting the data, wherein first and second buffer means for storing a data portion of the received data; and detecting a data type of the received data. Determining means for determining whether the data type matches a preset data type; and responding to the determination result by reversing the data writing and reading states of the first and second buffer means. Control means for performing switching control on the data buffer circuit. 2. A reference data type storage unit in which all of the data types of the received data are stored in advance, a data type detection unit that detects the data type of the data type unit and temporarily stores the data type, Means for comparing the data type detected by the data type detection means with all the reference data types stored in the reference data type storage means to determine the data type of the received data; 2. The data buffer circuit according to claim 1, further comprising: means for determining whether the data type is the preset data type. 3. An external read clock in response to an external reference trigger signal for reading data from the second buffer means during data writing to the first buffer means. 3. The data buffer circuit according to claim 1, wherein the data buffer circuit is operated in synchronization with the data buffer. 4. The control means changes the data write and read states of the first and second buffer means in accordance with the timing of the reference signal generated subsequently in response to the coincidence of the judgment results by the judgment means. 4. The data buffer circuit according to claim 3, wherein switching control is performed on the contrary. 5. The data buffer circuit according to claim 1, wherein said control means controls reading of said buffer means so as to sequentially start from an initial setting address.