KR100474766B1 - Jitter reduction apparatus for synchronous digital network - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter elimination apparatus in a synchronous digital network. In the related art, in order to control the reading period of data in an elastic store, only the offset value of the writing address and the reading address is used. Jitter due to pointer justification is transferred to the analog PEL as it is, thereby increasing the jitter of the PDH signal and causing data errors. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, an elastic store for performing a function of a buffer for storing gap data on the SDH frame; A phase linear generator for extracting a phase of the most significant bit MSB of the write address of the elastic store and outputting a corresponding phase signal; A smooth read pattern generator for outputting information on a change in write address in accordance with pointer alignment; A phase cue for receiving a phase signal of the phase linear generator and a fluctuation information signal of the smooth read pattern generator and generating a reference phase signal for converting low-frequency large pointer alignment jitter to high-frequency small jitter; A phase comparator for extracting phases of the reference phase signal of the phase queue and phases of the read address signal of the elastic store, and then detecting phase differences between the phase queues and performing PLL lock state control according to the phase difference. ; Analog Pielello, which removes high frequency components of the signal input by the control signal of the phase comparator through a low pass filter, extracts only low frequency components, and varies the frequency of the voltage controlled oscillator (VCO) to maintain the Piel lock state. By providing the configured device, it is possible to provide high quality service by eliminating jitter, which is a data error inducing factor, and by configuring only the digital circuit, thereby making it possible to use a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). It is easy to implement, so it is possible to reduce costs.

Description

JITTER REDUCTION APPARATUS FOR SYNCHRONOUS DIGITAL NETWORK}

The present invention relates to a jitter rejection apparatus in a synchronous digital network, and more particularly, to remove jitter generated when extracting a Plesiochronous Digital Hierarchy (PDH) signal from a Synchronous Digital Hierarchy (SDH) network. The present invention relates to a jitter elimination device in a synchronous digital network which is eliminated using a phase queue technique.

Pointer justification in a synchronous digital layer (SDH) network is a synchronization method used by the digital multiplexer to time-synchronize between input and output signals. The bit rate of the output side exceeds the bit rate of the input side (the bit rate of the input side) Set the bit rate slightly higher than the head bit rate, select some of the bits in a specific pointer as the stuff bit, and fill the corresponding bit with the valid data according to the change of the bit rate on the input side. It is time-synchronized by performing alignment (POS.JUST) or by invalid data filling (negative justification (NEG.JUST)). At this time, jitter occurs due to the alignment of the pointer. The jitter refers to the deviation or displacement of some aspects of the wave in the high frequency digital signal. As the name implies, jitter is considered to be a wave shaking or shaking. Can be. Deviations can be in the form of magnitude, phase control, or width of a signal wave. Another definition of jitter may be referred to as the "period in which the signal frequency shifts from an ideal position." The causes of jitter may include electromagnetic interference and crosstalk with other signals. Jitter can cause the display monitor to flicker, affect the PC's processor's ability to do what it wants to do, click into the audio signal or cause other unwanted effects, or loss of data transmitted between network devices. It can be cause. The amount of acceptable jitter depends largely on the application.

1 is an exemplary view showing the configuration of a conventional independent synchronous digital layer signal transmission apparatus. As shown in FIG. 1, an independent synchronous digital layer (PDH) signal input from an SDH network is inputted to an SDH by an SDH path terminating device (not shown) before being input to the conventional independent synchronous digital layer signal transmitter. After removing all of the overhead and control data required by the network, only pure PDH data (WD [7: 0] & WEN) in a gap format is input and stored in an elastic store (10). . The data stored in the elastic store 10 is read from the elastic store 10 by a smooth read pattern generator 12, wherein the read pattern is a data of the data input to the elastic store 10. In the case of a burst pattern, in the case of read data, it is read as a smooth pattern having a uniform distribution of data for each time zone.

The smooth pattern reading generator 12 is controlled by a threshold level detector 11, and the threshold level detector 11 is a write address WAD [4: 0] and a read address RAD of the elastic store 10. [4: 0]) is compared to control the smooth read pattern generator 12 by comparing the offset value.

The data RD [7: 0] & REN read by the smooth read pattern generator 12 is stored in a PLL store 13 and then a phase comparator 14 and an analog PLL. The final PDH signal is recovered by (15) and then sent to the transmission network via coaxial cable or cable.

As described above, in the conventional technology, since the data read period is simply controlled in the elastic store in the conventional independent synchronous digital layer signal transmitting apparatus, only the offset value of the write address and the read address is used. The jitter from the pointer justification of is transferred to the analog PEL as it is, that is, the pointer justification jitter from the SDH network is transferred to the analog filter which is included in the PDH signal to recover it, thereby increasing the jitter in the PDH network. In the end, there was a problem that caused data errors.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an apparatus for removing jitter generated by extracting a PDH signal using a phase queue technique. have.

In order to achieve the above object, a configuration of a jitter removing apparatus in a synchronous digital network according to the present invention includes: an elastic store performing a function of a buffer for storing gap data on an SDH frame; A phase linear generator for extracting a phase of the most significant bit MSB of the write address of the elastic store and outputting a corresponding phase signal; A smooth read pattern generator for outputting information regarding a change in the write address in accordance with the pointer alignment; A phase cue for receiving a phase signal of the phase linear generator and a fluctuation information signal of the smooth read pattern generator and generating a reference phase signal for converting low-frequency large pointer alignment jitter to high-frequency small jitter; A phase comparator for extracting phases of the reference phase signal of the phase queue and phases of the read address signal of the elastic store, and then detecting phase differences between the phase queues and performing PLL lock state control according to the phase difference. ; Analog Pielello, which removes high frequency components of the signal input by the control signal of the phase comparator through a low pass filter, extracts only low frequency components, and varies the frequency of the voltage controlled oscillator (VCO) to maintain the Piel lock state. It is characterized by the configuration.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

2 is an exemplary view showing the configuration of a jitter removing apparatus in a synchronous digital network according to an embodiment of the present invention. As shown in Fig. 2, the elastic store 20 performs a function of a buffer for storing gap data on an SDH frame from the SDH network; A phase linear generator 22 for extracting a phase of the most significant bit MSB of the write address WAD [4: 0] of the elastic store 20 and outputting the extracted phase signal INI.PHASE; A smooth read pattern generator (21) for outputting information (LEAK [5: 0]) relating to a change in the write address (WAD [4: 0]) according to pointer alignment in the SDH network; Low-frequency large-point alignment jitter by receiving the phase signal INI.PHASE which is the output of the phase linear generator 22 and the fluctuation information LEAK [5: 0] signal which is the output of the smooth read pattern generator 21. A phase cue 23 for generating a reference phase signal REF.PHASE for converting the signal into small jitter at high frequencies; Phase difference between the phase of the reference phase signal REF.PHASE, which is the output of the phase queue 23, and the phase of the read address RAD [4: 0] signal, which is the output of the elastic store 20, are respectively extracted. A phase comparator 24 for detecting and controlling the analog PEL 25 according to the phase difference to maintain the PEL lock state; The high frequency component of the signal inputted by the control signal of the phase comparator 24 is removed through the low pass filter 26, and only the low frequency component is extracted to change the frequency of the voltage controlled oscillator (VCO) 27 so as to lock the PEL. It consists of the analog PEL 25 which maintains a state.

Referring to the accompanying drawings, the operation of an embodiment according to the present invention configured as described above will be described.

As shown in FIG. 2, the PDH signal input from the SDH network is required by the SDH path receiver (not shown) before being input into the jitter removing device in the synchronous digital network according to the embodiment of the present invention. After removing all overhead and control data, only the pure PDH data (WD [7: 0] & WEN & WCLK [6.48MHz]) of the gap format is inputted and stored in the elastic store 20.

Thereafter, when the write address WAD [4: 0] of the data stored in the elastic store 20 is transmitted to the phase linear generator 22, the phase linear generator 22 writes the write address of the elastic store 20. Extracts the most significant bit MSB of (WAD [4: 0]) to make a phase signal INI.PHASE for the extracted most significant bit MSB and outputs it to the phase cue 23, i.e., the phase cue ( 23 is a phase of the most significant bit MSB of the write address WAD [4: 0] having the information of the burst data according to the pointer alignment of the data stored in the elastic store 20. Signal (INI.PHASE).

Also, the smooth read pattern generator 21 receives a negative justification (NEG.JUST) and a positive justification (POS.JUST) signal and an SDH frame signal from the SDH network, and then writes a write address (WAD [] according to the corresponding pointer alignment. 4: 0]) to generate information (LEAK [5: 0]) relating to the fluctuation, that is, the fluctuation which is information according to the fluctuation by the pointer of the write address WAD [4: 0] of the elastic store 20. An information LEAK [5: 0] signal is generated and transmitted to the phase queue 23.

FIG. 3 is an exemplary view briefly showing the configuration of the phase queue shown in FIG. 2. As shown in FIG. 3, the phase signal INI.PHASE of the most significant bit MSB of the write address WAD [4: 0] of the elastic store 20 is aligned with the pointer alignment in the SDH network. In case of negative justification (NEG.JUST), the change of the corresponding phase signal (INI.PHASE) changes faster, and in case of positive justification (POS.JUST), the corresponding phase signal (INI.PHASE) Changes more slowly. Accordingly, the variation information LEAK [5: 0] signal having information according to the change of the phase signal INI.PHASE is stored in the SEL [5: 0] of the phase cue 23.

That is, the fluctuation information (LEAK [5: 0]) signal input from the smooth read pattern generator 21 designates a changed pointer of the phase signal INI. PHASE.

The 64: 1 multiplexer 31 outputs each of the outputs (phase signals PHASE (0) to PHASE (63) of the deflip-flop 30n as shown in FIG. 4 according to the information stored in the SEL [5: 0]). Select one of)) and apply it to the flip-flop 32 to be output as the reference phase signal REF.PHASE. In the case of the positive justification POS.JUST, the phase signal INI.PHASE changes. The point is moved from the center point of the de-flip flop 30n to the left de-flip flop, which slows the point of change of the reference phase signal REF.PHASE. That is, when the difference between the write address WAD [4: 0] and the read address RAD [4: 0] is changed, it is reflected in the reference phase signal REF.PHASE as it is. [5: 0] = 32). At this time, if the Z point moved according to the information stored in the SEL [5: 0] is applied to the deflip-flop 30n at a high phase PCLK [51.84MHz] so that the Z point moved to the center is sequentially moved to the center, The reference phase signal REF.PHASE modulates the change according to the pointer of the write address WAD [4: 0] to the change of the high frequency. That is, the reference phase signal REF.PHASE converts a large low frequency pointer jitter into a small high frequency jitter. As a result, the large low frequency pointer alignment jitter is converted into a small high frequency jitter.

The phase comparator 24 then compares the difference between the phase of the read address RAD [4: 0] signal and the phase of the reference phase signal REF.PHASE. In addition, the difference between the phases includes a high frequency component by the reference phase signal REF.PHASE, and the high frequency component is removed through the low pass filter 26 of the analog PEL 25.

As described above, the jitter elimination apparatus of the synchronous digital network of the present invention can provide high quality service by eliminating jitter which is a data error inducing factor, and by configuring only a digital circuit, a field programmable gate array (FPGA) ) And easy-to-use integrated circuits (ASICs) to reduce costs.

1 is an exemplary view showing the configuration of a conventional independent synchronous digital layer signal transmission apparatus.

2 is an exemplary view showing the configuration of a jitter removing device in a synchronous digital network of the present invention.

3 is an exemplary view briefly showing the configuration of the phase queue shown in FIG.

4 is a timing diagram of a phase queue applied to the present invention.

********** Explanation of symbols for the main parts of the drawing **********

10, 20: elastic store 11: threshold level detector

12, 21: Smooth reading pattern generator 13: PEL store

14, 24: phase comparators 15, 25: analog PEL

16, 26: low pass filter 17, 27: voltage controlled oscillator

22: phase linear generator 23: phase cue

Claims (2)

An elastic store for performing a function of a buffer for storing gap data on the SDH frame; A phase linear generator for extracting a phase of the most significant bit MSB of the write address of the elastic store and outputting a corresponding phase signal; A smooth read pattern generator for outputting information regarding a change in the write address in accordance with the pointer alignment; A phase cue for receiving a phase signal of the phase linear generator and a fluctuation information signal of the smooth read pattern generator and generating a reference phase signal for converting low-frequency large pointer alignment jitter to high-frequency small jitter; A phase comparator for extracting phases of the reference phase signal of the phase queue and phases of the read address signal of the elastic store, and then detecting phase differences between the phase queues and performing PLL lock state control according to the phase difference. ; Analog Pielello, which removes high frequency components of the signal input by the control signal of the phase comparator through a low pass filter, extracts only low frequency components, and varies the frequency of the voltage controlled oscillator (VCO) to maintain the Piel lock state. Jitter elimination device in a synchronous digital network, characterized in that the configuration. 2. The apparatus of claim 1, wherein the phase queues are connected in parallel to each other, and include a plurality of deflip-flops for receiving a phase signal of the phase linear generator and outputting in synchronization with a clock signal; A multiplexer for selecting and outputting one of the outputs of the plurality of deflip-flops according to the variation information of the smooth read pattern generator; And a flip-flop for receiving the output of the multiplexer and outputting the reference phase signal in synchronization with a clock signal.