JPS6130456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital transmission system in which an analog signal is sampled, encoded, and transmitted through a digital transmission path, and when the sampling clock frequency and the clock frequency of the transmission path are independent, The present invention relates to a synchronization device that synchronizes frequencies.

When converting an analog signal into a digital signal and transmitting it through a digital transmission line, the sampling clock frequency of the analog signal and the clock frequency of the digital transmission line may be determined independently. For example, in digital transmission of television signals, it is common practice to set the sampling clock frequency of the television signal to be synchronized to a unique synchronization signal of the television signal. Specifically, taking a color television signal as an example, this also applies when the sampling frequency is selected to be three or four times the subcarrier frequency. On the other hand, the transmission line clock frequency of the digital transmission line is often predetermined by the transmission system, and is generally unrelated to the synchronization frequency of the television signal. In this way, if the sampling clock frequency of the analog signal to be transmitted and the transmission line clock frequency are independent, an asynchronous clock can be generated by sending the digitally converted signal to the transmission line via a buffer memory. It is common to match frequencies. A buffer memory is also prepared on the receiving side for the same purpose, but the receiving sampling frequency must match the transmitting sampling frequency. If the transmission sampling frequency and the reception sampling frequency do not match, not only will it be impossible to faithfully reproduce the analog signal, but the reception buffer memory will overflow or underflow, making it impossible to reproduce the reception signal.

Stuffing has conventionally been performed in order to match the transmit sampling clock frequency with the asynchronous transmission line clock and to match the receive sampling clock frequency with that on the transmitting side. Stuffing compares the phase of the data frame on the transmission path and the pseudo data frame created by dividing the sampling clock.
The length of the data frame is changed so that the two match on average, and stuffing information is added to a part of the data frame. However, conventional stuffing requires a pseudo data frame close to the data frame of the transmission line, and therefore has the disadvantage that the transmission line clock frequency cannot be changed arbitrarily.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling frequency synchronization device that makes the sampling frequencies of transmission and reception coincide with any transmission line clock frequency.

That is, the present invention provides means for comparing the transmission sampling clock frequency _S and the transmission line clock frequency _l on the transmitting side and obtaining the relative relationship between _S and _l as relative information _ΔS , and storing _ΔS in a buffer memory along with other information. and a means for detecting relative information △ _S on the receiving side, comparing the received sampling clock frequency _R and the transmission line clock frequency _l , and determining the relative relationship between _R and _l as relative information. △
This is a sampling frequency synchronization device comprising means for obtaining _R , and means for controlling the received sampling frequency _R so that _ΔS and _ΔR match.

According to the present invention, since the information for synchronizing the sampling frequency of transmission and reception is transmitted regardless of the data frame on the transmission path, the sampling frequency can be synchronized with any transmission path clock frequency. , applicable to a wide range of digital transmission systems.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, the analog signal to be transmitted is applied to input terminal 1, and the analog/digital (A/D)
The converter 2 converts it into a digital signal. In the present invention, the analog signal to be transmitted can be any arbitrary signal, including a television signal, an audio signal, or a facsimile signal, but a television signal will be explained below as an example.

Reference numeral 3 is a sampling clock generator, and when it is necessary to maintain a constant relationship between the synchronization frequency of the input television signal and the sampling clock frequency _S , a voltage controlled oscillator (VCO) is used, independent of the input signal. If specified, a simple oscillator is used.

The A/D converted television signal is further converted into an appropriate code by being transmitted by an encoder 4.
Relative information △ as other information in multiplexer 6
The signal is multiplexed with _S and written into the buffer memory 7, speed-matched, and sent out to the transmission line 10 through the modulator 8. In the case of television signals, the encoder 4 uses an intraframe encoder, an interframe encoder, a _ΔM encoder, etc., but PCM obtained by A/D conversion without using an encoder
(Pulse code modulation) signals may be transmitted as they are. In any case, since this part has no direct relation to the present invention, further explanation will be omitted.

Transmission line clock φ _l generated internally by modulator 8
is also used as a data read clock for buffer memory 7, and is also input to comparator 5, where it is used for frequency comparison with transmission sampling clock _φS .

FIG. 2 is a block diagram showing an example of a specific configuration of the comparator 5. As shown in FIG.

Transmission sampling clock φ _S is divided by frequency divider 21 to 1/N.
A divided pulse φ _N having a period of N/ _S is generated, and φ _N is connected to the clear terminal of the counter 22 and the clock terminal of the register 23 . Connect the transmission line clock φ _l to the clock terminal of the counter 22,
Count the number of transmission line clocks included in the period N/ _S . If this count value is taken into the register 23 by the frequency division pulse φ _N , the sampling clock frequency will be output.
Relative information _ΔS indicating the relative relationship of _l is obtained. That is, the relative information _ΔS in this case is given by _ΔS = N· _l / _S (1). Note that the frequency division number N is an integer, but
If _S /N is selected to match the frame frequency or line frequency of the input television signal, _ΔS is generated every time the television signal is synchronized, making it easy to multiplex the television signal _ΔS with the multiplexer 6.

Next, referring to FIG. 1, the operation on the receiving side will be explained.

The signal sent through the transmission path 10 is demodulated by a demodulator 18, and the demodulated data is sent via a buffer memory 17 to a demultiplexer 16 where it is separated into a television signal and relative phase information _ΔS . The television signal is converted into the original PCM signal by a decoder 14, which operates in the opposite manner to the encoder 4, and converted into an analog signal by a digital/analog (D/A) modulator 12, which is taken out at an output terminal 11. .

Reference numeral 13 is a sampling clock generator for generating a reception sampling clock φ _R , and a pressure controlled oscillator (VCO) whose oscillation frequency can be controlled is used.

The transmission line clock φ _l reproduced by the demodulator 18 is used for writing data into the buffer memory 17, and is also input to the comparator 15 and used for frequency comparison with the reception sampling clock φ _R.

The configuration of the comparator 15 is exactly the same as the configuration on the transmitting side shown in FIG. Therefore, the relative information _ΔR taken out at the output of the comparator 15 is _ΔR =N· _l / _R (2).

_ΔS separated by the demultiplexer 16 and _ΔR obtained by the comparator 15 are subtracted by a subtracter 19, and the difference Δ is taken out as an output. The difference Δ is integrated by the digital integrator 20 and converted into the control voltage V of the VCO 13 by the D/A converter 30. The difference △ is △=△ _R − △ _S = N _l / _SR ( _S − _R ) (3), and _the control voltage V is V = V △ + k∫ ( _S − _R ) dt (4) where, k is a constant.

If the receive sample clock frequency _R is _S when the VCO control voltage is V _O , then when _R tries to become larger than _S , the control voltage that makes V < V _O is added and this is prevented, and conversely, when _R becomes smaller than _S If an attempt is made to do so, a control voltage such that V>V _O is applied and this is prevented, so that control is performed so that _R = _S at all times.

If the accuracy of the transmission sampling clock frequency is high to some extent, the comparator shown in FIG. 2 can be simplified, so this will be described as a second embodiment.

In Fig. 2, the frequency of φ _N (= _S /N) is selected to be, for example, the television frame frequency, that is, 30 Hz, and the transmission line clock frequency _l is set to 30 M.
When set to Hz, △ _S becomes △ _S = 30 × 10 ⁶ /30 = 10 ⁶ , and counter 22 and register 2 in Fig. 2
The required number of bits for 3 is 20 bits, which increases the circuit scale.

However, if the transmission sampling frequency _S is limited to the range _O (1-δ) < _S < _O (1 + δ) (5), then △ _S becomes N _l / _O (1 + δ) < △ _S < N _l / _O (1
−δ)(6).

In this case, the variable range of the reception sampling clock frequency can be limited to the range _O (1-δ) < _R < _O (1+δ) (7), so △ _R is also N _l / _O (1+δ) <△ _R <N _l / _O (1
−δ)(8).

The range of information △ used for VCO control on the receiving side is -2N _l δ/ _O (1-δ ² )<△<2N _l δ from equations (6) and (8).
/ _O (1-δ ₂ )(9). For example, if the accuracy δ of the transmit sampling frequency is 10 ^-5
In the case of , if we calculate the numerical value of equation (9), we get -20<△<+20 (10). Therefore, the number of bits in the counter and register used in the comparator is reduced to 6 bits, and the 6-bit remainder value of △ _S is transmitted as △' _S , and the receiving side also transmits △ _R.
Find the 6-bit remainder value as △′ _R and calculate △′ _R −△′ _S
Correct control can be performed even if calculations are performed. However, the calculation of △′ _R −△′ _S is |△′ _R −△′ _S ｜<32, △=△′ _R −△′ _S , and when △′R−△′ _S ≧32, △= When △′ _R −△′ _S −64, △′ _R −△′ _S ≦−32, calculate as △=△′ _R −△′ _S +64. Generally｜△
When limited to |<n, 2 ^k >2n (11). The k-bit remainder value can be calculated for _ΔS and _ΔR . That is, in this embodiment, the second
The number of bits in the counter 22 and register 23 in the comparator shown in the figure is reduced to k bits, and the reception sampling frequency is controlled using k bits of relative information △' _S and △' _R. It not only simplifies the process, but also reduces the number of bits of relative information to be transmitted. Note that the subtracter indicated by reference numeral 19 in FIG. 1 may also be performed for k bits.

The present invention is characterized in that information for synchronizing the sampling clock frequency is transmitted regardless of the data frame on the transmission path. Therefore, the present invention can be easily applied to the case where multiple channels of television signals are multiplexed by time-divisionally using one transmission path. In other words, even if the sampling clock frequency is different for each channel,
Since the relative information _ΔS is sent together with the data for each channel, it is possible to synchronize the sampling frequencies of transmission and reception, respectively, on the receiving side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the sampling frequency synchronization device of the present invention, and FIG. 2 is a block diagram showing an example of a specific configuration of a comparator designated by numeral 5 in FIG. In the figure, 2...A/D converter, 3...Sampling clock generator, 4...Encoder, 5...Comparator, 6...Multiplexer, 7...Transmission buffer memory, 8... Modulator, 12... D/A converter, 13... Sampling clock generator, 14...
Decoder, 15... Comparator, 16... Demultiplexer, 17... Reception buffer memory, 18
... demodulator, 19 ... subtractor, 20 ... digital integrator, 30 ... D/A converter.

Claims (1)

[Scope of Claims] 1. In a synchronizer that synchronizes the sampling clock frequency of transmission and reception in a digital transmission system in which the sampling clock frequency of an analog signal to be transmitted and the clock frequency of a transmission path are independent, a first comparison means that compares the clock frequency _S and the transmission line clock frequency _l and obtains the relative relationship between _{S and l} as relative information _ΔS ; a second means for detecting relative information _ΔS on the receiving side; and a second means for comparing the received sample clock frequency _R and the transmission line clock frequency _l to obtain the relative relationship between _R and _l as the relative information _ΔR . 1. A sampling frequency synchronization device comprising a comparison means and a means for controlling a received sampling frequency _R so that relative information _ΔS and _ΔR match. 2. The first comparison means includes a frequency divider that divides the frequency of the transmission sampling clock signal by 1/N (N is an integer), counts the transmission line clock signal, and clears the frequency using the output signal of the frequency divider. 2. The sampling frequency synchronization device according to claim 1, further comprising: a counter that receives the output signal of the counter according to the output signal of the frequency divider and outputs the output signal as relative information.