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KR970052925A - High heat-resistant metal wiring structure of semiconductor device and method of forming the same - Google Patents
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KR970052925A - High heat-resistant metal wiring structure of semiconductor device and method of forming the same - Google Patents

High heat-resistant metal wiring structure of semiconductor device and method of forming the same Download PDF

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KR970052925A
KR970052925A KR1019950047455A KR19950047455A KR970052925A KR 970052925 A KR970052925 A KR 970052925A KR 1019950047455 A KR1019950047455 A KR 1019950047455A KR 19950047455 A KR19950047455 A KR 19950047455A KR 970052925 A KR970052925 A KR 970052925A
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layer
melting point
high melting
conductive layer
point metal
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KR0175030B1 (en
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고광만
이상인
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김광호
삼성전자 주식회사
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Priority to JP8337495A priority patent/JPH09199594A/en
Priority to US08/760,594 priority patent/US6156644A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H10D64/01125—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides the silicides being formed by chemical reaction with the semiconductor after the contact hole formation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

고내열 금속 배선 구조를 형성하는 방법 및 그 배선 구조에 대하여 기재되어 있다. 먼저, 반도체 소자의 활성 영역이 형성된 실리콘이 포함된 하부 도전층에 층간 절연층을 형성한 후, 층간 절연층을 부분적으로 제거하여 실리콘이 포함된 하부 도전층을 일부분 노출시키는 접촉 개구부를 형성한다. 이후, 그 결과물의 전면상에 고융점 금속 화합물로 이루어진 반응 조절층 및 고융점 금속으로 이루어진 반응 금속층을 순차적으로 적층거나 동일 장비에서 연속적으로 중착한 후, 열처리 공정을 진행하여 상기 접촉 개구부 저면의 실리콘이 포함된 하부 도전층 상에 오믹층(Ohmic Layer)을 형성한다. 반응 금속층만 또는 반응 금속층 및 반응 조절층을 제거하고, 여기에 고융점 물질로 각각 이루어진 확산 방지층 및 상부 도전층을 순차적으로 적층함으로써 고내열 금속 배선 구조로 형성할 수 있다. 반응 조절층은 후속되는 열처리 공정이 진행되는 동안, 예컨대 티타늄 실리사이드로 이루어진 오믹층(Ohmic Layer)이 균일하게 형성되도록 함으로써, 반도체 소자의 전기적 특성을 개선하고 더 나아가 반도체 소자의 집적화에 기여할 수 있는 효과가 있다.A method of forming a high heat resistant metal wiring structure and a wiring structure thereof are described. First, an interlayer insulating layer is formed on a lower conductive layer including silicon in which an active region of a semiconductor device is formed, and then a contact opening is formed to partially expose the lower conductive layer containing silicon by partially removing the interlayer insulating layer. Thereafter, a reaction control layer made of a high melting point metal compound and a reaction metal layer made of a high melting point metal are sequentially laminated or successively deposited in the same equipment on the front surface of the resultant, and then a heat treatment process is performed to obtain silicon on the bottom surface of the contact opening. An ohmic layer is formed on the included lower conductive layer. It is possible to form a high heat-resistant metal wiring structure by removing only the reactive metal layer or the reactive metal layer and the reaction control layer, and sequentially laminating a diffusion barrier layer and an upper conductive layer each made of a high melting point material. During the subsequent heat treatment process, the reaction control layer may uniformly form an ohmic layer made of titanium silicide, thereby improving the electrical characteristics of the semiconductor device and further contributing to the integration of the semiconductor device. There is.

Description

반도체 소자의 고내열 금속 배선 구조 및 그 형성 방법.A high heat resistant metal wiring structure of a semiconductor device and a method of forming the same.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 일 실시예를 순차적으로 설명하기 위하여 도시한 단면도들이다.5 is a cross-sectional view for sequentially explaining an embodiment of the present invention.

Claims (26)

반도체 소자의 금속 배선 형성 방법에 있어서, 실리콘 원소를 포함하는 하부 도전층 상에 층간 절연층을 형성하는 제1단계; 상기 층간 절연층을 부분적으로 제거하여 상기 하부 도전층의 일부를 노출시키는 접촉 개부를 형성하는 제2단계; 상기 접촉 개구부에 의하여 노출된 상기 하부 도전층 상에 반응 조절층 및 반응 금속층을 순차적으로 형성하는 제3단계; 상기 반응 조절층 및 반응 금속층이 형성되어 있는 결과물에 열처리를 함으로써 상기 접촉 개구부 저면의 상기 하부 도전층 상에 오믹층(Ohmic Layer)을 형성하는 제4단계; 상기 반응 금속층을 제거하는 제5단계 및 결과물 전면 상에 상부 도전층을 형성하는 제6단계를 포함하는 반도체 소자의 고내열 금속 배선 형성 방법.CLAIMS What is claimed is: 1. A method of forming metal wirings for semiconductor devices, comprising: a first step of forming an interlayer insulating layer on a lower conductive layer containing a silicon element; Partially removing the interlayer insulating layer to form a contact opening exposing a portion of the lower conductive layer; A third step of sequentially forming a reaction control layer and a reaction metal layer on the lower conductive layer exposed by the contact opening; A fourth step of forming an ohmic layer on the lower conductive layer on the bottom of the contact opening by heat-treating the resultant on which the reaction control layer and the reaction metal layer are formed; And a fifth step of removing the reactive metal layer and a sixth step of forming an upper conductive layer on the entire surface of the resultant metal layer. 제1항에 있어서, 상기 실리콘 원소를 포함하는 하부 도전층은 실리콘 기판 또는 고융점 금속 실리사이드인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the lower conductive layer including the silicon element is a silicon substrate or a high melting point metal silicide. 제1항에 있어서, 상기 반응 금속층 및 상부 도전층은 고융점 금속으로 형성하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the reactive metal layer and the upper conductive layer are formed of a high melting point metal. 제3항에 있어서, 상기 고융점 금속은 티타늄(Ti), 코발트(Co), 텅스텐(W), 몰리브덴(Mo), 탄탈륨(Ta) 및 지르코늄(Zr)군 중 어느 하나인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The semiconductor of claim 3, wherein the high melting point metal is any one of titanium (Ti), cobalt (Co), tungsten (W), molybdenum (Mo), tantalum (Ta), and zirconium (Zr). A method for forming high heat resistant metal wiring of an element. 제1항에 있어서, 상기 반응 조절층 및 상부 도전층은 고융점 금속을 공기에 노출시키지 않고 동일 장비에서 연속적으로 진행하여 형성하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the reaction control layer and the upper conductive layer are formed by continuously proceeding the same equipment without exposing the high melting point metal to air. 제1항에 있어서, 상기 반응 조절층 및 상부 도전층은 고융점 금속 화합물로 형성하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the reaction control layer and the upper conductive layer are formed of a high melting point metal compound. 제6항에 있어서, 상기 고융점 금속 화합물은 질화 티타늄(TiN), 질화 텅스텐(WN), 질화 탄탈륨(TaN), 질화지르코늄(ZrN)등과 같은 고융점 금속 질화물 중 어느 하나인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The semiconductor of claim 6, wherein the high melting point metal compound is any one of a high melting point metal nitride such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), zirconium nitride (ZrN), or the like. A method for forming high heat resistant metal wiring of an element. 제6항에 있어서, 상기 고융점 금속 화합물은 탄화 티타늄(TiC), 탄화 텅스텐(WC), 탄화 탄탈륨(TaC), 및 탄화 지르코늄(ZrC)등과 같은 고융점 금속 탄화물 중 어느 하나인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 6, wherein the high melting point metal compound is any one of a high melting point metal carbide, such as titanium carbide (TiC), tungsten carbide (WC), tantalum carbide (TaC), zirconium carbide (ZrC) and the like. A method for forming a high heat resistant metal wiring of a semiconductor device. 제1항에 있어서, 상기 반응 조절층은 상기 반응 금속층보다 상대적으로 얇게 형성하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the reaction control layer is formed relatively thinner than the reaction metal layer. 제1항에 있어서, 상기 제4단계의 열처리 공정은 불활성 가스 분위기 및 산화 방지 분위기 중 어느 하나의 분위기에서 진행하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the heat treatment process of the fourth step is performed in one of an inert gas atmosphere and an anti-oxidation atmosphere. 제1항에 있어서, 상기 제4단계의 열처리 공정은 600℃ 및 800℃ 중 어느 하나의 온도 조건의 RTA(Rapid Thermal Annealing) 공정으로 진행하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, wherein the heat treatment process of the fourth step is performed by a rapid thermal annealing (RTA) process at any one of 600 ° C. and 800 ° C. 2. 제1항에 있어서, 상기 제5단계 이후에 노출된 결과물의 전면 상에 확산 방지층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, further comprising forming a diffusion barrier layer on the entire surface of the resultant product exposed after the fifth step. 제1항에 있어서, 상기 제5단계 이후에 상기 반응 조절층을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of claim 1, further comprising removing the reaction control layer after the fifth step. 제13항에 있어서, 상기 반응 조절층을 제거하는 단계 이후에 상기 결과물의 전면 상에 확산 방지층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.15. The method of claim 13, further comprising forming a diffusion barrier layer on the entire surface of the resultant after removing the reaction control layer. 제12항 및 제14항 중 어느 하나의 항에 있어서, 상기 확산 방지층을 형성하는 단계 전에 결과물의 표면을 세척하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.15. The method of claim 12 or 14, further comprising the step of cleaning the surface of the resultant prior to forming the diffusion barrier layer. 제12항 및 제14항 중 어느 하나의 항에 있어서, 상기 확산 방지층은 고융점 금속 화합물로 형성되는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 형성 방법.The method of forming a high heat-resistant metal wiring of a semiconductor device according to any one of claims 12 to 14, wherein the diffusion barrier layer is formed of a high melting point metal compound. 반도체 소자의 금속 배선 구조에 있어서, 실리콘 원소를 함유하는 하부 도전층; 상기 하부 도전층을 부분적으로 노출시키는 접촉 개구부를 갖는 층간 절연층; 상기 접촉 개구부에 의해 노출된 상기 하부 도전층상에 형성된 오믹층(Ohmic Layer); 상기 층간 절연층 외면 상에 형성된 반응 조절층; 상기 반응 조절층 및 오믹층(Ohmic Layer) 상에 형성된 상부 도전층을 구비하는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.A metal wiring structure of a semiconductor device, comprising: a lower conductive layer containing a silicon element; An interlayer insulating layer having a contact opening that partially exposes the lower conductive layer; An ohmic layer formed on the lower conductive layer exposed by the contact opening; A reaction control layer formed on an outer surface of the interlayer insulating layer; And a top conductive layer formed on the reaction control layer and the ohmic layer. 제17항에 있어서, 상기 실리콘 원소를 포함하는 하부 도전층은 실리콘 기판 또는 고융점 금속 실리사이드인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.18. The high heat resistant metal wiring structure of a semiconductor device according to claim 17, wherein the lower conductive layer containing silicon element is a silicon substrate or a high melting point metal silicide. 제17항에 있어서, 상기 오믹층(Ohmic Layer)은 준안정상(C-49) 및 안정상 (C-54)의 실리사이드중 어느 하나의 실리사이드로 이루어진 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.18. The structure of claim 17, wherein the ohmic layer comprises one of a silicide of a metastable phase (C-49) and a silicide of a stable phase (C-54). . 제17항에 있어서, 상기 상부 도전층을 구성하는 고융점 금속으로 형성된 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.18. The high heat-resistant metal wiring structure of a semiconductor device according to claim 17, wherein the high-melting-point metal constituting the upper conductive layer is formed. 제20항에 있어서, 상기 고융점 금속은 티타늄(Ti), 코발트(Co), 텅스텐(W), 몰리브덴(Mo), 탄탈륨(Ta) 및 지르코늄(Zr)군 중 어느 하나인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.The semiconductor of claim 20, wherein the high melting point metal is any one of titanium (Ti), cobalt (Co), tungsten (W), molybdenum (Mo), tantalum (Ta), and zirconium (Zr). High heat-resistant metal wiring structure of the device. 제17항에 있어서, 상기 반응 조절층 및 상부 도전층은 고융점 금속 화합물로 형성된 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.18. The structure of claim 17, wherein the reaction control layer and the upper conductive layer are formed of a high melting point metal compound. 제22항에 있어서, 상기 고융점 금속 화합물은 질화 티타늄(TiN), 질화 텅스텐(WN), 질화 탄탈륨(TaN), 질화지르코늄(ZrN) 등과 같은 고융점 금속 질화물 중 어느 하나인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.The semiconductor of claim 22, wherein the high melting point metal compound is any one of a high melting point metal nitride such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), zirconium nitride (ZrN), or the like. High heat-resistant metal wiring structure of the device. 제22항에 있어서, 상기 고융점 금속 화합물은 탄화 티타늄(TiC), 탄화 텅스텐(WC), 탄화 탄탈륨(TaC), 및 탄화 지르코늄(ZrC) 등과 같은 고융점 금속 탄화물 중 어느 하나인 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.The method of claim 22, wherein the high melting point metal compound is any one of a high melting point metal carbide, such as titanium carbide (TiC), tungsten carbide (WC), tantalum carbide (TaC), zirconium carbide (ZrC) and the like. High heat-resistant metal wiring structure of semiconductor device. 제17항에 있어서, 상기 반응 조절층 및 오믹층(Ohmic Layer)의 외면과 상기 상부 도전층 사이에 확산 방지층이 더 구비되어 있는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.18. The structure of claim 17, wherein a diffusion barrier layer is further provided between an outer surface of the reaction control layer and the ohmic layer and the upper conductive layer. 제25항에 있어서, 상기 확산 방지층은 고융점 금속 화합물로 형성되는 것을 특징으로 하는 반도체 소자의 고내열 금속 배선 구조.The high heat resistant metal wiring structure of a semiconductor device according to claim 25, wherein the diffusion barrier layer is formed of a high melting point metal compound. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047455A 1995-12-07 1995-12-07 High heat-resistant metal wiring structure of semiconductor device and method of forming the same Expired - Fee Related KR0175030B1 (en)

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