JP2536622B2 - Interrupt control method - Google Patents

Description

The present invention relates to an interrupt control method for notifying each I / O of an interrupt cycle of a CPU in response to an interrupt request from a plurality of I / Os.

[Prior Art] Two methods are conventionally known to notify the interrupt cycle of the CPU in response to interrupt requests from a plurality of I / Os.

The first method is a method in which each I / O independently outputs an interrupt request signal and the CPU side outputs an acknowledge signal to each I / O in response to each interrupt request signal. This first method is the third
Shown in the figure.

In response to interrupt request signals 1, 2, and 3 from I / O-1, I / O-2, and I / O-n shown in FIG. 3, interrupt acknowledge signals 4, 5, and 6 are output from the CPU, respectively. Output to each corresponding I / O.

In addition, the second method of notifying the interrupt cycle of the CPU to interrupt requests from multiple I / Os is to use a common interrupt request signal for each I / O, This is a method of outputting an interrupt acknowledge signal, and each I / O is connected in a daisy chain. This second method is shown in FIG.

For the interrupt request signal 7 from I / O-1, I / O-2 and I / O-n, an interrupt acknowledge signal from the CPU to the first I / O (here I / O-1) 8 is output. If the I / O-1 itself does not send an interrupt request signal, the lower I / O-
An interrupt acknowledge signal relay output 9 is output to 2. I / O
-2 outputs the interrupt request signal, the I / O-2 acquires the CPU interrupt cycle without outputting the interrupt acknowledge signal relay output 10 to the lower I / O-n. To do.

In the second method shown in FIG. 4, for example, when I / O-1 is removed, the interrupt acknowledge signal 8 from the CPU causes I / O-
Since it will be interrupted at 1, means for relaying the interrupt acknowledge signal 8 to the interrupt acknowledge signal relay output 9 is required.

[Problems to be Solved by the Invention] The above-mentioned first method has a drawback that wiring is complicated because each I / O needs to be individually connected to the CPU side.

In the second method, since the interrupt acknowledge signals between I / Os are connected in a daisy chain, I / Os in the middle
There is a drawback that a means for relaying an interrupt acknowledge signal is required when O is removed.

[Means for Solving the Problems] The present invention has been made in view of the above problems.
The purpose is to connect I / Os with a common signal, and to eliminate the need for special signal relaying means even if I / Os on the way are removed.

In order to achieve this object, the interrupt control method according to the present invention transmits an interrupt request signal to the CPU as active when there is an interrupt request from at least one of a plurality of I / Os, and outputs from the CPU. It activates the interrupt acknowledge signal that indicates the CPU interrupt cycle, and outputs the timing signal in synchronization with this interrupt acknowledge signal.
Each I / O checks the presence or absence of an interrupt request in the time slot of the timing signal corresponding to its own address in the order of address, and outputs the interrupt request by itself, and the CP
It is configured to acquire an interrupt cycle when it sees that the busy signal indicating that U's interrupt cycle is being used is inactive.

EXAMPLES The present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of an interrupt control method according to the present invention, and FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. In addition, as a description of the embodiment, a case where the I / O-2 issues an interrupt request is illustrated.

When the I / O-2 and I / O-n make an interrupt request, the interrupt request signal 11 becomes active and is transmitted to the CPU. CPU
When the interrupt request is accepted, the interrupt acknowledge signal 12
, And outputs timing signals 13 corresponding to I / O-1, I / O-2, ..., I / O-n in synchronization with the interrupt acknowledge signal 12.

Here, I / O-1, I / O-2, ..., I / O-n indicate addresses “1”, “2”, ... Positions corresponding to the number of pulses are time slots t ₁ , t ₂ , ..., T _n .

I / O-1 checks whether the interrupt request in the time slot t ₁ of the timing signal 13 corresponding to the own address "1". At this time, the I / O-1 does not need to acquire the interrupt cycle unless it outputs the interrupt request, and keeps the busy signal 14 inactive.

The I / O-2 checks whether or not there is an interrupt request at the time slot t ₂ of the timing signal 13 corresponding to its own address “2”. At this time, after confirming that the busy signal 14 is inactive and detecting that the self can acquire an interrupt cycle, the busy signal 14 is activated.
After that, the busy signal 14 is held active while the interrupt acknowledge signal 12 is active.

The I / O-n checks whether or not there is an interrupt request at the time slot t _n of the timing signal 13 corresponding to its own address “n”. At this time, the busy signal 14 is already active. Even if an interrupt request is output, it is detected that the interrupt cycle cannot be acquired.

In this way, by connecting each I / O with a common signal and acquiring the interrupt cycle in the time slot corresponding to the address of each I / O, I / O in the middle can be removed. However, it is not necessary to use a special signal relay means.

Also, in one interrupt cycle, one I / O can be selected and processed according to the priority order of the address order, so if the address order is set to the highest priority, the I / O with the highest priority will be given priority. Can be processed.

[Effects of the Invention] As described above, according to the present invention, a common interrupt request signal output from a plurality of I / Os, an interrupt acknowledge signal indicating an interrupt cycle of a CPU, and an interrupt acknowledge signal. By using a timing signal that has a time slot assigned to the addresses of multiple I / Os and a busy signal that indicates that the interrupt cycle of the CPU is being used, In the time slot of the timing signal assigned to the address, it is possible to connect each I / O with a common signal by configuring to acquire the interrupt cycle by judging the busy signal. Even if I / O is removed, there is an effect that no special signal relay means is required.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an interrupt control method according to the present invention, FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a conventional interrupt. FIG. 4 is a block circuit diagram showing an example of the control method, and FIG. 4 is a block circuit diagram showing another example of the conventional interrupt control method. 11 …… Interrupt request signal 12 …… Interrupt acknowledge signal 13 …… Timing signal 14 …… Busy signal

Claims (1)

(57) [Claims] 1. An interrupt request signal that is active when there is an interrupt element from at least one of a plurality of I / Os and that activates an interrupt acknowledge signal that is output from the CPU and that indicates the interrupt cycle of the CPU. In addition, the timing signal is output in synchronization with this interrupt acknowledge signal, and each I / O checks the presence or absence of an interrupt request in the time slot of the timing signal corresponding to its own address in the address order. Is outputting an interrupt request, and acquires an interrupt cycle when it confirms that the busy signal indicating that the CPU interrupt cycle is being used is inactive. Embedded control method.