JPH0436419B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Conventionally, in a data processing device that has multiple operating ports and performs multiplexed processing, timeout detection has conventionally been performed using a common slot. In order to identify when a port timeout occurs, it is necessary to provide a circuit for timeout detection etc. for each port, and when trying to increase the number of ports implemented, the amount of hardware for these circuits etc. There was a problem in that it became large. In order to address this further problem, the present invention discloses a timeout error handling method that can easily identify which of a plurality of ports has caused a timeout error with a small amount of hardware.

[Industrial Field of Application] The present invention relates to control related to timeout error detection in a data processing device that has a plurality of operation ports and receives and processes multiple requests.

[Prior Art] FIG. 5 is a diagram for explaining a conventional timeout error detection circuit, in which 1 is an input/output channel, 2 is a port, 3 is an end code holding circuit, and 4 is a diagram for explaining a conventional timeout error detection circuit.
is a bus, 5 is a timing pulse generation circuit, 6 is a timeout detection circuit, 7 is a port selection circuit, 8 is an operation instruction code decoding circuit, 9 is a main memory start control circuit, 10 is a main memory device, 11 is a main memory termination control The circuit 12 represents a transfer control circuit.

Further, reference numeral e indicates a signal line for reporting an error to the transfer control circuit 12 when an error occurs in each circuit.

[Problems to be Solved by the Invention] In the configuration shown in FIG. 5 described above, each circuit (port selection circuit 7 to main memory termination control circuit 11)
When an error occurs, the error transfer control circuit transmits the error through the signal line indicated by reference numeral e, thereby setting the corresponding error code in the end code of the corresponding port. In this case, since the operation of each circuit in the previous stage is unique to the port selected at that time, it is easy to identify which port caused the error, and the related circuits etc. One set is sufficient for all.

However, regarding timing errors, since timing pulses generated by the timing pulse generation circuit 5 at regular time intervals are used for common time monitoring, Time errors related to events that occur at each port during the time period between pulses) occur simultaneously with a subsequent pulse (after the time that should be a timeout), so it is important to note that time errors occur on any port. In order to be able to identify whether a timeout error has occurred, it was necessary to provide a timeout error detection circuit for each port.

This has caused a problem in that the amount of hardware has increased significantly as the number of multiplexed ports has increased due to the recent trend toward higher integration.

In view of these conventional problems, the present invention enables multiple ports to share signal lines and circuits, thereby reducing the amount of hardware compared to the conventional method even if the number of ports is large. Its purpose is to provide a timeout error handling method.

[Means for Solving the Problems] According to the present invention, this object is achieved by performing multiplexing processing using a plurality of ports operating in synchronization with a common clock pulse, as described in the claims. At the end of each process, the completion result or abnormal termination result is indicated in the completion code and returned to the processing request destination. A register that outputs a port busy signal to indicate that a port is busy, a check pulse generation circuit that outputs check pulse signals of at least the number of ports that are shifted by a fixed time based on a common clock pulse, and a register that outputs a port busy signal that indicates that a port is busy. A signal, a reset signal that notifies the end of the operation of the corresponding port, and one type of check pulse signal are input, and after receiving the port busy signal, a predetermined number of check pulse signals are detected. A logic circuit that outputs a timeout error signal if a reset signal is still not received, an end code generation circuit that outputs an abnormal termination code that indicates that a timeout has occurred on one of the ports, and an end code generation circuit for each port. This is achieved by a timeout error processing circuit characterized in that it is provided with an end code holding circuit that stores an end code corresponding to the processing request destination of the port.

[Embodiment] FIG. 1 is a diagram showing the configuration of one embodiment of the present invention, in which 1 to 12 are the same as those in FIG. 5 described above, and 1
3 represents a timeout detection circuit. Also,
1' to 4' are the same as 1 to 4, respectively.

In Figure 1, processing requests from each input/output channel are handled by setting an operation instruction (function) code and data to one of the four ports for each input/output channel and raising a valid signal. It will start up. Then, the port selection circuit 7 and the operation instruction code decoding circuit 8 are requested to process the main memory device via the main memory activation control circuit 9.

At this time, the port becomes BUSY from the time the valid signal is received until the end code is returned from the transfer control circuit 12 after the processing is completed.

The timing pulse generation circuit 5 generates a timing pulse every 2ms, and the timeout detection circuit 13 uses this to perform monitoring.
If the port is in the BUSY state for the above period, it is assumed that some abnormality has occurred and a timeout error is generated.

FIG. 2 is a diagram showing an example of the relationship of the timeout detection circuits in the above explanation, in which 5 is the same as in FIG. 1, 14 is a check pulse generation circuit, and 15
~18 is a flip-flop, 19 is an AND circuit,
20 represents an OR circuit, and 21 represents a release control section.

In FIG. 2, the timing pulse generation circuit 5
As described above, timing pulses are sent out every 2 ms. The check pulse generating circuit 14 generates pulses shifted by one clock for each port from the pulse, and outputs them as check timing to . When the port is in the BUSY state and this check timing is turned "ON", the TIME STAMP signal is set.
The TIME STAMP signal is normally reset by the release control unit 21 when the port BUSY state is released, but if the BUSY state is prolonged for some reason (for example, a failure in the storage device),
When checking is turned “ON” again even though the TIME STMP signal is still “ON” (the port is in the BUSY state for 2ms or more)
will be treated as a timeout error.

FIG. 3 is a time chart of the timeout detection operation, in which 22 is a timing pulse, 23 _{0 to} 2
3 ₆ and 24 ₀ to 24 ₄ are check pulses, 25
indicates a storage device failure.

As shown in FIG. 3, the number of ports checked for each clock is limited to one specific port.
When a timing error occurs, the error signal and port number can notify the transfer control circuit that a timeout has occurred.

FIG. 4 is a diagram showing an example of the configuration of an end code generation circuit in the transfer control circuit, in which 26 is a flip-flop, 27 is a data holding circuit, 28 is an end code generation circuit, and 29 is an end code holding circuit for each port. represents.

As shown in FIG. 4, in the case of the present invention, a timeout error signal and a port number are obtained from the timeout detection circuit 13 as information, and an end code is generated by an end code generation circuit common to all ports. This is distributed to each port by port number.

The same figure also shows the end code generation circuit of the port selection circuit for comparison, but the other blocks are almost the same.

[Effects of the Invention] As explained above, according to the method of the present invention, there is no need to provide circuits and wiring related to timeout detection for multiple ports corresponding to each port as in the past, and it is not necessary to provide them in common. Since this can be carried out using a single set of circuits, the timeout detection section of a device having a large number of ports, such as a transfer device, can be made compact and economical with a simple configuration and a small amount of hardware. big.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a diagram showing an example of the configuration of a timeout detection circuit, Fig. 3 is a time chart of the timeout detection operation, and Fig. 4 is an end code generation circuit. FIG. 5 is a diagram for explaining a conventional timeout error detection circuit. 1, 1'... Input/output channel, 2, 2'... Port, 3, 3', 29... End code holding circuit,
4, 4'... Bus, 5... Timing pulse generation circuit, 6, 13... Timeout detection circuit, 7...
... Port selection circuit, 8 ... Operation instruction code decoding circuit, 9 ... Main memory start control circuit, 10 ... Main memory device, 11 ... Memory end control circuit, 12 ... Transfer control circuit, 14 ... Check pulse Creation circuit, 1
5-18, 26...flipflop, 19...
AND circuit, 20... OR circuit, 21... Release control section, 22... Timing pulse, 23 ₀ ~
23 ₆ , 24 ₀ to 24 ₄ ...Check pulse, 25
...Storage device failure, 27...Data retention circuit,
28... End code creation circuit.

Claims (1)

[Claims] 1 Multiplex processing is performed using multiple ports that operate in synchronization with a common clock pulse, and at the end of each process, the completion result or abnormal termination result is indicated in the completion code and returned to the processing request destination. In a data processing device configured as follows,
A register that outputs a port busy signal that corresponds to each port and indicates that the port is busy, and check pulse signals of at least more types than the number of ports that are shifted by a fixed time based on a common clock pulse. After receiving the port busy signal, input a check pulse generation circuit that outputs a port busy signal, a reset signal that notifies the end of operation of the corresponding port, and one of the check pulse signals. , a logic circuit that outputs a timeout error signal when a reset signal is not received even after detecting a check pulse signal a predetermined number of times, and an abnormal termination code that indicates that a timeout has occurred on any port. 1. A timeout error processing circuit comprising: an end code generation circuit that outputs an end code, and an end code holding circuit that corresponds to each port and stores an end code sent to a processing request destination of that port.