JP2553573B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a source / source method.
It is suitable for use in forming an offset structure gate of an N ⁺ injection self-aligned field effect transistor in a drain region.

2. Description of the Related Art FIG. 3 shows a conventional method for manufacturing a field effect transistor having an offset structure gate, and FIG.
A method of manufacturing an N ⁺ -implanted self-aligned field effect transistor in a drain region will be described. In FIG. 3, the offset structure gate is formed by a normal photolithography technique. Further, in FIG. 4, the gate after N ⁺ implantation does not have an offset structure.

Problems to be Solved by the Invention In order to form the gate with an offset structure in FIG. 3, mask alignment in the conventional photolithography process is performed, and thus the yield is deteriorated due to misalignment. Further, according to FIG. 4, the gate having the offset structure cannot be formed by the N ⁺ implantation self-alignment method.

In order to solve these problems, in order to solve these problems, for example, a gate used for the N ⁺ implantation self-alignment method of the source / drain region is formed by an insulating film to form a dummy gate, and after N ⁺ implantation, sidewall etching and An offset gate is realized by using one of the second insulating films on the sidewalls of the dummy gate by sidewall deposition, and the offset gate structure and the N ⁺ implantation self-alignment method are simultaneously performed.

By the method for manufacturing a semiconductor device of the present invention, the offset gate structure and the N ⁺ implantation self-alignment method are performed at the same time, which eliminates the need for conventional mask alignment for forming a gate pattern and facilitates formation of sub-micron or smaller gates. The static characteristics and high frequency characteristics of the field effect transistor are improved, and the yield is improved.

Embodiment FIG. 1 shows an embodiment of the present invention.

In FIG. 1 (a), by the conventional photolithography technology,
The active layer 22 is formed on the GaAs semiconductor substrate 21 using the resist as a mask.
To form. In Fig. 1 (b), a SiO ₂ film is formed on the substrate surface.
6000Å deposited, leaving the SiO ₂ film 23 only on the gate part of the field effect transistor (hereinafter referred to as FET), and the SiN film 2 on the entire surface.
000Å is deposited, and the SiN film 26 is left only on the side wall of the SiO ₂ film 23 by reactive ion etching using CF ₄ gas. In FIG. 1 (e), Si ions are implanted at 100 kev, 5 × 10 ¹³ cm ^{-2 using} a dummy gate of SiO ₂ / SiN film as a mask to form an ohmic layer 25 in a self-aligned manner. In FIG. 1 (d), the resist is removed, and annealing is performed under As pressure at 820 ° C. for 15 minutes to deposit a SiO ₂ film 27 of 4000 Å and spin on a resist 28 of 1.5 μm. In FIG. 1 (e), reactive etching is performed with CF ₄ gas to expose the head of the SiN film 26.
In FIG. 1 (f), the SiN film 26 on the source side of the FET is selectively etched and removed by using a normal photolithography technique and plasma etching of CF ₄ gas. After that, the gate electrode 28, the source electrode 29, and the drain electrode 30 are formed, and the FET having the offset structure is completed.

Figure 2 (b) shows the SiN film surface deposition thickness and the SiN left on the sidewall.
FIG. 2A is a schematic diagram showing a process of forming a sidewall film, which shows a relationship with the film thickness of the film.

In FIG. 2, it can be seen that when the deposition rate is 100 Å / min, the variation of the SiN film left on the side wall is smaller, and it is possible to control the film thickness of sub-micron or less by the surface deposition film thickness of the SiN film. This is because the coverage for the SiO ₂ film is poor at a deposition rate of 300 Å / min.

According to the semiconductor device manufacturing method of the present invention, the offset gate structure and the N ⁺ implantation self-alignment method are performed at the same time, which eliminates the need for conventional mask alignment for forming a gate pattern and facilitates the formation of a submicron gate or less. Since it can be formed in the field effect transistor, its transconductance gm is improved by 10%, the gain of high frequency characteristics is improved by 30% or more, and the yield is improved by 20%.

[Brief description of drawings]

1 (a) to 1 (f) are process cross-sectional views showing a method for manufacturing a field effect transistor in one embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are sidewall formation of one embodiment of the present invention. And a characteristic diagram showing the relationship between the surface deposited film thickness of the SiN film and the side wall film thickness, and FIGS. 3 (a) to 3 (d) are steps showing a conventional method for manufacturing an FET having an offset gate structure. Sectional views and FIGS. 4A to 4C are process sectional views showing a method of manufacturing an FET using a conventional N ⁺ implantation self-alignment method. 21 ... GaAs semi-insulating substrate, 22 ... active layer, 23 ... SiO
₂ film, 26 …… SiN film, 27 …… SiO ₂ film, 28 …… gate electrode.

Claims (1)

(57) [Claims] 1. A step of forming a first conductivity type first semiconductor layer on one main surface of a semi-insulating substrate, a step of depositing a first insulating film on a surface of the first semiconductor layer, The step of leaving the first insulating film only in the gate portion, the step of depositing the second insulating film so as to cover the first insulating film, the step of etching the second insulating film, and the first insulating film. Leaving only on the side wall of the film, and using the first and second insulating films as a mask, a second conductive film having the same conductivity type as the first semiconductor layer and a high concentration.
Forming a semiconductor layer, annealing with the first and second insulating films formed, depositing a third insulating film equivalent to the first insulating film, and Spin-on a fourth organic insulating film on the third insulating film; etching the fourth organic insulating film and the third insulating film to expose the head of the second insulating film;
The second formed on the source side of the field effect transistor
Etching the insulating film to form a gate portion window, and forming a gate electrode in the gate portion window,
And a step of etching a third insulating film on the surface of the second semiconductor to form an ohmic electrode.