JP2557551B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a contact formed for connecting an impurity diffusion region on a semiconductor substrate and an upper wiring portion. The present invention relates to a method of burying polysilicon in a hole to reduce a step and form a contact portion.

(B) Conventional Technology As a conventional method of this kind, as shown in FIG. 3, an NSG interlayer insulating layer is formed on a semiconductor substrate 33 having a gate electrode 31 and a source / drain 32 on which sidewalls 30 are formed. After stacking, the direct contact hole 34 is formed, and the high concentration N-type polysilicon layer 36 is formed on the entire surface of the NSG film 35 including the contact hole 34 to form the contact hole 34.
Was filled in, and the polysilicon layer was patterned to form a capacitor lower electrode.

(C) Problem to be Solved by the Invention At this time, the N ₊ polysilicon layer 36 is doped with impurities such as phosphorus and arsenic, and this impurity is subjected to heat treatment for recovering crystal defects. Diffused by
Since the obtained impurity diffusion layer 32a has a diffusion depth Xj that is deeper than the diffusion depth of the source / drain 32 that is the impurity injection layer before the heat treatment, the diffusion of impurities does not occur when making a submicron transistor. There is a possibility that the transistor may reach just below the gate electrode 31 of the transistor, and the transistor is likely to be adversely affected.

It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can prevent the diffusion of the impurity on the semiconductor substrate by suppressing the increase of the diffusion depth of the impurity diffusion region.

(D) Means and Actions for Solving the Problems The present invention provides a contact to an interlayer insulating layer which is laminated on the entire surface of a semiconductor substrate having a gate electrode portion and an impurity injection layer provided between the gate electrode portions. When a hole is provided and polysilicon is embedded in the contact hole,
(I) A polysilicon layer not implanted with impurities is stacked on the entire surface of the interlayer insulating film including the contact hole, and (ii) the polysilicon layer is etched back to leave the polysilicon film only in the contact hole. Let (iii)
An interlayer-insulating film including a polysilicon film is overlaid with a polysilicon layer into which impurities have been substantially implanted, (iv)
Manufacturing of a semiconductor device characterized by performing a heat treatment to convert the impurity-implanted layer into an impurity-diffused region and diffusing the impurity into at least the impurity-implanted polysilicon film in the contact hole from the impurity-implanted layer. Is the way.

That is, according to the present invention, the polysilicon to be buried in the contact hole is deposited by non-dope, and then a heat treatment is applied to diffuse the impurities from the source / drain to the non-dope buried polysilicon film, so that the semiconductor substrate This is to prevent the diffusion of impurities.

In the present invention, the polysilicon layer into which impurities are substantially implanted means that impurities such as phosphorus and arsenic are contained in the range of 10 ¹⁹ to 10 ^20.
It means a highly concentrated polysilicon layer doped with cm ^-3 . This polysilicon layer is used as a part of the upper layer wiring (used as a contact) or as a capacitor lower electrode of the DRAM capacitor after patterning (used as a direct contact).

In the present invention, the heat treatment has a role of (i) converting the impurity-implanted layer into an impurity diffusion region, and (ii) at least diffusing the impurity from the impurity-implanted layer into the buried polysilicon film. Impurities to the polysilicon film can also be diffused from the upper polysilicon layer in which the impurities are implanted. This makes it possible to control the contact resistance to a predetermined value. In addition, in the obtained impurity diffusion region, the order of the impurity doping amount is reduced by about one digit (since the impurity diffuses from the implantation layer into the buried polysilicon film), and thus the diffusion depth can be suppressed.

(E) Example Hereinafter, the present invention will be described in detail based on an example shown in the drawings. The present invention is not limited to this.

FIG. 1 shows a first embodiment of the present invention and shows an example of use for a contact.

In FIG. 1 (d), the N channel MOSFET is arsenic (
⁷⁵ As ⁺⁾ impurities of 10 ²⁰ cm ^-3 doped impurity diffused regions as the source and drain 1 and the gate electrode of polysilicon provided with a SiO ₂ sidewalls 3 through the gate insulating film 2 of SiO ₂ of 4 And a gate electrode portion 20 composed of
Si substrate 5, NSG film 6 with a thickness of 1500Å and BPS with a thickness of 6000Å
The interlayer insulating film 8 made of the G film 7, the contact hole 9 formed in the interlayer insulating film, and the contact hole 9
Embedding the polysilicon film 10 ^a buried ³¹ P ⁺ impurity comprising doped to about 10 ¹⁶ cm ^-3 uniform, which are sequentially stacked thereon, ³¹ P ⁺ impurity in a thickness of 1000Å is about 10 ²⁰ cm
^-3 Doped High Concentration N-type Polysilicon Layer 11 and Thickness
It is the upper layer wiring pattern 12 of 9000Å Al-Si.

 Hereinafter, the manufacturing method will be described.

First, as shown in FIG. 1A, the NSG layer and the BPSG layer are entirely formed on the Si substrate 5 having the gate electrode portion 20 and the impurity injection layer 1a having an impurity doping amount of about 10 ²⁰ cm ^-3. Are sequentially laminated to form a contact hole 9.

Next, a polysilicon layer not implanted with impurities is laminated so as to fill the contact hole 9, and then etched back to leave the polysilicon film 10a only in the contact hole 9 [see FIG. 1 (b)]. .

Then, a polysilicon layer 11 in which a high concentration of impurities is injected is stacked on the entire surface, and then heat treatment is performed at 900 ° C. for 40 minutes [see FIG. 1 (c)].

At this time, the polysilicon layer 11 and the impurity-implanted layer 1a having a doping amount of about 10 ²⁰ cm ⁻³ are respectively formed in the directions of arrows D and F in the figure.
From then on, diffusion of impurities into the polysilicon film 10a starts. At the same time, the melting of the interlayer insulating film 8 is also started.

After that, when heat treatment is applied and diffusion of impurities is completed, a polysilicon film 10 having a contact resistance of about 300Ω (1 μm □) is formed. Further, an Al—Si layer is laminated on the entire surface of the melted interlayer insulating film 8 by sputtering, and then wiring patterning is performed to form the upper wiring 12 [see FIG. 1 (d)].

At this time, the impurity-implanted layer 1a having a doping amount of about 10 ²⁰ cm ^-3 is replaced by the impurity diffusion layer 1 having a doping amount of about 10 ¹⁹ cm ^-3 by heat treatment, and a part of the impurity is directly above the implantation layer 1a. Diffuse into the embedded polysilicon film 10a. That is, as described above, the impurity doping amount of the impurity diffusion layer 1 is reduced by one digit as compared with the impurity implantation layer 1a before the heat treatment. Therefore, in this state, even if the impurity diffusion layer 1 is converted into the impurity diffusion layer 1, there is no possibility that the diffusion of impurities will reach directly under the gate electrode portion 20 as in the conventional case, and therefore, it is possible to prevent the transistor characteristics of the FET from being adversely affected. On the other hand, impurities are diffused from the polysilicon layer 11 into the buried polysilicon film 10 by heat treatment, so that a desired contact resistance can be secured.

FIG. 2 shows a second embodiment of the present invention and shows an example of use for direct contact.

 The manufacturing method will be described below.

First, as shown in FIG. 2A, an NSG film 26 having contact holes 29 opened is formed on a Si substrate 25 having a gate electrode portion 28 and an impurity injection layer 21a.

Next, a polysilicon layer not implanted with impurities is laminated on the entire surface, and then etched back to leave the polysilicon film 30a only in the contact hole 29 [see FIG. 2 (b)].

Then, a polysilicon layer in which a high concentration of impurities is injected is stacked on the entire surface, and heat treatment is performed at 900 ° C. for about 40 minutes to fill the buried polysilicon film 30a with the polysilicon layer 31 in the arrow directions shown by M and N in the figure. Impurities are diffused from the implantation layer 21a to form a buried polysilicon film 30 having a desired contact resistance and source / drain regions (not shown) are formed [see FIG. 2 (c)].

At this time, the polysilicon layer 31 functions as a capacitor lower electrode after patterning.

After that, although not shown, a capacitor insulating film, a capacitor upper electrode, an interlayer insulating film, and an upper wiring pattern are sequentially formed to form an element.

As described above, according to both of the above-described embodiments, the NON-Doped Poly Si
After the deposition, heat treatment is performed to at least secure the contact resistance by diffusing the impurities from the source / drain and suppress the diffusion depth.

(F) Effect of the Invention As described above, according to the present invention, after poly-Si embedded in a contact hole is deposited by non-dope, heat treatment is performed to at least non-dope from the source / drain.
Since impurities are diffused into the buried polysilicon film of, contact resistance can be secured and
This has the effect of suppressing the diffusion depth.

[Brief description of drawings]

1 and 2 are explanatory views of the manufacturing process for explaining the first and second embodiments of the present invention, respectively, and FIG. 3 is a structural explanatory view showing a conventional example. 1 ... Source / drain (impurity diffusion region), 5,25 ...
Si substrate, 6 ... NSG film, 7 ... BPSG film, 8 ... Interlayer insulating film, 9,29 ... Contact hole, 10,30 ... Impurity-doped buried polysilicon film, 10a, 30a. Embedded polysilicon film not doped with impurities, 11, 31 ...
… High-concentration polysilicon layer, 12 …… Upper wiring pattern, 2
0,28 …… Gate section.

Claims (1)

(57) [Claims] 1. A contact hole is provided in an interlayer insulating layer laminated over the entire surface of a semiconductor substrate having a gate electrode portion and an impurity injection layer provided between the gate electrode portions, and polysilicon is provided in the contact hole. At the time of embedding, (i) a polysilicon layer not implanted with impurities is stacked on the entire surface of the interlayer insulating film including the contact hole, and (ii) the polysilicon layer is etched back to form polysilicon only in the contact hole. The film is left, (iii) a polysilicon layer into which an impurity has been substantially implanted is laminated on the entire surface of the interlayer insulating film including the polysilicon film, and (iv) a heat treatment is performed to remove the impurity-implanted layer from the impurities. At the same time as converting to the diffusion region, the impurities are diffused from at least the impurity implantation layer into the polysilicon film in the contact hole where the impurities are not implanted. The method of manufacturing a semiconductor device according to claim.