JP2559945B2 - Bare chip for dot data output - Google Patents

Description

Detailed Description of the Invention

[0001]

This invention relates to a thermal head, LE
The present invention relates to an IC used for driving a printing element or a display element such as D, and particularly to a bare chip for dot data output having a characteristic pad arrangement.

[0002]

2. Description of the Related Art There are various types of bare chips that output dot drive data to a printing (display) element such as a thermal head or a liquid crystal. For example, a driver IC for a thermal head is a signal processing circuit, It consists of a drive circuit, and data is serially in and parallel out.

In a thermal head, the above driver IC is generally mounted on a substrate (for example, a ceramic substrate for a thermal head), and the parallel output of the driver IC and the print dots of the thermal head are paired. . To mount the driver IC on the thermal head substrate, as shown in FIG. 4, the driver IC chip 4 having a plurality of pads 3 is mounted on the conductor pattern 2 formed on the thermal head substrate 1, Bonding pattern 5 and driver I formed on part of pattern 2
Each pad 3 of C4 is wire-bonded with a wire 6.

According to the current technology, it is said that the pitch L1 of the pads 3 of the IC 4 needs to be 100 μm or more, and the distance L2 between the end of the chip and the terminal of the pattern 5 needs to be about 0.7 mm for wire bonding. It is said that Since the pad pitch of the IC has a predetermined limit in this way, for example, when the integration degree of the print dots of the heating element is increased and the number of dots is increased, a plurality of ICs are associated with the dot row. It becomes difficult to arrange them in a horizontal row.

Therefore, driver ICs 4a, 4b, 4c, and 4d having a 32-bit parallel output for driving a 128-dot thermal head, for example, as shown in FIG.
The wiring patterns 2a and 2c for the upper and lower ICs 4a and 4c are led out through the lower portions of the ICs 4a and 4c, respectively, and for the lower ICs 4b and 4d, between the ICs 4a and 4c, and further between 4c and the end portion. Had been derived through.

However, the formation of the wiring pattern by the arrangement of the ICs as described above makes the size of the ICs, for example, 4.8.
If the size is 2.5 mm × 2.5 mm, it is possible to secure a lateral pattern pitch of 100 μm.
Regarding the wiring pattern 2b for the IC4b that passes between C4a and 4c, both are considered to be 1.4 mm in consideration of the 0.7 mm distance for wire bonding of the IC4a, and the distance between the IC4a and 4c is 32 wiring patterns. When passing through, the wiring pattern interval becomes 45 μm pitch, and the pitch of the wiring pattern in the vertical direction is very small with respect to the wiring pattern in the lateral direction, which causes an extreme difference, resulting in imbalance and complicated patterns. there were.

Therefore, in order to eliminate the drawbacks of the wiring pattern becoming complicated and unbalanced, the upper ICs 4a and 4c and the lower ICs 4b and 4d are arranged in a vertically overlapping position as shown in FIG. Wiring pattern 2a,
2b together under the IC4a, same IC4c, 4
It is conceivable that the wiring patterns 2c and 2d of d are led out below the IC 4c.

According to this IC array and pattern arrangement, for example, for an IC size of 4.8 × 2.5 mm,
Even if the distance for wire bonding is 1.12 mm in the lateral direction, it is 6 for the lateral width of 2.5 + 1.12 × 2 = 4.74.
Since four leads are passed, a pitch of about 74 μm can be secured and the pattern pitch in the x (horizontal) direction is substantially close to 100 μm, which facilitates alignment and averaging.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
According to the arrangement of C and the wiring pattern arrangement method, the wiring patterns can be averaged, the wiring patterns can be simplified, and it is possible to connect even to printed dots or the like having a high mounting density, which can be dealt with. However, commonly used drive ICs
For example, for 32 bits, as shown in FIG. 5, one serial input terminal SiT, a plurality of parallel output terminals Po1, ..., Po32, and one more serial output terminal S are provided.
It usually has oT. For convenience of explanation, it is assumed that this type of IC has 4 bits, and the arrangement and pattern arrangement of the ICs shown in FIGS. 6 and 7 are simplified as shown in FIGS. 8 and 9, respectively. According to FIG. 8, serially input data is derived as parallel outputs of 1, 2, 3, and 4, respectively, and is sequentially 5, 6, 7, ..., 16 for each of the ICs 4a, 4b, 4c, 4d. It is possible to serially input and output parallel output up to 1, ..., 16 instantly, and in this case, parallel data can be taken out without any problem. However, in the case shown in FIG. 9, the parallel outputs are 1, 2, 5, 6, 7, 8,
Since it is derived in the order of 3, 4, there is a problem that the parallel output is completely different from the serially input bit order of 1, 2 ,.

Further, the conventional drive IC has only one external input terminal for receiving serial data and one output terminal for outputting serial data, so that various modes of data input cannot be selected according to the application. was there. The present invention has been made in view of the above problems, and for connecting a plurality of ICs to, for example, a print dot portion,
Even in the case where the wiring pattern of each IC is derived through the lower side of each IC, parallel data can be derived in the input order of serial data without causing any deviation, and therefore, the invention can be applied to the one in which the wiring pattern is extremely uniform. Another object of the present invention is to provide a bare chip for dot data output, in which data input / output can be flexibly selected and high density can be achieved.

[0011]

A bare chip for dot data output according to the present invention provides dot drive data to be supplied to a plurality of printing elements and the like outside the chip.
The dot drive data for each of the first and second storage units, which temporarily stores the divided dot drive data, and the dot drive data for each of the first and second storage units are serial data from a circuit outside the chip. And first and second serial input terminals for receiving the dot drive data of the first and second storage sections in the order of input of the serial data.
And a dot signal output terminal for outputting the dot drive data temporarily stored in the first and second storage units to a device outside the chip, the bare chip for dot data output, A first serial input terminal, a dot signal output terminal that receives data from the first storage section, and a first serial output terminal are arranged in order from one end near one side of the chip to the other end, A second serial output terminal, a dot signal output terminal for receiving data from the second storage section, and a second serial input terminal,
The chips are arranged in order from one end portion on the other side facing the one end portion on the one side to the other end portion.

The dot data output bare chip of the present invention can independently input serial data to the first and second storage sections, and output serial data independently from the first and second storage sections. Therefore, when the present invention is applied to an IC and wiring pattern arrangement as shown in FIG. 9, for example, 1, 2, 5, 6, 7, 8, 3,
By inputting the serial data in the order of 4, ..., The parallel data can be arranged and taken out in the order of 1, 2, 5, 6, 7, 8, 3, 4. If the arrangement shown in FIG. 9 is operated as described above, 4a, 4b and 4
It is also possible to use dots c and 4d like one chip to cope with high density of dots.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit block diagram of a thermal head driver IC in a dot data output bare chip according to the present invention. In the figure, the driver IC 21 includes a shift register 22 in which 16 memory cells (stages) D1 to D16 are connected in series, and a shift register D17.
16 to D32, a shift register 23 in which 16 storage cells are connected in series, a latch 24, and a gate circuit from G1 to G32.

The shift register 22 has an input terminal Si1T for serial data and So1T for outputting serial data. Further, parallel data can be output to each bit of L1 to L16 of the latch circuit 24. Similarly to the shift register 22, the shift register 23 has an input terminal Si2T for inputting serial data and an So2T terminal for outputting serial data, and the parallel output is provided to each cell of L17, ... L32 of the latch circuit. It is designed to be latched individually. The latch circuit 24 uses the latch signal applied to the latch signal input terminal LPT to shift register 2
The parallel outputs 2 and 23 are latched and stored in the latch circuit 24. Furthermore, the latch circuit 2
, L32 of 4 outputs parallel output terminals Po through gate circuits G1, ..., G32 when a strobe signal is input to the strobe signal input terminal SBT.
Outputs are respectively derived from 1, Po2, Po3, ..., Po32. PT is the power supply voltage Vc
terminal for supplying c, LGT for logic ground terminal, P
GT is a power ground terminal.

The layout of the external terminals of the driver IC 21 is as shown in FIG.
Two serial data input terminals Si1T and further parallel output terminals Po1, Po2, Po3, ..., Po16 are arranged, and the serial data output terminal So1T of the shift register 22 is arranged at the lowermost end. On the right side, from the upper end, the serial data output terminal S of the shift register 23
o2T or lower, parallel output terminals Po32, ..., Po sequentially
19, Po18, Po17 are arranged downward,
The serial data input terminal Si2T of the shift register 23 is arranged at the lowermost end. That is, the serial data input terminals of the shift registers 22 and 23 are diagonally arranged, and similarly, the output terminals So1T and So2T of the shift registers 22 and 23 are diagonally arranged.

Four driver ICs 21 (21a, 2a)
1b, 21c, 21d) are arranged in the same manner as in FIG. 7, that is, 21a and 21b, 21c and 21d are arranged two by two at the top and bottom (see FIG. 3), and the serial data output terminals So1T and 21b of 21a are serial data. The input terminal Si1T is connected, and the serial data output terminal S of the IC 21b is further connected.
Serial data input terminal Si2 of o1T and IC21b
T is connected, and further the serial data output terminal So2T of the same IC 21b and the serial data input terminal Si2T of the upper IC 21a are connected. When serial data is sequentially input to the serial data input terminal Si1T of the IC 21a from the outside, parallel data is derived at the time when 64 bits of data are input.
Parallel output from Po1 to Po16 of C21a,
Next, the output from Po1 to Po16 of the IC21b, the output from Po17 to Po32 of the IC21b, and finally the output from Po17 to Po32 of the IC21a are derived, and the parallel output from 1 to 64 bits is right. It will be output in the order in which they are sequentially input. Connect IC21c and IC21d in the same way,
Serial data output terminal So2T and IC2 of IC21a
If the serial data input terminal Si1T of 1c is connected,
Data of 1 to 128 bits can be sequentially output in parallel. That is, the same data output as that shown in FIG. 7 can be obtained.

In the above embodiment, the shift registers 22 and 23 are each provided with two 16-bit registers, but it goes without saying that the number of bits can be appropriately selected depending on the application.

[0018]

According to the present invention, n output terminals, 2
Consisting of a first and a second storage section having a divided storage capacity,
First and second serial input terminals and a serial output terminal are connected to the respective storage units. Therefore,
Data can be independently input to and output from the first and second storage sections, flexible data input / output is possible, and an n-bit printing (display) element and a bisected element are provided. Either of them can be selectively driven.

Since the dot data output bare chip of the present invention has independent serial input terminals and serial output terminals for data respectively, two of them are arranged vertically and the input and output terminals are connected appropriately to input. Parallel output data can be taken out in the same order as the data bits. Therefore, the bare chip for dot data output according to the present invention can be applied to the one in which the wiring pattern is connected to the dot portion while passing under the ICs arranged above and below, and the pitch of the wiring pattern is averaged. There is an advantage that patterning can be performed with high precision, a fine pattern can be avoided, and the packaging density of ICs can be increased.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a thermal head driver IC in a dot data output bare chip according to the present invention.

FIG. 2 is a view showing an arrangement of external terminals of the chip of FIG.

FIG. 3 is a view showing a state in which a plurality of chips shown in FIG. 2 are arranged and connected.

FIG. 4 is a perspective view for explaining a connection state between a conventional general driver IC and a substrate of a thermal head.

FIG. 5 is a view showing an arrangement of external terminals of a conventional driver IC.

6 is a drawing showing an example of a wiring pattern using a plurality of ICs of FIG.

FIG. 7 is a drawing showing an arrangement state of an IC and a wiring pattern, which is a premise of the present invention, for increasing the mounting degree of the wiring pattern.

FIG. 8 is a diagram for explaining FIG. 6 in a simplified manner.

FIG. 9 is a diagram for explaining FIG. 7 in a simplified manner.

[Explanation of symbols]

21 chips 22 and 23 shift registers G ₁ , ..., G ₃₂ gate circuits Si1T, Si2T serial data input terminals So1T, So2T serial data output terminals Po1, Po2, ..., Po32 parallel data output terminals

Claims (1)

(57) [Claims] 1. Dot driving data to be supplied to a plurality of printing elements outside a chip is divided into two parts.
1st and 2nd to temporarily save the respective dot drive data
Storage units, first and second serial input terminals that receive dot drive data for each of the first and second storage units as serial data from a circuit outside the chip, and the first and second storage units. The dot drive data temporarily stored in the first and second storage units, the first and second serial output terminals outputting the dot drive data of each unit in the input order of the serial data, a dot data output bare chips and a dot signal output terminal for outputting the said first serial input terminal, data from the first storage unit
Dot signal output terminal for receiving data and the first serial output
Force terminals are sequentially arranged along one side of the chip from one end to the other end , and the second serial output terminal and the data from the second storage section are arranged.
Dot signal output terminal for receiving data and second serial input
The force terminal to face one end of the chip near the one side
A bare chip for dot data output, characterized in that the bare chips are sequentially arranged from one end portion toward the other end portion along the other end portion .