JPH0339429B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to an integrated circuit device for a drive circuit used for driving thermal heads, LEDs, etc.

(b) Prior Art A driver IC for a thermal head etc. consists of a signal processing circuit and a drive circuit, and data is normally input in serial and output in parallel.

Thermal heads generally have the driver IC mounted on a substrate, such as a ceramic substrate for thermal heads, so that the parallel output of the driver IC and the printed dots of the thermal head are arranged in pairs. Driver IC on thermal head board
As shown in FIG. 4, on the conductor pattern 2 formed on the thermal head substrate 1,
Driver IC chip 4 having multiple pads 3
A bonding pattern 5 formed on a part of the conductor pattern 2 and each pad 3 of the driver IC 4 are wire-bonded with a wire 6.

With current technology, the pitch of pad 3 of IC4 is
1 is said to require at least 100 μm, and it is said that the distance l2 between the end of the chip and the terminal of pattern 5 is approximately 0.7 mm for wire bonding.

In this way, there is a certain limit to the pad pitch of ICs, so if the number of dots is increased by increasing the number of dots printed on the heating element, then multiple ICs can be placed in a horizontal line in response to this row of dots. It becomes difficult to arrange them.

Therefore, to drive a 128-dot thermal head, for example, driver ICs 4a, 4b, 4c, and 32-bit parallel outputs are used as shown in FIG.
4d are arranged vertically and IC4a, 4 is provided on the top.
Wiring patterns 2a and 2c for c are respectively
Lead out through the bottom of IC4a and 4c, and
4b and 4d were led out between IC4a and 4c, and further between 4c and the end.

However, forming wiring patterns by placing ICs in this way reduces the size of the IC, for example 4.8 mm.
x 2.5mm, the horizontal pattern pitch can be secured at 100μm, but the IC
Wiring pattern 2 for IC4b passing between 4a and 4c
For b, 0.7mm for wire bonding of IC4a
Considering the spacing of 1.4 mm on both sides, this IC4
If 32 wiring patterns are passed between a and 4c, the wiring pattern spacing will be 45μm pitch,
The pitch of the wiring pattern in the vertical direction is very small compared to the wiring pattern in the horizontal direction, and there is an extreme difference in pitch, resulting in an unbalanced and complicated pattern.

Therefore, in order to eliminate the drawbacks of complicating and unbalanced wiring patterns, the upper ICs 4a and 4c and the lower ICs 4b and 4d are arranged in vertically overlapping positions as shown in Fig. 7, and the wiring pattern of ICs 4a and 4b is Pass both 2a and 2b below IC4a,
Wiring patterns 2c and 2d of IC4c and 4d as well
It is conceivable to derive it through the lower part of IC4c.

According to this IC arrangement and pattern arrangement, for example, if the IC size is 4.8 x 2.5 mm and the wire bond distance is 1.12 mm in the horizontal direction, it is 2.5 +
64 leads will be passed through the width of 1.12 x 2 = 4.74, and a pitch of approximately 74 μm can be secured x
The pattern pitch in the (horizontal) direction is approximately close to 100 μm, making positioning and averaging easy.

(c) Problems to be Solved by the Invention According to the IC arrangement and wiring pattern arrangement method shown in FIG. 7 above, the wiring patterns are averaged,
The wiring pattern can be simplified, and it can be connected to printed dots with high packaging density.

However, for commonly used drives
For example, in the case of a 32-bit IC, as shown in Figure 5, the IC has one serial input terminal SiT, multiple parallel output terminals Pol, ..., Po32, and one serial output terminal SoT. is normal. For convenience of explanation, this type of IC is assumed to be 4 bits, and the IC arrangement and pattern arrangement shown in FIGS.
It becomes as shown in FIG. According to Fig. 8, the serially input data are 1, 2, and 2, respectively.
Derived as parallel outputs of 3 and 4, each IC4
For a, 4b, 4c, 4d, respectively,
5, 6, 7, . . . , 16 can be serially input and 1, . However, in the case shown in Figure 9, the parallel outputs are 1, 2, 3,
The problem is that the bit order is derived in the order of 6, 7, 8, 3, 4, resulting in a parallel output that is completely different from the serially input bit order of 1, 2, . . . , 16.

Furthermore, in conventional integrated circuit devices for driving circuits, the shift register for inputting and storing data has only one external input terminal and one output terminal.
There was a problem in that it was not possible to select various data input modes.

This invention has been made by focusing on the above-mentioned problem, and even in the case where the wiring pattern of each IC is led out through the bottom of each IC to connect a plurality of ICs to the printed dot part, the serial data cannot be transmitted. Parallel data can be derived without any deviation in the input order, and therefore it can be applied to devices with extremely uniform wiring patterns, and the integrated circuit device for the drive circuit can flexibly select data input/output. is intended to provide.

(d) Means and effects for solving the problem The integrated circuit device for a drive circuit of the present invention has n (n: even number) output terminals for connection to a circuit outside the chip, and these n output terminals. The circuit has n drive circuits each outputting a drive signal individually, and each has an n/2 bit storage stage, and data is input serially, and a parallel output is input to each of the drive circuits. and a shift register, and each of the two shift registers is provided with a serial input terminal capable of inputting serial data from the outside and a serial output terminal capable of serially outputting data to the outside. There is.

Since the integrated circuit device for a drive circuit of the present invention can independently input and output serial data to two shift registers, for example, when an IC and wiring pattern arrangement as shown in FIG. 9 is applied,
By inputting serial data in the order of 1, 2, 5, 6, 7, 8, 3, 4, ..., extracting parallel data in the order of 1, 2, 5, 6, 7, 8, 3, 4. becomes possible. In addition, serial input terminals and serial output terminals for the two shift registers are provided individually, so you can easily select between driving n elements and driving n/2 elements. can.

(E) Embodiment FIG. 1 is a circuit block diagram of an integrated circuit device for a driving circuit showing one embodiment of the present invention. In the figure, a driving integrated circuit device 21 includes a shift register 22 in which 16 memory cells (stages) from D1 to D16 are connected in series, and a shift register 23 in which 16 memory cells from D17 to D32 are connected in series. It consists of a latch 24 and gate circuits G1 to G32.

The shift register 22 has an input terminal Si1T for serial data, uses a So1T terminal for outputting serial data, and can output parallel data to each bit of L1 to L16 of the latch circuit 24. Like the shift register 22, it has an input terminal Si2T for inputting serial data and a So2T terminal for outputting serial data, and the parallel output is provided by L17 of the latch circuit,
..., L32 are individually latched. The latch circuit 24 is configured to latch store each of the parallel outputs of the shift registers 22 and 23 in the latch circuit 24 by a latch signal applied to the latch signal input terminal LPT. Furthermore, when a strobe signal is input to the strobe signal input terminal SBT, each bit output of L1,..., L32 of the latch circuit 24 is output to the gate circuit G1,...,
Parallel output terminals Po1, Po2,
Outputs are derived from Po3, ..., Po32, respectively. In addition, PT is the terminal that supplies the power supply voltage Vcc, LGT is the logic ground terminal,
PGT is a power ground terminal.

The arrangement of the external terminals of the integrated circuit device 21 for the drive circuit of this embodiment is as shown in FIG.
Si1T, and the following parallel output terminals Po1, Po
2, Po3, ..., Po16 are arranged, and the serial data output terminal So1 of the shift register 22 is placed at the bottom.
T is placed. Also, on the right side, from the top end, the serial data output terminal So2 of the shift register 23
Parallel output terminal Po32,...,Po
19, Po18, and Po17 are arranged in a downward direction, and the serial data input terminal Si2T of the shift register 23 is provided at the bottom end. That is, the serial data input terminals of the shift registers 22 and 23 are diagonally arranged, and the output terminals So1T and So of both shift registers 22 and 23 are arranged diagonally.
2Ts are also arranged diagonally.

The four drive circuit devices 21 of this embodiment, namely 21a, 21b, 21c, and 21d, are arranged in the same manner as shown in FIG.
Place 1b, 21c and 21d (see Figure 3),
Serial data output terminal Si1T of 21a and 21b
Connect the serial data input terminal Si1T of IC21b, and also connect the serial data input terminal Si2 of the same IC21b to the serial data output terminal So1T of IC21b.
Furthermore, the serial data output terminal So2T of the IC 21b and the serial data input terminal Si2T of the upper IC 21a are connected. Then, when serial data is sequentially input from the outside to the serial data input terminal Si1T of IC21a, when the parallel data is derived when 64 bits of data have been input, the output terminal is from Po1 of IC21a from the left side.
Parallel output up to Po16 and then IC2
Same as the output from Po1 to Po16 of 1b.
The outputs from Po17 to Po32 of IC21b and finally the outputs from Po17 to Po32 of IC21a are derived, and parallel outputs from 1 to 64 bits are output in the order in which they were input from the right. Connect IC21c and IC21d in the same way, and connect IC21a's serial data output terminal So2T.
By connecting the serial data input terminal Si1T of IC21c to the serial data input terminal Si1T of IC21c, data of 1 to 128 bits can be sequentially output in parallel. That is, data output similar to the data output shown in FIG. 7 can be obtained.

In addition, in the above embodiment, the shift register 2
Two bits 2 and 23 are provided, each having 16 bits, but it goes without saying that the number of bits can be selected as appropriate depending on the application.

(f) Effect of the invention According to this invention, n (even number) output terminals,
For n drive circuits, two shift registers are provided, each consisting of an n/2-bit storage stage and having individual serial input terminals and serial output terminals, and the parallel outputs of these two shift registers are , is input to each drive circuit, so 2
Data can be input to and output from each shift register independently, allowing flexible data input/output, and it is possible to selectively drive either n elements or n/2 elements. .

For example, if the integrated circuit device for a drive circuit of the present invention is applied to a device in which two ICs (integrated circuit devices) are arranged one above the other, each has an independent data serial input terminal and serial output terminal. By appropriately connecting the input/output terminals, parallel output data can be extracted in the same order as the input data bits.

Therefore, the integrated circuit device of the present invention can be applied to a device in which a wiring pattern is connected to a dot portion by passing under ICs arranged above and below, and the pitch of the wiring pattern is averaged, resulting in high accuracy. It has the advantage of being able to be patterned quickly, avoids the need for fine patterns, and can increase IC packaging density.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a driving integrated circuit device showing one embodiment of the present invention, FIG. 2 is a diagram showing the arrangement of external terminals of the integrated circuit device, and FIG.
FIG. 4 is a perspective view illustrating the connection state between a conventional general integrated circuit device and a thermal head substrate, and FIG. is a diagram showing the arrangement of external terminals of a conventional integrated circuit device for driving circuits, Fig. 6 is a diagram showing an example of a wiring pattern of a conventional IC using multiple ICs, and Fig. 7 is a diagram showing a further implementation of the same wiring pattern. Figures 8 and 9 are diagrams showing the layout of IC and wiring patterns, which are the premise of this invention to improve the performance.
The figures are diagrams for explaining the simplified versions of FIGS. 6 and 7, respectively. 21: Chip, 22, 23: Shift register,
G ₁ ,...,G ₃₂ : Gate circuit, Si1T, Si2T: Serial data input terminal, So1T, So2T: Serial data output terminal, Po1, Po2,..., Po3
2: Parallel data output terminal.

Claims (1)

[Claims] 1. n (n: even number) output terminals for connection to circuits outside the chip, and to these n output terminals,
n drive circuits each outputting a drive signal individually, and two shift registers each having an n/2 bit storage stage, into which data is serially input, and whose parallel output is input to each of the drive circuits. and a drive characterized in that each of the two shift registers is provided with a serial input terminal capable of inputting serial data from the outside and a serial output terminal capable of serially outputting data to the outside. Integrated circuit device for circuits. 2. One of the shift registers has an output terminal for n/2 bit parallel output arranged along one side of the chip, and the output terminal for parallel output of the other shift register is arranged opposite to said one side. The integrated circuit device for a drive circuit according to claim 1, which is arranged along the other side. 3. The integrated circuit device for a drive circuit according to claim 1, wherein the two shift registers have respective serial input terminals and serial output terminals arranged diagonally to each other.