JP2586653B2 - Trigger circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trigger circuit, and more particularly, to a trigger circuit capable of outputting a trigger signal based on a level change of a measurement signal.

<Prior Art> The level of a signal M of a measurement object whose level originally changes gently suddenly changes as shown in, for example, part A of FIG. 4 due to the occurrence of some abnormality in the measurement object. There is.

In performing the measurement by paying attention to the portion A where the level changes rapidly, it is necessary to detect such a sudden level change and output a trigger signal.

Conventionally, as a method of detecting such a level change and generating a trigger signal, for example, as shown in FIG. 4, a preset reference level Vref is compared with a level of a measurement signal M, and a rise of the measurement signal M is measured. Alternatively, a fall is also determined.

<Problems to be solved by the invention> However, in such a method, for example, the reference level
Assuming that a trigger occurs on Vref and falling,
Not only the time t ₂ associated with the part A, also becomes a trigger is output at time t ₁ the same condition is satisfied, it ended up mistaking trigger at this time t ₁ as a trigger at time t ₂ There is a risk that accurate measurement cannot be performed.

The present invention focuses on such a point, and an object of the present invention is to provide a trigger circuit that reliably detects a sudden level change and outputs a trigger signal.

<Means for Solving the Problems> A trigger circuit according to the present invention comprises: a data memory for storing measurement data; a first address generator for outputting an address for writing data to the data memory; A second address generator for outputting an address for reading data stored in the first address generator; a first data written to a data memory in accordance with an address output from the first address generator; A calculator for calculating the absolute value of the difference between the second data read from the data memory according to the address output from the address generator; and comparing the output data of the subtractor with the reference level data to trigger a comparison result. A comparator that outputs the signal as a signal; and a register that stores reference level data input to the comparator. And outputs the address alternately to said data memory from the address generator and the second address generator.

<Operation> According to the trigger circuit of the present invention, a trigger is generated when the difference between the current data and the data before a certain period of time changes to a predetermined reference level or more.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, measurement data MD input to input terminal 1
Is stored in the data memory 3 in accordance with the write address W output from the first address generator 2 as write data WD, and is also applied to one input terminal of the subtractor 4. The data stored in the data memory 3 is
Is read out to the other input terminal of the subtractor 4 as read data RD according to the read address R output from the address generator 5. The subtracter 4 subtracts the absolute value of the difference between the write data WD written in the data memory 3 and the read data RD read from the data memory 3, and
SD is input to one input terminal of the comparator 6. The reference level data RED stored in the register 7 is input to the other input terminal of the comparator 6. The comparator 6 compares the operation result SD of the subtractor 4 with the reference level data RED. For example, when SD ≧ RED, the comparison result is output as a trigger signal TG.

FIG. 2 is a timing chart showing the operation of such a circuit. In the figure, (a) is an address input to the data memory 3, which is a write address (W, W + 1,...) Output from the first address generator 2 and output from the second address generator 5. Read address (R, R +
1, ...) are input alternately. (B) is write data WD written to the data memory 3 in accordance with the write address W and input to one input terminal of the subtractor 4, and (c) is data data 3 in accordance with the read address R.
Is read data RD read from the other input terminal of the subtracter 4 from the input terminal. Here, the time relationship between addresses is
The read address R is output after the write address W is output. The data previously written in the data memory 3 is read out as the read data RD in accordance with the subsequently input read address RD. (D) is the output data SD of the subtractor 4. The subtracter 4 outputs the absolute value of (AB), where A is the write data WD and B is the read data RD.
(E) is a trigger TG output from the comparator 6. For example, “M
Assuming that "AX" is stored, the trigger data TG in that section goes high when the output data SD of the subtractor 4 satisfies the condition of SD≥MAX. Then, an operation for ending the data acquisition, for example, is started by the H-level trigger TG.

FIG. 3 is a waveform chart showing an example of such an operation. Here, the difference between the write address W and the read address R alternately output from each of the address generators 2 and 5 means a certain time T. That is, the current data A is written to the data memory 3 according to the write address W, and the data B before the time T is read from the data memory 3 according to the read address R.

With this configuration, a level change within a predetermined time is detected and a trigger is output, and a sudden level change can be reliably detected and a trigger can be generated.

Such a trigger circuit monitors, for example, the temperature and pressure of the measurement target system, detects a sudden level change when any of these abnormalities occur, and detects the sudden change in level and simultaneously performs other data acquisition on other channels or measuring instruments. It is effective to trigger and analyze those data to find the cause of the abnormality.

Further, it can be used as an alarm for notifying that a sudden level change has occurred.

<Effects of the Invention> As described above, according to the present invention, it is possible to realize a trigger circuit that reliably detects a sudden level change and outputs a trigger signal with a relatively simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a waveform diagram showing the operation of FIG. 1, and FIG. It is a waveform diagram which shows operation | movement. 1 ... input terminal, 2 ... write address generator, 3 ...
Data memory, 4 ... Subtractor, 5 ... Read address generator, 6 ... Comparator, 7 ... Register.

Claims (1)

(57) [Claims] 1. A data memory for storing measurement data, a first address generator for outputting an address for writing data to the data memory, and an address for reading data stored in the data memory A second address generator that outputs the first data written to a data memory in accordance with an address output from the first address generator;
A subtractor for calculating the absolute value of the difference between the second data read from the data memory in accordance with the address output from the address generator, and comparing the output data of the subtractor with the reference level data to obtain a comparison result. A comparator that outputs a trigger signal; and a register that stores reference level data input to the comparator. The first address generator and the second address generator output addresses alternately to the data memory. A trigger circuit.