JP2587481B2 - Logic simulation equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation system, and more particularly, to a logic simulation system for leveling a logic simulation of a circuit model including feedback.

[Conventional technology]

Conventionally, in this type of logic simulation method, execution of logic simulation of a circuit model including feedback is realized by executing logic simulation from a minimum level to a maximum level a plurality of times.

[Problems to be solved by the invention]

In the above-described conventional logic simulation method, the entire process from the minimum level to the maximum level of the circuit model is executed a plurality of times during the execution of the logic simulation of the circuit model including the feedback. There is a drawback that portions other than the process to be executed are executed in a meaningless and redundant manner, and the execution time of the logic simulation increases.

In view of the above, an object of the present invention is to realize a logic simulation of a feedback in a circuit model by executing only a process affected by feedback a plurality of times, and to perform a logic simulation by repeating all the conventional processes. An object of the present invention is to provide a logic simulation method that minimizes an increase in simulation execution time.

[Means for solving the problem]

A logic simulation apparatus according to the present invention is a logic simulation apparatus for performing a logic simulation of a circuit model including a feedback by leveling, wherein execution level management means for managing which level in the circuit model is to be executed; Simulation executing means for executing a logic simulation for one level in the circuit model designated by the level management means, and whether or not a previous result is affected by a simulation result of the logic simulation executed by the simulation executing means An execution result determining means for determining whether the previous level is affected by the execution result determining means, and returning to the level having the largest return width among the affected levels to execute the simulation. Run level tube And a determination result evaluation means for instructing the means.

[Action]

In the logic simulation method according to the present invention, the execution level management means manages which level in the circuit model is to be executed, and the simulation execution means executes the logic simulation for one level in the circuit model specified by the execution level management means. Executing, the execution result determining means determines from the simulation result of the logic simulation executed by the simulation executing means whether or not the previous level is affected; If it is determined that there is an effect on the target, evaluate which level should be returned from among the affected levels.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a logic simulation system according to one embodiment of the present invention. The logic simulation method according to the present embodiment includes an execution level management unit 1,
Simulation executing means 2 and execution result determining means 3
And determination result evaluation means 4.

The execution level management means 1 is a means for instructing the simulation execution means 2 on which level in the circuit model a the logic simulation is to be executed by the level value b.

The simulation execution means 2 is a means for performing a logic simulation at the level specified by the execution level management means 1 and outputting a simulation result c.

The execution result determination means 3 is a simulation execution means 2
It is determined from the simulation result c whether or not the previous level is affected (ie, whether or not the input value of the previous level changes), and if so, the level of the affected level is determined. The value d is used as the evaluation result evaluation means 4
Output means.

The determination result evaluation means 4 is based on the level value d output from the execution result determination means 3 and is a level value e of a level having the largest return width among the levels affected.
Is sent to the execution level management means 1 to request a return of the level.

Figure 2 shows an example of a circuit model a including a feedback, assumed to be composed of five levels of _{A 1, A 2, A 3} , A 4 and A _5. B ₁₁ , B ₁₂ , B ₁₃ , B ₂₁ , B ₂₂ , B
₃₁ , _B32 , _B41 , _B42 and _B51 are constituent elements of each level.

Next, the operation of the logic simulation method according to the present embodiment configured as described above will be described.

First, run-level management unit 1 instructs the execution of logic simulation of the level A ₁ in the simulation executing unit 2 by the level value b.

Simulation means 2 outputs the simulation result c perform functional simulation of level A ₁ indicated by the level value b from the execution level management unit 1.

The execution result determination means 3 is a simulation execution means 2
Does not change the input value of the previous level, it is determined that there is no level to return to, and the level value d of the level to return to is not output.

The judgment result evaluating means 4 does not output the level value d of the level to be returned from the execution result judging means 3 and does not request the execution level managing means 1 to return the level. As a result, logic simulation of the component B _11, B ₁₂ and B ₁₃ level A ₁ is completed.

Then, run-level management unit 1, a level to be executed next the level A _2, and then execute the logic simulation by repeating the same operation.

After logic simulation of level A ₃ is performed in the same manner, the execution level management unit 1 and instructs the execution of logic simulation of level A _4, the simulation execution means 2, the level A ₄ of the component B ₄₁ and B ₄₂ A logic simulation is performed, and a simulation result c is output.

Execution result determining unit 3, a simulation result if c (output value of the component B ₄₁ and B ₄₂₎ is determined to give a change in the input value of Level A ₂ and A _3, level A ₂ and
And outputs as a determination result the level value d of A _3.

The judgment result evaluation means 4 determines the level based on the level value d.
Evaluates the return width A ₂ and A _3, and outputs a more return greater level A ₂ of the level value e of width, it requests the level return run level management unit 1 to the level A _2.

Run-level management unit 1 instructs the execution of logic simulation of the next level A ₂ receives the level value e to the simulation execution means 2 by the level value b. Therefore, the logic simulation of the levels A ₂ , A ₃ and A ₄ is performed again.

If the simulation result c of logic simulation of the level A ₄ gives only change in the input value of Level A ₃ without affecting the input value of Level A _2, the execution result determining unit 3
Outputs a level value d of level A ₃ as a determination result.
Thus, taking place the process similar to that described above, so that the logic simulation of level A ₃ and A ₄ are repeated.

Then, if the simulation result c of logic simulation of the level A ₄ no longer gave a change in the input value of Level A ₂ and A _3, the execution result determining unit 3, no level to return the determined level value d Is not output. As a result, the judgment result evaluation means 4 does not request the execution level management means 1 to return the level, and the execution level management means 1
A level to be executed next A _5, by repeating the same operation, and terminates the logic simulation of the entire circuit model a.

Figure 3, when the logic simulation system of the present embodiment a circuit model a shown in FIG. 2 and logic simulation, once the level A _2, execution sequence logic simulation is completed back twice the level A ₃ FIG.

〔The invention's effect〕

As described above, the present invention provides an execution level management unit,
By providing the simulation executing means, the execution result judging means and the judgment result evaluating means, the logic simulation of the feedback in the circuit model can be realized by executing only the steps affected by the feedback a plurality of times. This has the effect of minimizing the increase in the execution time of the logic simulation caused by repeating all the steps.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic simulation system according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a circuit model including feedback, and FIG. FIG. 3 is a diagram illustrating an execution sequence of a logic simulation of the circuit model shown in FIG. 2; In FIG, 1 ...... execution level management unit, 2 ...... simulation execution unit, 3 ...... execution result determining means 4 ...... determination result evaluation unit, A ₁ to A ₅ ...... level, a ...... circuit model, B _{11 to} B ₅₁ ... Constituent elements, b, d, e... Level values, c... Simulation results.

Claims (1)

(57) [Claims] 1. A logic simulation apparatus for performing a logic simulation of a circuit model including feedback by leveling, wherein an execution level management means for managing which level in the circuit model is to be executed, and an instruction by the execution level management means. Simulation execution means for executing a logic simulation for one level in the circuit model obtained, and an execution result for judging whether or not an earlier level is affected from a simulation result of the logic simulation executed by the simulation execution means A determination unit; and if the execution result determination unit determines that the previous level is affected, the execution level management unit returns to the level having the largest return width among the affected levels and executes the simulation. Judgment to instruct A logic simulation device comprising: a result evaluation unit.